WO1999062049A1 - Synthetiseur d'images - Google Patents

Synthetiseur d'images Download PDF

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Publication number
WO1999062049A1
WO1999062049A1 PCT/JP1998/002348 JP9802348W WO9962049A1 WO 1999062049 A1 WO1999062049 A1 WO 1999062049A1 JP 9802348 W JP9802348 W JP 9802348W WO 9962049 A1 WO9962049 A1 WO 9962049A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
circuit
signal
color
output
Prior art date
Application number
PCT/JP1998/002348
Other languages
English (en)
Japanese (ja)
Inventor
Kouji Sakamoto
Soichiro Maita
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to JP2000551377A priority Critical patent/JP3804915B2/ja
Priority to PCT/JP1998/002348 priority patent/WO1999062049A1/fr
Publication of WO1999062049A1 publication Critical patent/WO1999062049A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N9/00—Details of colour television systems
    • H04N9/64—Circuits for processing colour signals
    • H04N9/68—Circuits for processing colour signals for controlling the amplitude of colour signals, e.g. automatic chroma control circuits
    • H04N9/69—Circuits for processing colour signals for controlling the amplitude of colour signals, e.g. automatic chroma control circuits for modifying the colour signals by gamma correction

Definitions

  • the present invention relates to an image synthesizing apparatus and, more particularly, to an effective technique used for synthesizing and displaying characters and graphics on a television screen of a satellite broadcast.
  • Japanese Patent Laid-Open No. Hei 6-2766434 discloses an image synthesizing method for synthesizing a CG (computer graphics) image with a natural image such as a television image. On the other hand, it converts the nonlinear characteristics of the diode or the CG image signal into AZD signals, digitally corrects them, and D / A converts them to combine them with television images.
  • a television receiver that receives multi-channel satellite broadcasting such as 100 channels displays channel information on a screen and selects a specific channel from the displayed channel information.
  • multi-channel satellite broadcasting such as 100 channels
  • CRT Cathod -Ray Tube
  • CRT Cathod -Ray Tube
  • an L-correction corresponding to the CRT nonlinear characteristic is performed based on a digital color one-pixel data output from a signal source circuit that generates digital color one-pixel data, and the ⁇ -corrected output signal is output.
  • a data conversion circuit for selectively performing data conversion according to the signal form to be combined is provided, and the image signal to be displayed on the CRT screen and the image data passed through the data conversion circuit are converted. De-Evening synthesis circuit
  • FIG. 1 is a schematic block diagram showing one embodiment of an image synthesizing apparatus according to the present invention.
  • FIG. 2 is a block diagram showing another embodiment of the image synthesizing apparatus according to the present invention.
  • FIG. 3 is a block diagram showing one embodiment of an error correction circuit used in the image synthesizing apparatus according to the present invention
  • FIG. 4 is a block diagram showing another embodiment of the key correction circuit used in the image synthesizing apparatus according to the present invention.
  • FIG. 5 is a timing chart for explaining the operation of the correction circuit of FIG. 4,
  • FIG. 6 is a timing chart for explaining the operation of the key correction circuit of FIG. 4,
  • FIG. 7 is a characteristic diagram for explaining the operation of the correction circuit shown in FIG. 3 or FIG.
  • FIG. 8 is a block diagram of an embodiment of a satellite broadcast receiving apparatus using the image synthesizing apparatus according to the present invention.
  • FIG. 8 is a block diagram of an embodiment of a digital satellite broadcast receiving apparatus using the image synthesizing apparatus according to the present invention.
  • the digital satellite broadcast receiving apparatus of this embodiment is roughly composed of a receiving section 100, a system control section 200, an MPEG video section 300, a color encoder 20 and a CRT display apparatus 30.
  • the receiving section 100 is a tuner section that selects only the radio wave of the required frequency from the satellite broadcasting antenna, and a demodulation section such as QPSK (Quadrature Phase Shift Keying) that extracts the digital signal from the received radio wave. It consists of a correction unit that performs error correction processing on the converted digital data,
  • the system control unit 200 is composed of a DEMUX (demultiplexer) unit and a CPU (central processing unit; microprocessor) for controlling the DEMUX.
  • the DEMUX is a digital signal transmitted from the reception unit 100. Selectively distributes a plurality of video and audio program information, system control information, and information accompanying the broadcast, which are bucket-multiplexed with the issue.
  • the MPEG video unit 300 includes an MPEG 2 decoder (including a frame memory), an OSD (On 'Screen' Display) decoder and a mixing unit according to the present invention.
  • the MPEG-2 decoder decodes the MPEG image from the bit stream output from the DEMUX and reproduces the first video signal.
  • the bit stream output from the DEMUX The audio program information is also included in the program, and the audio signal is reproduced by the MPEG 2 decoder (not shown).
  • a second video signal is generated as an OSD by supplying data such as character information from the CPU to the OSD decoder.
  • the mixing unit combines the first video signal and the second video signal and outputs a new third video signal.
  • the color encoder 20 can be displayed on the CRT display 30.
  • the third video signal is converted into an analog combo signal or a component signal.
  • FIG. 1 is a block diagram of an embodiment of the image synthesizing apparatus according to the present invention.
  • the image synthesizing apparatus of this embodiment constitutes the MPEG video section 300 shown in FIG. 8 and is not particularly limited, but is formed on the same semiconductor substrate.
  • the bit stream of the image coded and output from the DEMUX is input to the MPEG2 decoder 1, where it is decoded, and the image of the luminance signal Ym and the color difference signals Cbm and Crm is obtained. Detaka ⁇ obtained.
  • two types of data formats can be selected corresponding to the color encoder that forms the display signal of the CRT display device.
  • a matrix circuit for converting the luminance signal Y m and the color difference signals C bm and C rm into RGB three primary color signals Rm, Gm and Bm, and the three primary color intensity signals R M , G m and B m or A selector 3 for selecting and outputting one of the image data Ym, Cbm, and Crm output from one of the MPEG-2 decoders,
  • the selector 3 outputs the luminance signal Y m and the color difference signals C bm and C rm output from the MPEG 2 decoder 1 or the output from the matrix circuit 2 by the control signal CTRL output from the parameter register 5.
  • the correction data supplied to the color correction circuit 12 is the same as the color data of the RG color. In the evening, there is a point.
  • the OSD decoder 8 generates the RGB color data of the three primary colors based on the character tf report from the CPU or the like, whereas the image data from the MPEG decoded data 1
  • two types of data formats by the selector 3 are prepared, and the output of the correction circuit 12 synthesized by the mixing circuit (data synthesizing circuit) 4 and the output format corresponding to the two are also provided.
  • the inverse matrix 13 and the selector 14 are provided in order to reduce the number of colors.
  • the three primary colors that have been corrected, ie, R (a), G (7) and B (7) are converted by the inverse matrix 13
  • the corrected luminance signal Y (a), the color difference signal Cb (a), and the color difference signal Cr (a) are converted to the corrected luminance signal Y (a), and the selector 14 converts the luminance signal Y (7) and the color difference signal Cb (A), C r (a) and Mihara corrected Karade - evening R (r), thereby selectively outputting the G (r) and B (r).
  • the selector 14 also corresponds to the data format (Ym, Cbm, and Crm) or (Rm, Gm, and Bm) selected by the selector 3 by the control signal CTRL output from the parameter register 5.
  • the data format Y (r) and one of Cb (a) and Cr (7) or R (a), G (a) and B (r) are output.
  • FIG. 2 is a block diagram showing another embodiment of the image synthesizing apparatus according to the present invention.
  • two types of data are also provided on the OSD decoder side. —A function to generate signals in the evening format will be added. I mean
  • one pixel data is generated by using the first memory 7 for storing the bit map and the second memory 9 for storing the color data of each bit.
  • the CPU stores the 0SD image bitmap data to be displayed on the first memory 7.
  • the OSD decoder 8 for storing the bullet data for specifying the color to be displayed in the second memory 9 corresponds to the operation of the MPEG 2 decoder 1 in other words, in other words, the raster scan type of the CRT screen.
  • the bitmap data of the first memory 7 is read out, the data is decoded, and the second memory 9 is accessed to form a data line.
  • the color data the above two types of data formats Y / R, CbZG, and CrZB are formed. ,
  • the output section of the 0 SD decoder is provided with a matrix 10 and a selector 11. That is, as described above, the key correction circuit 12 performs key correction on the three primary colors — data RG #. Therefore, when the luminance signal ⁇ and the color difference signals Cb and Cr are obtained by the above 0 SD decoder, the three primary colors converted by the matrix 11 by the selector 11 are selected. It is.
  • the selector 11 is also controlled by the control signal CTRL from the parameter 5 similarly to the selectors 3 and 14.
  • the operation for outputting the color format data in RGB format to the color encoder 20 is as follows.
  • MP EG 2 YmC b mC rm format formed by decoder 1
  • the color data is the three primary color data of RmGmBm passed through the matrix 2 and the selector 3.
  • the above MP EG 2 decoded data is mixed with the above OSD data. Format must be matched; 0
  • To generate SD data the bitmap data of the 0 SD image to be displayed from the CPU 6 is stored in the first memory 7 as described above.
  • the second memory 9 stores the palette data.
  • the SD decoder 8 decodes the bit map data stored in the first memory 7 and reads the corresponding palette from the second memory circuit 9.
  • the RGB components of this ballet become the OSD data, and the selector 11 selects the path through which matrix 10 was bypassed and inputs it to the key correction circuit 12.
  • the key correction circuit 12 selects the CRT display device. Color correction having characteristics opposite to the light emission characteristics is performed, and color data R ( 7 ) G (a) and B (a) with corrected RGB signal levels are formed.
  • the corrected color data R (r) G (a) and B ( 7 ) select the signal bypassing the inverse matrix circuit 13 in the selector 14 and send it to the mixing circuit 4.
  • the MPEG 2 data and the OSD data are combined to generate a new video signal and output to the color encoder.
  • the operation for outputting the color data in the YCbCr format to the color encoder 20 (not shown) is as follows.
  • the YmC bmC rm format color data formed by the MPE G 2 decoder 1 is output by the selector 3 to bypass the matrix circuit 2 and output the YmCbmC rm color data.
  • the MPEG data is mixed with the above-mentioned MPEG 2 decoded data.
  • ⁇ SD data must also match the above-mentioned MPEG 2 decoded data—evening side output format.
  • ⁇ To generate SD data the bit of OSD image to be displayed from CPU 6 as above The map data is stored in the first memory 7, the pallet data is stored in the second memory 9, the OSD decoder 8 decodes the bit map data stored in the first memory 7. Then, the corresponding palette is read from the second memory circuit 9.
  • YCbCr is stored in this bucket, it becomes 0 SD data, and the selector 11 selects the path through the matrix 10. Then, the data is converted into the RGB format and input to the key correction circuit 12. 7 In the correction circuit 12, correction is performed having characteristics opposite to the light emission characteristics of the CRT display device, and the color data R (r) G (a) and B (a) having the corrected RGB signal levels are obtained. It is formed
  • the corrected color values R (7), G (? B (?) Are the format of Y ( ⁇ ), Cb ( ⁇ ), and Cr ( ⁇ ) through the inverse matrix circuit 13 in the selector 14.
  • the mixing circuit 4 selects the signal converted into the signal and sends it to the mixing circuit 4.
  • the mixing circuit 4 combines the MPEG 2 data and the OSD data, generates a new video signal, and outputs the video signal to the color encoder.
  • FIG. 3 is a block diagram showing one embodiment of a 7-correction circuit used in the image synthesizing apparatus according to the present invention.
  • the image synthesizing apparatus according to the present invention handles digital signals. Therefore, the linear correction circuit is also considered to be a circuit that takes advantage of the characteristics of digital signals.CRT nonlinear characteristics have linear characteristic curves, which are approximated by multiple straight lines and The corresponding gain is divided from gain 1 to gain 5, although there is no particular limitation.Gain 1 to gain 5 store the multiplier, and the input data is multiplied by the multiplier of each gain circuit.
  • the correction data of a plurality of types are output through a secretor selectively controlled by a control signal formed by a level detection circuit, and the above-described operation data corrected according to the input signal is output.
  • three sets of circuits are provided corresponding to OSDR-data, 0SDG data, and OSDB data of the three primary colors.
  • gain 2 is selected, for the G signal component, gain 3 is selected, and for the B signal component, the gain is selected. 4 is selected to form R (a), G (a) and B (r) signals, each corrected by 7
  • FIG. 4 is a block diagram showing another embodiment of the key correction circuit used in the image synthesizing apparatus according to the present invention.
  • FIG. 4 in order to simplify the circuit, FIG.
  • the combination of the above-described level detection circuit and gain circuit is used in a time-division manner, so that the circuit scale is significantly reduced.
  • the correction of the above-mentioned color data OSDR data, 0 SDG-data, and OSDB-data is performed by dividing the same circuit in time because the characteristics of the same gain circuit (table) are the same. Or shared with 0 SDR-data.
  • the input section is provided with a parallel-to-serial conversion circuit power ⁇ and the output section is provided with a serial-to-parallel conversion circuit power ⁇ .
  • R data. G-data and B data are converted into serial data R-GB by a switching signal and serially multiplexed as shown in the waveform diagram of FIG. R (r) -data.
  • B (r) The data obtained from the serial image data corrected by the gain and level detection circuits The data is returned to parallel data by the data conversion circuit.
  • the serial-parallel conversion circuit is composed of a shift register that sequentially receives the serial data, and takes out the data of each stage at the timing shown by the arrow to convert the parallel-converted correction data R (7 )-data.G (7) -data.B ( 7) --data can be obtained
  • FIG. 7 is a characteristic diagram for explaining the operation of the 7 correction circuit according to the present invention.
  • the digital color data is 8-bit quantization.
  • the input levels can be divided into 0 to 51, 52 to 102, 103 to 135, 154 to 204, and 205 to 255 in decimal notation.
  • the output gradation level is corrected as shown by the straight line in the figure, that is, the output level is set to 122 for the input level 51 at the branching point of each straight line, and
  • the output level is 1 6 8 for level 102
  • the output level is 202 for input level 1 53
  • the output level is 230 for input level 204
  • the key correction may be conversion using a ROM.
  • the 8-bit input data may be read as an address signal and the 8-bit corrected data may be read.
  • a ROM of storage capacity of 256 x 8: 248 bits.
  • the above-described image synthesizing apparatus can be flexibly adapted to the system in which it is mounted.
  • OSD data can be handled by any of the two types of data formats as described above. Two types of data formats can be selected according to the color encoder that also uses the generated image data,
  • L correction is performed based on the L and CRT nonlinear characteristics.
  • a data conversion circuit for selectively performing data conversion according to a signal form to be synthesized is provided, and an image signal to be displayed on the CRT screen and an image data passed through the data conversion circuit are provided. Is synthesized by the data synthesizing circuit, it is possible to obtain an effect that a synthesized image signal corresponding to two data formats can be obtained.
  • a bit map memory that stores a bit map corresponding to the image to be displayed and a color valet memory that specifies the colors of the pixels that should be displayed are displayed on the CRT.
  • a signal generation circuit for forming color data composed of three primary colors of RGB or color data composed of a luminance signal and two color difference signals, and a signal generation circuit composed of the luminance signal and two color difference signals A matrix circuit that converts the color data into color data of three primary colors consisting of RGB, and the RGB primary colors that are selected from the output or input signal of the matrix circuit and supplied to the key correction circuit.
  • an inverse matrix circuit for converting the corrected three primary colors of RGB output from the color correction circuit into a luminance signal and two color difference signals;
  • a circuit selector or a data selector that selects the output of the circuit or the output of the inverse matrix circuit and transmits it to the data synthesis circuit, thereby providing two types of color filters corresponding to the two data formats. If it can be applied to a single application, it will be effective.
  • a multiplication circuit consisting of a plurality of multipliers having a multiplier approximated to the non-linear characteristic of the CRT in each region by dividing the input level into a plurality of regions, and Relatively simple by comprising a level detection circuit for judging an input level and an output selector for selecting an output signal of a multiplication circuit corresponding to an area corresponding to the input signal based on a detection signal of the level detection circuit. It is possible to obtain an effect that it is possible to perform digital color data correction with a simple configuration.
  • a parallel-serial conversion circuit is provided in the input section of the plurality of multiplication circuits and the level detection circuit, and the RGB primary color power to be corrected is input in a time-division manner.
  • Providing a serial-to-barrel conversion circuit in the output section of this device has the effect of greatly reducing the circuit size of the correction circuit.
  • the present invention relates to an image mounted on an itiUi-wave digital color television receiver, a digital television receiver or a digital VTR (video tape recorder) in addition to the digital satellite broadcast receiver described above. It can be widely used for synthesis equipment ⁇

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Processing Of Color Television Signals (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

Synthétiseur d'images qui possède un circuit de conversion de données et un circuit synthétiseur de données. Le circuit de conversion de données effectue une correction η compatible avec des caractéristiques non linéaires de tube cathodique sur la base de données de sortie numériques de pixels de couleur provenant d'un circuit de source de signaux qui produit les données numériques de pixels de couleur et effectue ensuite une conversion sélective des données sur le signal de sortie à correction η selon la forme des signaux à synthétiser. Le circuit synthétiseur de données synthétise le signal d'image à afficher sur l'écran à tube cathodique et les données d'images produites par le circuit de conversion de données.
PCT/JP1998/002348 1998-05-28 1998-05-28 Synthetiseur d'images WO1999062049A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2000551377A JP3804915B2 (ja) 1998-05-28 1998-05-28 画像合成装置
PCT/JP1998/002348 WO1999062049A1 (fr) 1998-05-28 1998-05-28 Synthetiseur d'images

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1998/002348 WO1999062049A1 (fr) 1998-05-28 1998-05-28 Synthetiseur d'images

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WO1999062049A1 true WO1999062049A1 (fr) 1999-12-02

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WO (1) WO1999062049A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006184916A (ja) * 2006-01-18 2006-07-13 Fujitsu Ten Ltd 表示装置
US8253861B2 (en) 2004-10-20 2012-08-28 Fujitsu Ten Limited Display device, method of adjusting the image quality of the display device, device for adjusting the image quality and device for adjusting the contrast

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09130710A (ja) * 1995-11-06 1997-05-16 Sharp Corp 液晶表示映像信号生成装置
JPH09139865A (ja) * 1995-11-13 1997-05-27 Matsushita Electric Ind Co Ltd ガンマ補正回路
JPH1011025A (ja) * 1996-06-20 1998-01-16 Nec Corp 液晶表示装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09130710A (ja) * 1995-11-06 1997-05-16 Sharp Corp 液晶表示映像信号生成装置
JPH09139865A (ja) * 1995-11-13 1997-05-27 Matsushita Electric Ind Co Ltd ガンマ補正回路
JPH1011025A (ja) * 1996-06-20 1998-01-16 Nec Corp 液晶表示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8253861B2 (en) 2004-10-20 2012-08-28 Fujitsu Ten Limited Display device, method of adjusting the image quality of the display device, device for adjusting the image quality and device for adjusting the contrast
JP2006184916A (ja) * 2006-01-18 2006-07-13 Fujitsu Ten Ltd 表示装置

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Publication number Publication date
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