WO1999040518A1 - Procede et appareil pour synchroniser le rendu et l'affichage graphiques - Google Patents

Procede et appareil pour synchroniser le rendu et l'affichage graphiques Download PDF

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Publication number
WO1999040518A1
WO1999040518A1 PCT/US1999/002149 US9902149W WO9940518A1 WO 1999040518 A1 WO1999040518 A1 WO 1999040518A1 US 9902149 W US9902149 W US 9902149W WO 9940518 A1 WO9940518 A1 WO 9940518A1
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WO
WIPO (PCT)
Prior art keywords
image
buffer
display
control command
memory
Prior art date
Application number
PCT/US1999/002149
Other languages
English (en)
Inventor
Peter L. Doyle
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to AU23524/99A priority Critical patent/AU2352499A/en
Publication of WO1999040518A1 publication Critical patent/WO1999040518A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/399—Control of the bit-mapped memory using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Definitions

  • the present invention relates generally to the field of computer graphics, and more specifically, to a system for efficiently performing a display flip operation between buffered image data.
  • Many present graphics processors employ a technique known as "double buffering" to provide the appearance of smooth animation in three-dimensional graphic sequences.
  • This technique utilizes two image buffers. One image buffer is used to display a first image frame on the display screen while a second buffer is used to generate the next image frame. Once the second image frame is complete, the display output is switched to display the image from the second buffer, thus freeing the first image buffer for the generation of the next image frame.
  • the process of switching between successive images in an image sequence is referred to as a "display flip".
  • a graphics driver for the graphics device provides information for the next frame to be displayed to the graphics device after a display flip occurs.
  • the display flip operation is typically performed by the display device hardware during the video vertical blank period.
  • a currently displayed image buffer does not become available for image generation until the display flip operation has completed.
  • Image generation is presently performed by software processes in which a host processor issues drawing commands to appropriate graphics hardware.
  • Drawing command processing typically occurs asynchronously with video output.
  • the host processor is therefore required to request the graphics hardware to perform a display flip operation during the next vertical blank period and synchronize rendering of the new image with the completion of the display flip operation.
  • Present known systems typically use a direct (unbuffered) graphics hardware command to request the display flip.
  • a software driver is used to poll graphics hardware registers for a notification of the completion of image generation, as well as a notification of the completion of the display flip operation.
  • the request for the generation of the next image is postponed until the software determines that the display flip has occurred.
  • the processor is therefore required to initiate numerous read operations to the graphics device for display flip status.
  • This polling technique thus imposes software overhead that requires both processor and bus time. In certain applications, these polling operations may significantly degrade system performance as they consume processor and bus cycles that could otherwise be applied to image generation and other applications.
  • a method and apparatus for synchronizing the generation and display of graphics images in a graphics processing system.
  • Data comprising a first image is stored in a first buffer of a plurality of memory buffers.
  • a first control command causes the first image to be displayed on a display device, and a second buffer to be made available for storing data comprising a second image.
  • a second control command causes subsequent commands to be suspended if the first control command has not completed execution.
  • Figure 1 is a block diagram of one embodiment of a digital processing system of the present invention.
  • FIG. 2 is a block diagram of one embodiment of a graphics controller included in the digital processing system of Figure 1.
  • Figure 3 is a state diagram for a double buffered system during a display flip operation.
  • Figure 4 is flow chart illustrating the steps of synchronizing graphics generation and display according to one embodiment of the present invention.
  • Figure 5 is a state diagram for a triple buffered system during a display flip operation.
  • Figure 6 is flow chart illustrating the steps of synchronizing graphics rendering and display according to an alternative embodiment of the present invention.
  • control and image generation commands are stored in a memory buffer for later execution by a graphics processor.
  • a first control command requests a display flip operation, and a second command causes the graphics processor to suspend execution of subsequent instructions if a display flip operation has been requested but has not yet completed.
  • FIG. 1 is a block diagram of a digital processing system including a graphics processor according to one embodiment of the present invention.
  • Digital processing system 100 includes a processor 102 coupled through a bus 101 to a random access memory (RAM) 108, a read only memory (ROM) 106, and a mass storage device 104.
  • Mass storage device 104 may be a disk or tape drive for storing data and instructions.
  • input/output controller 105 is also coupled to processor 102 through bus 101 .
  • Input/output controller 105 provides an interface to various input /output devices such as a keyboard, mouse, or similar cursor control devices.
  • Graphics controller 103 provides the physical and logical connections between processor 102 and various display devices, such as display monitor 110. Graphics controller 103 can also be used to control display output through a television 114 through television encoder 112. It should be noted that the architecture of Figure 1 is provided only for purposes of illustration, and a host computer used in conjunction with the present invention is not limited to the specific architecture shown.
  • Graphics controller 103 in digital processing system 100 is controlled by a graphics driver that may be stored in memory, such as RAM 108, ROM 106, or mass storage device 104.
  • the memory devices e.g., RAM 108, are also used to buffer certain commands for later execution by graphics controller 103 or processor 102.
  • graphics controller 103 also includes its own internal local memory 107, which may be implemented as Video RAM (VRAM) devices.
  • VRAM Video RAM
  • FIG. 2 is a block diagram of a graphics controller according to one embodiment of the present invention.
  • Graphics controller 103 includes Video RAM 107.
  • RAM 107 is used to temporarily store data used by graphics controller 103 for the generation of images on a display device.
  • RAM 107 may also be used to cache certain instructions or data structures frequently used by graphics driver 202.
  • RAM 107 contains a plurality of data buffers 206-210. These buffers store pixel information for graphics images to be displayed on the display device. In general, each buffer stores data sufficient for display engine 204 to generate a single image frame on the display device.
  • Graphics controller 103 also includes display engine 204.
  • Display engine 204 outputs the signals comprising the pixel data stored in RAM 107.
  • Display engine 204 receives commands from graphics driver 202.
  • Graphics driver 202 includes software instructions that control various aspects of the display operations of digital processing system 100, such as generating graphics instructions and data, processing starting addresses of graphics data, and processing various display status information.
  • Graphics driver 202 also stores certain drawing and control commands that control the display flip and wait operations that are used to synchronize the generation and display of graphics images.
  • graphics driver 202 is stored in RAM 108 and transmits drawing and control commands to display engine 204 in graphics processor 103 over bus 101.
  • the drawing, flip, and wait control commands are stored in a command buffer 212 contained in RAM 108 for subsequent execution by display engine 204 in graphics controller 103.
  • the buffers 206-210 in RAM 107 are used by the digital processing system to store sequential image frames for processing and display on a display device, such as display monitor 110.
  • the buffers are used in conjunction with control commands that synchronize the rendering of the image data in the graphics processor with the display of image data on the display device.
  • One graphics control command is a "Display Flip” control command that requests the graphics processor to perform a display flip operation.
  • a second graphics control command is a "Wait While Flip Pending" control command that causes the graphics processor to pause if a display flip operation has been requested but has not yet been completed. Double Buffer System
  • the Display Flip and Wait While Flip Pending commands are used in a graphics processing system that employs a double buffering technique.
  • a double buffer system two buffers are used to sequentially render and store image frames. The image data in one buffer is displayed while the next image is generated in the second buffer. Once the next image is completely generated, the display output is flipped to display from the second buffer, thus freeing the previously-displayed image buffer for the generation of a new image.
  • the first buffer is denoted buffer A and the second buffer is denoted buffer B.
  • the buffers are implemented in RAM devices included within graphics controller 103 in Figure 2.
  • buffer A corresponds to buffer 206 and buffer B corresponds to buffer 208.
  • the two buffers could be implemented in other memory devices, such as, for example, RAM 108.
  • Figure 3 is a generalized state diagram illustrating the execution of a display flip operation using double buffers A and B, and the state of the buffers before and after completion of a flip operation sequencing the state.
  • Buffer A, 302 first contains image i and provides the data for image i for display 312.
  • graphics controller 103 reads and executes drawing commands 310 to generate image i+1 stored in buffer B, 304.
  • the Display Flip command 308 is then read and executed.
  • buffer B, 304 provides the data for image i+1 for display 322.
  • graphics controller 103 reads and executes drawing commands 320 to generate image i+2 stored in buffer A, 302.
  • a processor In present double buffered graphics systems, a processor is required to poll the status of the drawing command operations and the display flip operation before causing execution of the next command. Without this polling procedure, synchronization between image generation and display between the two buffers would be lost, resulting in possible image tearing effects. In one embodiment of the present invention, however, synchronization between image generation and display is provided through the storage of display control commands in memory and the use of a Wait While Flip Pending command prior to image generation. This control command mechanism provides adequate synchronization without requiring costly polling operations to be performed by the processor.
  • FIG. 4 is a flow chart which illustrates the steps of performing a display flip operation using stored commands in a double buffer system, according to one embodiment of the present invention.
  • the image data (corresponding to image frame i-1) in buffer A is currently being displayed and that buffer B is available for the generation of the next image.
  • commands to generate image i in buffer B are stored in memory.
  • a first Display Flip command is stored in memory. The first Display Flip command will cause image i in buffer B to be displayed, making buffer A available for new image data (corresponding to the next image, i+1) when the flip operation completes.
  • a Wait While Flip Pending command is stored in memory, step 406. This command causes the generation of image i+1 to be postponed until buffer A is available.
  • step 408 commands to generate image i+1 in buffer A are stored in memory.
  • step 410 a second Display Flip command is stored in memory. This second Display Flip command will cause image i+1 in buffer A to be displayed, making image buffer B available for a new image (corresponding to image i+2) when the flip operation completes.
  • a Wait While Flip Pending command is stored in memory, step 412. This command causes the generation of image i+2 to be postponed until buffer B is available.
  • the steps of the above process are repeated for subsequent frames of the graphics sequence until all of the frames are processed.
  • the image generation, Display Flip, and Wait While Flip Pending commands are stored in command buffer 212 in RAM 108. After being buffered in RAM 108, these commands are executed by display engine 204 in graphics controller 103.
  • the Display Flip and Wait While Flip Pending commands are used in a triple buffer graphics processing system.
  • a triple buffer system three buffers are used to sequentially render and store image frames. The image data in one buffer is displayed while the next image is generated in the second buffer. The third buffer is used to generate a new image during the period between the request for a display flip and the completion of the display flip operation.
  • a triple buffer system improves performance over a double buffer system by reducing the time spent polling for display flip completion notification.
  • present triple buffer systems still require some degree of software polling to be performed by a processor, thus imposing a certain processor bandwidth overhead.
  • the first buffer is denoted buffer A
  • the second buffer is denoted buffer B
  • the third buffer is denoted buffer C.
  • the buffers are implemented in RAM devices included within graphics controller 103 in Figure 2. Again, however, it should be noted that the three buffers could be implemented in other memory devices, such as, for example, RAM 108.
  • Figure 5 is a generalized state diagram illustrating the execution of display flip operations using triple buffers A, B, and C, and the states of the buffers before and after completion of flip operations that sequence the states.
  • Buffer A, 502 first contains image i-2.
  • Buffer B, 504 first contains data for image i-1 and provides the data for image i-1 for display, 512.
  • graphics controller 103 reads and executes drawing commands 510 to generate image i stored in buffer C, 506.
  • the first Display Flip command 508 is then read and executed.
  • buffer C, 506 provides the data for image i for display 522.
  • graphics controller 103 reads and executes drawing commands 520 to generate image i+1 stored in buffer A, 502.
  • buffer B, 504 still contains data for image i-1.
  • a second Display Flip command 518 is then read and executed.
  • buffer A 502
  • graphics controller 103 reads and executes drawing commands 530 to generate images i+2 stored in buffer B, 504.
  • buffer C, 506, still contains data for image i.
  • present triple buffered graphics systems require a processor to poll the status of the drawing command operations and the display flip operations before executing the next command.
  • synchronization between image generation and display is provided through the storage of display control commands in memory and the use ⁇ of a Wait While Flip Pending command prior to image generation. This control command mechanism provides adequate synchronization without requiring polling operations.
  • Figure 6 is a flow chart which illustrates the steps of performing a display flip operation using stored commands in a triple buffer system according to one embodiment of the present invention.
  • the three buffers are assumed to be in the following states: the image data (corresponding to image frame i-2) in buffer A is currently being displayed, the next image (corresponding to frame i-1) has been generated in buffer B, a Display Flip command has been stored to cause buffer B to be displayed, and buffer C is available for the generation of the next image.
  • step 602 commands to generate image i in buffer C are stored in memory.
  • step 604 a Wait While Flip Pending command is stored in memory. This command causes the execution of subsequent commands to be postponed until the preceding display flip operation has completed, thus ensuring that buffer A is no longer being displayed and is available for new image generation.
  • step 606 a first Display Flip command is stored in memory. The first Display Flip command will cause image i in buffer C to be displayed, making buffer B available for new image data when the flip operation completes.
  • step 608 commands to generate image i+1 in buffer A are stored in memory.
  • step 610 a Wait While Flip Pending command is stored in memory. This command causes the execution of subsequent commands to be postponed until the preceding display flip operation has completed, thus ensuring that buffer B is no longer being displayed and is available for new image generation.
  • step 612 a second Display Flip command is stored in memory. This second Display Flip command will cause image i+1 in buffer A to be displayed, making buffer C available for new image data when the flip operation completes.
  • step 614 commands to generate image i+2 in buffer B are stored in memory.
  • step 616 a Wait While Flip Pending command is stored in memory. This command causes the execution of subsequent commands to be postponed until the preceding display flip operation has completed, thus ensuring that buffer C is no longer being displayed and is available for new image generation.
  • step 618 a third Display Flip command is stored in memory. This third Display Flip command will cause image i+2 in buffer B to be displayed, making buffer A available for new image data when the flip operation completes. The steps of the above process are repeated for subsequent frames of the graphics sequence until all of the frames are processed.
  • the image generation, Display Flip, and Wait While Flip Pending commands are stored in command buffer 212 in RAM 108. After being buffered in RAM 108, these commands are executed by display engine 204 in graphics controller 103.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

L'invention concerne un procédé et un appareil permettant de synchroniser la production et l'affichage de données images dans un système processeur graphique (200), ces données images étant mémorisées dans plusieurs tampons mémoires (107). Une première commande est destinée à afficher une image mémorisée dans un premier tampon (206), permettant ainsi à un second tampon (208) d'être disponible pour mémoriser les données de l'image suivante. Une seconde commande de contrôle suspend les commandes suivantes jusqu'à ce que la première commande ait été totalement exécutée, de manière à empêcher tout affichage d'une image incomplète.
PCT/US1999/002149 1998-02-10 1999-02-01 Procede et appareil pour synchroniser le rendu et l'affichage graphiques WO1999040518A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU23524/99A AU2352499A (en) 1998-02-10 1999-02-01 Method and apparatus to synchronize graphics rendering and display

Applications Claiming Priority (2)

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US2162698A 1998-02-10 1998-02-10
US09/021,626 1998-02-10

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WO1999040518A1 true WO1999040518A1 (fr) 1999-08-12

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1143331A2 (fr) * 2000-04-07 2001-10-10 Sony Corporation Appareil de traitement d'image et méthode associée, et appareil d'affichage utilisant l'appareil de traitement d'image
US6970851B1 (en) * 2001-09-28 2005-11-29 Ncr Corporation System and method of configuring value cards
FR2920631A1 (fr) * 2007-08-30 2009-03-06 Alstom Transport Sa Systeme et procede de traitement d'un signal video
EP3525203A1 (fr) * 2017-07-06 2019-08-14 Channel One Holdings Inc. Procédés et systèmes de mise en mémoire tampon d'affichage
US10929946B2 (en) 2018-06-01 2021-02-23 Channel One Holdings Inc. Display buffering methods and systems
US11164496B2 (en) 2019-01-04 2021-11-02 Channel One Holdings Inc. Interrupt-free multiple buffering methods and systems

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5543824A (en) * 1991-06-17 1996-08-06 Sun Microsystems, Inc. Apparatus for selecting frame buffers for display in a double buffered display system
US5657478A (en) * 1995-08-22 1997-08-12 Rendition, Inc. Method and apparatus for batchable frame switch and synchronization operations
US5801717A (en) * 1996-04-25 1998-09-01 Microsoft Corporation Method and system in display device interface for managing surface memory

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5543824A (en) * 1991-06-17 1996-08-06 Sun Microsystems, Inc. Apparatus for selecting frame buffers for display in a double buffered display system
US5657478A (en) * 1995-08-22 1997-08-12 Rendition, Inc. Method and apparatus for batchable frame switch and synchronization operations
US5801717A (en) * 1996-04-25 1998-09-01 Microsoft Corporation Method and system in display device interface for managing surface memory

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1143331A2 (fr) * 2000-04-07 2001-10-10 Sony Corporation Appareil de traitement d'image et méthode associée, et appareil d'affichage utilisant l'appareil de traitement d'image
EP1143331A3 (fr) * 2000-04-07 2006-12-20 Sony Corporation Appareil de traitement d'image et méthode associée, et appareil d'affichage utilisant l'appareil de traitement d'image
US6970851B1 (en) * 2001-09-28 2005-11-29 Ncr Corporation System and method of configuring value cards
FR2920631A1 (fr) * 2007-08-30 2009-03-06 Alstom Transport Sa Systeme et procede de traitement d'un signal video
EP3525203A1 (fr) * 2017-07-06 2019-08-14 Channel One Holdings Inc. Procédés et systèmes de mise en mémoire tampon d'affichage
US11049211B2 (en) 2017-07-06 2021-06-29 Channel One Holdings Inc. Methods and system for asynchronously buffering rendering by a graphics processing unit
US10929946B2 (en) 2018-06-01 2021-02-23 Channel One Holdings Inc. Display buffering methods and systems
US11164496B2 (en) 2019-01-04 2021-11-02 Channel One Holdings Inc. Interrupt-free multiple buffering methods and systems

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Publication number Publication date
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