AU2352499A - Method and apparatus to synchronize graphics rendering and display - Google Patents

Method and apparatus to synchronize graphics rendering and display

Info

Publication number
AU2352499A
AU2352499A AU23524/99A AU2352499A AU2352499A AU 2352499 A AU2352499 A AU 2352499A AU 23524/99 A AU23524/99 A AU 23524/99A AU 2352499 A AU2352499 A AU 2352499A AU 2352499 A AU2352499 A AU 2352499A
Authority
AU
Australia
Prior art keywords
display
graphics rendering
synchronize
synchronize graphics
rendering
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU23524/99A
Inventor
Peter L. Doyle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU2352499A publication Critical patent/AU2352499A/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/399—Control of the bit-mapped memory using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
AU23524/99A 1998-02-10 1999-02-01 Method and apparatus to synchronize graphics rendering and display Abandoned AU2352499A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US2162698A 1998-02-10 1998-02-10
US09021626 1998-02-10
PCT/US1999/002149 WO1999040518A1 (en) 1998-02-10 1999-02-01 Method and apparatus to synchronize graphics rendering and display

Publications (1)

Publication Number Publication Date
AU2352499A true AU2352499A (en) 1999-08-23

Family

ID=21805265

Family Applications (1)

Application Number Title Priority Date Filing Date
AU23524/99A Abandoned AU2352499A (en) 1998-02-10 1999-02-01 Method and apparatus to synchronize graphics rendering and display

Country Status (2)

Country Link
AU (1) AU2352499A (en)
WO (1) WO1999040518A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6747656B2 (en) * 2000-04-07 2004-06-08 Sony Corporation Image processing apparatus and method of the same, and display apparatus using the image processing apparatus
US6970851B1 (en) * 2001-09-28 2005-11-29 Ncr Corporation System and method of configuring value cards
FR2920631B1 (en) * 2007-08-30 2010-01-22 Alstom Transport Sa SYSTEM AND METHOD FOR PROCESSING A VIDEO SIGNAL
US11049211B2 (en) 2017-07-06 2021-06-29 Channel One Holdings Inc. Methods and system for asynchronously buffering rendering by a graphics processing unit
CA3044477A1 (en) 2018-06-01 2019-12-01 Gregory Szober Display buffering methods and systems
US11164496B2 (en) 2019-01-04 2021-11-02 Channel One Holdings Inc. Interrupt-free multiple buffering methods and systems

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3316592B2 (en) * 1991-06-17 2002-08-19 サン・マイクロシステムズ・インコーポレーテッド Dual buffer output display system and method for switching between a first frame buffer and a second frame buffer
US5657478A (en) * 1995-08-22 1997-08-12 Rendition, Inc. Method and apparatus for batchable frame switch and synchronization operations
US5801717A (en) * 1996-04-25 1998-09-01 Microsoft Corporation Method and system in display device interface for managing surface memory

Also Published As

Publication number Publication date
WO1999040518A1 (en) 1999-08-12

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase