WO1999031607A1 - Procede de mise au point d'un dispositif a circuit integre a semi-conducteur - Google Patents

Procede de mise au point d'un dispositif a circuit integre a semi-conducteur Download PDF

Info

Publication number
WO1999031607A1
WO1999031607A1 PCT/JP1997/004619 JP9704619W WO9931607A1 WO 1999031607 A1 WO1999031607 A1 WO 1999031607A1 JP 9704619 W JP9704619 W JP 9704619W WO 9931607 A1 WO9931607 A1 WO 9931607A1
Authority
WO
WIPO (PCT)
Prior art keywords
test
semiconductor integrated
integrated circuit
design
circuit device
Prior art date
Application number
PCT/JP1997/004619
Other languages
English (en)
Japanese (ja)
Inventor
Isao Shimizu
Masayuki Satou
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1997/004619 priority Critical patent/WO1999031607A1/fr
Priority to JP2000539433A priority patent/JP3971104B2/ja
Publication of WO1999031607A1 publication Critical patent/WO1999031607A1/fr

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
    • G01R31/318357—Simulation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318307—Generation of test inputs, e.g. test vectors, patterns or sequences computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Definitions

  • the present invention relates to a semiconductor integrated circuit device design and test design technique, and more particularly to a technique that enables a test design to be started from an upstream side of a semiconductor integrated circuit device design process.
  • the target specification (the target specification may mean the final specification of the product depending on the product manufactured using the present invention) is determined, and the logic design and the circuit design are performed. And layout design etc. At this time, if there are past design assets, they are used. In the design process, a logic simulation or a circuit simulation is performed to verify whether or not the design target specification is satisfied.
  • a prototype of the semiconductor integrated circuit device is next produced, and the function of the prototyped semiconductor integrated circuit device is actually verified using a tester. According to the terminal arrangement and the number of terminals of the semiconductor integrated circuit device, the device and the test device are connected via a test board. If the design target specification has not been achieved in the device test, modify the circuit design of the semiconductor integrated circuit device to achieve the target specification. After that, mass production of the semiconductor integrated circuit device starts.
  • test design it is necessary to design the test board and design a test program for operating the test.
  • test process for test design starts after a device designer creates a test specification.
  • a test process has not been performed in parallel with a semiconductor integrated circuit device design process.
  • test specifications were created after the circuit design of the device was completed, and test board / test program design was started based on the test specifications.
  • the mainstream of the series design work is to start the test design after completing the circuit design, so in the test design process, the designer decided on the test that was decided for mass production testing.
  • a test engineer prepares a test board for the specifications by creating a test program and debugging the software. It was common practice to debug a program on a test screen. In other words, along with the evaluation of the prototype device, the evaluation of the test program and the test board were also performed using the test equipment.
  • the defect was either the prototype device, test program, or test board.
  • the present inventor has clarified that there is a case where it is difficult to identify whether the problem is caused by the problem or not, and that the development period of the semiconductor integrated circuit device including the test design cannot be shortened.
  • the present inventor has proposed a semiconductor integration by parallelizing test design and device design. I found a new idea to shorten the development period of integrated circuit devices overall and improve development efficiency.
  • An object of the present invention is to provide a method for developing a semiconductor integrated circuit device capable of shortening the entire development period of a semiconductor integrated circuit device and improving development efficiency by parallelizing a test design and a device design. To do so.
  • Another object of the present invention is to provide a semiconductor integrated circuit device development system capable of shortening the development period of a semiconductor integrated circuit device as a whole from the viewpoint of a test design process.
  • a method for developing a semiconductor integrated circuit device is based on a first process for generating a device model in which functions of a semiconductor integrated circuit device are modeled in a function description language so as to satisfy a target specification, and based on the device model.
  • a second process for designing a circuit of a semiconductor integrated circuit device and in parallel with the second process, a device model is simulated together with a test model in which test items corresponding to the target specifications are modeled.
  • a third process of performing the design The device model whose function is described satisfies the target specification of the semiconductor integrated circuit device to be developed.This device model is simulated together with the test model, and based on the simulation result, it is determined whether the device model satisfies the target specification.
  • the validity of the test model for example, the validity of the test program or the test board design for connecting the test device and the semiconductor device can be verified. Before completing, proceed with the test design. It becomes possible.
  • the first processing includes: a first step of defining an input / output state of each external terminal corresponding to each external terminal of the semiconductor integrated circuit device so as to satisfy a target specification of the semiconductor integrated circuit device; A second step of dividing the device into a plurality of functional modules, defining the internal terminals of each functional module, and defining the input / output state of each internal terminal so that each functional module satisfies the target specification;
  • the input / output state of the external terminal defined in the first step is given, the coupling state of the internal terminal between the respective functional modules is defined so as to satisfy the target specification of the semiconductor integrated circuit device, and the device Generating a model.
  • the size of the division of the functional module is related to the simulation time when verifying whether the divided functional module satisfies the target specification. The larger the larger, the shorter the time required for verification, and the smaller the smaller, the more detailed the function. Can be defined. Which one to use can be determined according to whether the semiconductor integrated circuit device is a digital circuit, an analog circuit, a digital / analog mixed circuit, or depending on the degree of attention. .
  • the first processing in a more detailed aspect is performed by an eye of the semiconductor integrated circuit device.
  • the functional module A third step of verifying whether the target specification is satisfied, and a step of repeating the adjustment of the target specification and the third step for the functional module that does not satisfy the target specification in the third step until the target specification is satisfied.
  • the definition of the function module, the definition of the input / output state of the external terminal and the internal terminal, and the coupling between the internal terminals The device model can be generated based on the definition.
  • the device model includes a chip function description data relating to a function to be realized in a chip of a semiconductor integrated circuit device and an electric characteristic of a package which accommodates the chip and forms an electrical connection with the chip. It can be formed by both package function description data and the former. For example, when the inductance component, the capacitance component, and the like parasitic on the bonding wires of the package are considered in advance, the device model is described by both the chip function description data and the package function description data. To form
  • the test setup model includes test setup function description data specifying a test setup hardware by a function description, a test program for determining the operation of the tester for each test item, a test setup and a semiconductor integrated circuit. It can be formed based on the test board design data that specifies the test board circuit configuration for realizing the connection with the device. At this time, as described above, in the test design, the test program and the test board are designed by reflecting the simulation result in the test model.
  • the method for developing a semiconductor integrated circuit device further includes a fourth process for generating a date and time for specifying a layout of the semiconductor integrated circuit device based on the circuit description data, and a process for generating the date and time based on the date and time.
  • a fifth process of mounting the manufactured semiconductor integrated circuit device on the test board through the test board, operating the test board using the test program, and performing an actual test. Can be included.
  • a development system for a semiconductor integrated circuit device generates a device model in which functions of the semiconductor integrated circuit device are modeled by a function description language so as to satisfy a target specification, and furthermore, the semiconductor integrated circuit device is developed based on the device model.
  • Device design means for designing the circuit; and test design means for performing a test design for testing the semiconductor integrated circuit device.
  • the test design means functions as a first data processing means for inputting the device model and supporting circuit design of a test board for connecting a tester to a semiconductor integrated circuit device, and a hardware unique to a test board.
  • Second data processing means for supporting the design of a test program for verifying necessary test items based on the test function description data specified by the description and the device model, and the test function description Based on the data, the test program, and the design data of the test board, a test item model that models test items corresponding to the target specification is configured, and the test item model and the device model are integrated to perform simulation. And a third data processing means for performing the above-mentioned, and before completing the circuit design by the test design means, verifying whether or not the device model satisfies a target specification based on the simulation result. This enables verification of test board design data and test programs.
  • FIG. 1 is an explanation schematically showing a method of developing a semiconductor integrated circuit device according to the present invention.
  • FIG. 2 is a flowchart showing an example of a method for developing a semiconductor integrated circuit device.
  • FIG. 3 is a flowchart showing a comparative example in which design of a test board and a test program is started after circuit design of a semiconductor integrated circuit device is completed.
  • FIG. 4 is an explanatory diagram showing an example of a divided functional module and an example of a hardware description of the functional module in HDL.
  • FIG. 5 is a conceptual diagram showing a state in which a semiconductor integrated circuit device is mounted on a test board.
  • FIG. 6 is an explanatory diagram showing a virtual test setup which is an example of the test design means.
  • Fig. 7 is an explanatory diagram of an example of data flow in system design and function design.
  • FIG. 8 is an explanatory diagram of an example of a data flow in circuit design.
  • FIG. 9 is an explanatory diagram of an example of a data flow when designing a test program and a test board while performing a virtual test using the virtual test server.
  • FIG. 10 is an explanatory diagram of an example of a data flow accompanying the design of the user board.
  • Fig. 11 is an explanatory diagram of an example of a test board design method using a virtual test board.
  • FIG. 12 is an explanatory diagram of an example of a user board design method using a device model.
  • FIG. 13 is an explanatory diagram of an example of a method of verifying a semiconductor integrated circuit device in which a part of the semiconductor integrated circuit device on a user board is subjected to circuit simulation.
  • a computer system such as a workstation is used.
  • a device design means 1 and a test design means 2 are constituted by the operation program.
  • the device design means 1 and the test design means 2 are configured by separate combination systems.
  • the device design means 1 performs system design, function design, circuit design, and rate design of a semiconductor integrated circuit device based on target specifications.
  • system design a semiconductor integrated circuit device is divided into functional modules of an appropriate size.
  • function design the functions of a semiconductor integrated circuit device are described as a set of function modules in a function description language (for example, HDL Description Language): Generates a device model modeled in the hardware description language).
  • a prototype of the wafer is produced by the wafer process, and a probe test (P test) is performed on the prototype, followed by an assembly process to assemble (package) the prototype device.
  • This prototype device is subjected to product debugging (final inspection), the results of the debugging are fed back to the device design, and finally, mass production of semiconductor integrated circuit devices is started.
  • the mass-produced semiconductor integrated circuit devices are tested at mass production test 3 and shipped.
  • the test design means 2 performs test design for testing a semiconductor integrated circuit device.
  • a test board that supports the design of a test program for debugging for P inspection and final inspection, a test program for mass production testing for mass production testing, and a connection between the testing and semiconductor integrated circuit devices. Used for design.
  • the result of the functional design of the semiconductor integrated circuit device is given to the test design means 2. That is, function description data of a semiconductor integrated circuit device represented by the device model is given. Based on this, the test design means 2 generates a test model that models test items corresponding to the target specification, and simulates a device model together with the test model to perform test design. Do. The device model in which the function is described satisfies the target specification of the semiconductor integrated circuit device to be developed.This device model is simulated together with the test model, and based on the simulation results, it is determined whether the device model satisfies the target specification.
  • test model By determining the validity of the test model, the validity of the test model, for example, whether the design of the test program or the test board is valid, can be verified, and the test design can proceed from the functional design stage. As shown in Fig. 1, test design can be completed by the P test stage. Therefore, The development period of the semiconductor integrated circuit device can be shortened as a whole, and the development efficiency can be improved.
  • the function description data of the semiconductor integrated circuit device represented by the device model as a result of the function design can be provided to the user of the semiconductor integrated circuit device.
  • the device model is a model of the functions of a semiconductor integrated circuit device as a set of the above-mentioned functional modules in a function description language, and satisfies the target specifications.
  • the user can use the device model to design a system board or a circuit board (referred to as a user board) using the semiconductor integrated circuit device before the device is completed.
  • a device model that satisfies the target specification is simulated together with a model of the required user board, and it is verified whether the device model satisfies the target specification. I do.
  • the user board design can be advanced from an early stage while evaluating the user board. . Further, as described later with reference to FIG. 13, the user can request a design change for the semiconductor device at an early stage so as to optimize the user board.
  • FIG. 2 is a flowchart illustrating an example of a method for developing a semiconductor integrated circuit device.
  • steps S1 to S5 are a first process for generating a device model in which the functions of the semiconductor integrated circuit device are modeled in a function description language so as to satisfy a target specification.
  • steps S6 to S8 are a second process for performing circuit design of the semiconductor integrated circuit device based on the device model.
  • steps S20 to S23 a test design is performed by simulating a device model together with a test model that models test items corresponding to the target specifications in parallel with the second processing. This is the third process.
  • Steps S30 to S37 are a board design process by the user.
  • Steps S1 and S2 are not particularly limited, but fall under the category of system design.
  • the target specification of the semiconductor integrated circuit device (hereinafter, also simply referred to as IC) is determined.
  • the input / output state of each external terminal is defined corresponding to each external terminal of the semiconductor integrated circuit device so as to satisfy the target specification of the semiconductor integrated circuit device.
  • the semiconductor integrated circuit device is divided into a plurality of functional modules. The size of the functional module division is related to the simulation time when verifying whether the divided functional modules satisfy the target specifications.The larger the size, the shorter the verification time, and the smaller the size, the more detailed the function. Can be defined. Which one to use can be determined depending on whether the semiconductor integrated circuit device is a digital circuit, an analog circuit, a digital / analog mixed circuit, or the like, or depending on the degree of attention.
  • steps S3 and S4 the internal terminals of each functional module are defined, and the input / output state of each internal terminal is defined so that each functional module satisfies the target specification.
  • the device model is generated by defining the coupling state of the internal terminals between the functional modules so as to satisfy the target specification of the semiconductor integrated circuit device when the input / output state of the external terminal is given.
  • step S2 input / output of each external terminal is made corresponding to each external terminal of the semiconductor integrated circuit device so as to satisfy the target specification of the semiconductor integrated circuit device.
  • the state is defined, and the semiconductor integrated circuit device is defined by dividing it into a plurality of functional modules.
  • the input / output status of the internal terminals of each function module Is defined, and a functional simulation of the functional module is performed using the defined input / output state to verify whether the functional module satisfies the target specification (S4).
  • S3 target specification of the functional module until each functional module satisfies the target specification
  • S4 perform simulation
  • the connection of the internal terminals between the function modules is defined, the input / output state of the external terminals defined in step S2 is given, and the simulation is performed. Verify whether the target specifications of the integrated circuit device are satisfied (S4). If the target specification of the semiconductor integrated circuit device is not satisfied, the simulation is repeated by adjusting the target specification of the desired functional module until the target specification of the semiconductor integrated circuit device is satisfied (S4).
  • a device model is generated based on the definition of the function module, the definition of the input / output state of the external and internal terminals, and the definition of the connection between the internal terminals.
  • the device model includes a chip function description data relating to a function to be realized in a chip of a semiconductor integrated circuit device and an electric characteristic of a package which accommodates the chip and forms an electrical connection with the chip. It can be formed by both the package function description data and the former. For example, when the inductance component, the capacitance component, and the like that are parasitic on the bonding wires of the package are considered in advance, the device model is determined by both the chip function description data and the package function description data. Form.
  • Such a definition of the device model satisfies the target specification of the semiconductor integrated circuit device in terms of the input / output state of the external terminal and the internal terminal. Specifications or test items will be given.
  • Such a device model is given to the test design means 2, and design of a test board test program is started based on the description of the device model (S21). Note that the number of terminals and the terminal functions are specified from the target specifications of the semiconductor integrated circuit device, and these often do not depend on the simulation result of step S4.
  • These basic target specifications are given to the test design means 2 in advance, and the test board element constants, that is, the number of used terminals and their terminal functions are extracted from the given target specifications (S20). The obtained data is given to the process of step S21 as a basic test board design data.
  • test design can proceed in parallel with circuit design in step S5 and subsequent steps.
  • the above device model is simulated together with the test model, and whether or not the device model satisfies the target specification is determined from the simulation results.
  • Validity for example, the validity of the test program or test board design can be verified from the functional design stage.
  • the test setup model includes a test setup function description data that specifies a test setup hardware by a function description, a test program for determining a test setup operation for each test item, and a circuit configuration of a test board. It can be formed based on the specified test board design data.
  • the test design means 2 proceeds with the design of the test program and the test board by reflecting the simulation results in the test model.
  • circuit design the design target specifications are satisfied at the circuit level by repeating circuit design 'modification (S6) and circuit simulation (S7).
  • circuit design is completed (S8), the result is reflected in the test design (S22). For example, if the driving capability of the external output buffer circuit of a semiconductor integrated circuit device is changed to be smaller than the original, it is necessary to change the driving capability of the relay amplifier for driving relatively long wiring on the test board. Because it becomes. In some cases, it is necessary to eliminate dynamic characteristic changes such as voltage reflection.
  • the test board is prototyped (S23).
  • the layout design of the semiconductor integrated circuit device is performed, and the semiconductor integrated circuit device is prototyped (S9).
  • the prototyped semiconductor integrated circuit device is connected to the test board via the test board thus prepared, and the test board is operated using the test program generated in the test design.
  • the verification is performed by operating the semiconductor integrated circuit device (S10).
  • the test board and the test program are in a state of high perfection because the virtual test is performed in step S21 and the correction is performed in step S22. Therefore, in the device test stage of step S10, if there is any inconvenience in the test results, the cause of the failure of the device can be pointed out first, thereby improving the test reliability.
  • it is most effective to verify the dynamic characteristics such as voltage reflection in step S10, which is the final verification for the test design.
  • the device model is also provided to a user.
  • the user can design the board of the user's actual system based on the description of the device model (S31).
  • the number of terminals and their functions are specified from the target specifications of the semiconductor integrated circuit device, and they often do not depend on the simulation result of step S4. Therefore, in this description, these basic target specifications are used. Is also given to the user, and from the given target specification, semiconductor integration
  • the number of terminals used for mounting the circuit device on the user board and their terminal functions are extracted (S30), and the extracted data is given to the process of step S31 as a basic design of the user board.
  • the user can proceed with the user board design in parallel with the circuit design by the semiconductor manufacturer.
  • the device model is simulated together with the model of the user board, and whether or not the device model satisfies the target specification is determined based on the simulation result.
  • the validity of the model can be verified from the functional design stage. Therefore, the user can proceed with the design of the user board by reflecting the verification result from the function design stage of the semiconductor integrated circuit device based on the user's skill.
  • the result is provided to the user.
  • the user can reflect the result of the circuit design on the design of the user board (S32). For example, when the driving capability of the external output buffer circuit of the semiconductor integrated circuit device is changed to be smaller than the initial one, it is also possible to make a correction to insert a relay amplifier or the like in the middle of the signal wiring on the user board. In some cases, it is necessary to eliminate dynamic characteristic changes such as voltage reflection.
  • the user can start designing the user board before providing the prototype of the semiconductor integrated circuit device. After the design of the user board is completed, a prototype of the user board is manufactured. As is clear from Fig. 2, the prototype of the user board can be completed almost at the same time as the acquisition of the prototype of the semiconductor integrated circuit device. Therefore, the user can obtain a prototype of the semiconductor integrated circuit device immediately after producing the prototype of the user board, incorporate the prototype into the user board, and determine whether the semiconductor integrated circuit device achieves the target specification of the user system. It can be verified (S35). By referring to the verification result, if necessary, tuning such as adjustment of circuit elements on the user board can be performed (S36).
  • the user board is in a highly completed state because the virtual test in step S31 and the correction in step S32 are performed. Therefore, the verification in step S35 can be performed efficiently, and the period until mass production (S37) of the user board can be shortened.
  • test design in the method of starting test design such as a test board and a test program after circuit design of a semiconductor integrated circuit device is completed, test design must be performed from the upstream side of the circuit design. Cannot be done. Therefore, when verifying the achievement of the target specifications using a prototyped semiconductor integrated circuit device, there is not enough time to complete the design of the test board test program. Test program and test board cannot be verified.
  • FIG. 4 shows an example of the functional module divided in step S2 and an example of a hardware functional description of the functional module by HDL.
  • FIG. 5 shows a conceptual diagram of a state in which a semiconductor integrated circuit device is mounted on a test board.
  • 5 is a test board and 6 is a semiconductor package. It is an integrated circuit device. Terminals for connection to the test board are arranged on the periphery of the test board 5, and the terminals of the semiconductor integrated circuit device 6 are connected to corresponding terminals of the test board via wiring and circuit elements according to their input / output functions. Is done.
  • the circuit elements are a relay amplifier for driving the wiring load of the test board, a capacitance element for preventing oscillation, and a resistance element for preventing voltage reflection.
  • FIG. 6 shows a virtual test evening (hereinafter referred to as virtual test evening 2) which is an example of the test designing means 2.
  • the virtual test system 2 is configured on a convenience store system such as a workstation, and includes a simulator 14, a design environment tool 13, a virtual test environment tool 11, a test board design environment module 10, and Has test pattern processing and conversion tool 15 According to this example, each tool constitutes a data processing means by hardware of the contribution system and an application program.
  • For virtual test 2 input the test specifications selected in the system design and the function description data of the device obtained by the device design means 1.
  • the test board design environment tool 10 supports a circuit design of a test board for connecting a test board and a semiconductor integrated circuit device based on the device model and the like.
  • the virtual test environment tool 11 includes a plurality of modules 12 that generate test function specific hardware function description codes such as device power supply, DC measurement system, pin electronics, arbitrary waveform generation, and frequency measurement. Inserted.
  • the virtual test environment tool 11 supports the design of a test program based on the information generated by the module 12, the device model, the test specifications, and the like. That is, it supports the design of a test program for verifying necessary test items based on test function description data that specifies the hardware specific to the test based on the function description and the device model.
  • the design environment tool 13 is a tool for realizing a software test, and includes a device specified by a device model and a circuit of a test board obtained by the test board design environment tool 10.
  • the test board specified from the design day and the tester are integrated in the function description, in other words, integrated in software, to construct a test environment. That is, based on the test setup function description data, the test program and the design data of the test board, a test setup model that models test items corresponding to the target specifications is constructed, and the tester model is configured. And the device model.
  • Simulate overnight 14 Simulate test items in the built test environment.
  • the test pattern processing / conversion tool 15 is a tool that converts or corrects event pattern test pattern data on a simulation into patterns on the time axis that can be used in testing.
  • a test program, a circuit design data of a test board, and a test pattern are generated by the virtual test 2.
  • the virtual tester 2 completes the test board design, test program, and test program to some extent in parallel with the circuit design, in other words, before the device prototype is completed. Can be.
  • Fig. 7 shows an example of the data flow in system design and functional design.
  • reference numeral 20 denotes a tool for functional design and circuit design operated on a computer system such as a workstation, and a semiconductor integrated circuit is drawn by drawing a diagram combining symbols on a screen.
  • a large number of symbols are stored in the symbol library 21, and graphics predefined using the symbols are stored in the graphic library 22.
  • Netlist 23 stores connection information for each figure.
  • the function design and circuit design tools 20 are provided with package element constants such as the number of external terminals of the semiconductor integrated circuit device package, target specifications of the semiconductor integrated circuit device, and the like.
  • a functional model (device model) 24 of the entire semiconductor integrated circuit device can be generated as a set of functional modules.
  • FIG. 8 shows an example of a data flow in circuit design.
  • the functional design and circuit design tool 20 receives the device model 24 and the target specification, performs circuit design and simulation based on this, and repeats the operation until the target specification is satisfied. As a result, circuit design data 25 is obtained.
  • FIG. 9 shows an example of a data flow when a test program and a test board are designed while performing a virtual test using the virtual test server 2.
  • the virtual test environment 2 test board design environment tool and virtual test environment tool, etc. enable test design by drawing a figure that combines symbols on the screen. A large number of symbols are stored in the symbol library 21, and graphics predefined using the symbols are stored in the graphics library 22.
  • Netlist 23 stores connection information for each figure. For virtual test 2, test board element constants, device model 24, target specifications, etc. are input, and basic design data for the test board is generated based on these.
  • test program and test board design data 28 in which bugs are corrected are obtained.
  • FIG. 10 shows an example of a data flow accompanying the design of the user board.
  • Reference numeral 30 denotes a design tool used for designing a user board.
  • the design tool 30 enables functional design and circuit design by drawing a figure combining symbols on the screen. A large number of symbols are stored in the symbol library 31, and graphics predefined using the symbols are stored in the graphics library 32. Net list 33 stores connection information of each figure.
  • the design tool 30 inputs the device constants of the user board, the device model, the target specifications of the user board, etc., constructs a test environment integrating the user board model and the device model, and executes simulation of the device and the test board by simulation. Is evaluated.
  • Figure 11 shows an example of a test board design method using virtual test equipment 2.
  • the semiconductor integrated circuit device As a DUT (Device Under Test), but also the circuit of the input / output interface circuit of the test board between the test device and the semiconductor integrated circuit device Device constants (inductance, capacitance, etc.) must be taken into account.
  • the above-mentioned element constant is assumed. Making such an assumption, the input board of the test board coupled to the input of the semiconductor integrated circuit device as the DUT and the test board coupled to the output of the semiconductor integrated circuit device as the DUT A circuit simulation is performed for the output interface circuit, and a functional simulation is performed for the semiconductor integrated circuit device as the DUT.
  • FIG. 12 shows an example of a user board design method using a device model.
  • the circuit element constants inductance, capacitance, etc.
  • the above circuit element constants are assumed. With such assumptions, circuit simulation is performed on the input peripheral circuit coupled to the input of the semiconductor integrated circuit device and the output peripheral circuit coupled to the output of the semiconductor integrated circuit device. A function simulation will be performed for this.
  • the device constant is corrected, and the design of the input peripheral circuit and the output peripheral circuit on the user board is changed.
  • Fig. 13 shows an example of a method of verifying a semiconductor integrated circuit device in which a part of the semiconductor integrated circuit device on a user board is subjected to circuit simulation. Contrary to FIG. 12, the input circuit and the output circuit of the semiconductor integrated circuit device are subjected to circuit simulation, and the other parts of the semiconductor integrated circuit device are subjected to functional simulation. If the simulation waveforms of the input circuit and output circuit of the semiconductor integrated circuit device deviate significantly from the ideal waveform, it is necessary to change the element constants of the transistors constituting the input circuit inside the semiconductor integrated circuit device become. Such a simulation is performed at the circuit design stage using device capabilities. Because it can be clarified, it is easy to change the design inside the semiconductor integrated circuit device in order to obtain good compatibility with the user system.
  • the tools that make up the virtual test are not limited to the above description, and can be changed as appropriate.
  • the circuit scale of the semiconductor integrated circuit device is small, or when the circuit configuration is simple, it is possible to generate a device model without dividing into a plurality of functional modules.
  • the method for developing a semiconductor integrated circuit device of the present invention can be applied not only to the development of a new device, but also to the improvement or extension of functions of an existing device. In this case, it goes without saying that the method of the present invention can be applied by diverting design resources accumulated in the past. Industrial applicability
  • the present invention is also applicable to logic LSIs, analog LSIs, analogs such as memories and microcomputers, etc. '' Widely applicable to the development of various types of semiconductor integrated circuit devices that are not limited to functions such as digital mixed LSI, shorten the overall development period of semiconductor integrated circuit devices, improve development efficiency, and are effective can do.

Abstract

L'invention concerne un procédé de mise au point d'un dispositif à circuit intégré à semi-conducteur comprenant une première série d'étapes de fabrication (S1 à S5) permettant de produire un modèle de dispositif dans lequel les fonctions d'un circuit intégré à semi-conducteur devant être mis au point sont modélisés au moyen d'un langage de description de fonction, de manière à correspondre aux spécifications cible, une deuxième série d'étapes de fabrication (S6 à S8) permettant de concevoir le circuit du dispositif à partir du modèle de dispositif, et une troisième série d'étapes de fabrication (S21 à S22) permettant de produire un modèle d'essai dans lequel les éléments d'essai correspondant aux spécifications cibles sont modélisés en parallèle avec la seconde série d'étapes de fabrication, et qui permet de réaliser un essai de conception par simulation du modèle d'essai et du modèle de dispositif. Etant donné que le modèle de dispositif dans lequel les fonctions du dispositif à circuit sont décrites correspond aux spécifications du dispositif à circuit, on peut vérifier le caractère adéquat du modèle d'essai, par exemple le caractère adéquat d'un programme d'essai ou la conception d'une carte d'essai permettant de connecter un dispositif d'essai à un dispositif à semi-conducteur, par une simulation du modèle du dispositif et du modèle d'essai, et déterminer alors si le modèle de dispositif respecte ou non les spécifications cible. On peut ainsi réaliser la conception d'essai avant d'achever la conception du circuit du dispositif.
PCT/JP1997/004619 1997-12-16 1997-12-16 Procede de mise au point d'un dispositif a circuit integre a semi-conducteur WO1999031607A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/JP1997/004619 WO1999031607A1 (fr) 1997-12-16 1997-12-16 Procede de mise au point d'un dispositif a circuit integre a semi-conducteur
JP2000539433A JP3971104B2 (ja) 1997-12-16 1997-12-16 半導体集積回路デバイスの開発方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1997/004619 WO1999031607A1 (fr) 1997-12-16 1997-12-16 Procede de mise au point d'un dispositif a circuit integre a semi-conducteur

Publications (1)

Publication Number Publication Date
WO1999031607A1 true WO1999031607A1 (fr) 1999-06-24

Family

ID=14181665

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1997/004619 WO1999031607A1 (fr) 1997-12-16 1997-12-16 Procede de mise au point d'un dispositif a circuit integre a semi-conducteur

Country Status (2)

Country Link
JP (1) JP3971104B2 (fr)
WO (1) WO1999031607A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008070294A (ja) * 2006-09-15 2008-03-27 Yokogawa Electric Corp Ｉｃテスタ用デバッグ支援方法
JP2009545791A (ja) * 2006-08-02 2009-12-24 エアバス フランス 電子アセンブリの実現可能性の決定を補助するプロセス及び装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PFU TECHNICAL REVIEW, Vol. 7, No. 1, (May 1996), HIROTAKE NIIDE et al., "Application of Concurrent Engineering to Development of Computer System (in Japanese)", pages 31-40. *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009545791A (ja) * 2006-08-02 2009-12-24 エアバス フランス 電子アセンブリの実現可能性の決定を補助するプロセス及び装置
JP2008070294A (ja) * 2006-09-15 2008-03-27 Yokogawa Electric Corp Ｉｃテスタ用デバッグ支援方法

Also Published As

Publication number Publication date
JP3971104B2 (ja) 2007-09-05

Similar Documents

Publication Publication Date Title
US6678645B1 (en) Method and apparatus for SoC design validation
US6083269A (en) Digital integrated circuit design system and methodology with hardware
JP2815281B2 (ja) デジタル回路設計支援システムおよびその方法
JP4058252B2 (ja) Ｉｃ設計の検証方法
EP0485199A2 (fr) Création d'un dispositif programmé par le fabriquant utilisant une description logique et dispositif échantillon réalisant la description
US6363509B1 (en) Method and apparatus for transforming system simulation tests to test patterns for IC testers
US6197605B1 (en) Method and device for test vector analysis
US20060294008A1 (en) Method And System For Designing A Probe Card
US6487704B1 (en) System and method for identifying finite state machines and verifying circuit designs
JP2005292144A (ja) 集積回路デバイスを試験するための集積回路デバイス試験を検証する方法及び装置
US20020173942A1 (en) Method and apparatus for design validation of complex IC without using logic simulation
US6629294B2 (en) Tool and method for improving the quality of board design and modeling
US20020163351A1 (en) Method for producing test patterns for testing an integrated circuit
US6185726B1 (en) System and method for efficiently designing integrated circuit devices
US7539900B1 (en) Embedded microprocessor for integrated circuit testing and debugging
JP3971104B2 (ja) 半導体集積回路デバイスの開発方法
Thiel Have I really met timing?-validating primetime timing reports with SPICE
WO1999031608A1 (fr) Procede de mise au point d'une carte systeme
US20040230414A1 (en) Method for verification of hardware designs with multiple asynchronous frequency domains
JPH09171056A (ja) テスト設計方法とその装置、並びにテスト方法とその装置
JP3162316B2 (ja) 電子回路テスト用システム
US20030126570A1 (en) Systems and methods for realizing integrated circuits
Hainz et al. Reduction of System Development Time with Early Sensor Prototyping and Measurement-Based Simulations
August A robust and efficient pre-silicon validation environment for mixed-signal circuits on intel's test chips
Jervan et al. Decider: A decision diagram based hierarchical test generation system

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CN JP KR SG US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: KR

122 Ep: pct application non-entry in european phase