WO1999028972A1 - Dispositif a semi-conducteurs a dielectrique capacitif ferroelectrique et procede de realisation - Google Patents

Dispositif a semi-conducteurs a dielectrique capacitif ferroelectrique et procede de realisation Download PDF

Info

Publication number
WO1999028972A1
WO1999028972A1 PCT/US1998/005634 US9805634W WO9928972A1 WO 1999028972 A1 WO1999028972 A1 WO 1999028972A1 US 9805634 W US9805634 W US 9805634W WO 9928972 A1 WO9928972 A1 WO 9928972A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
dielectric
plate
semiconductor device
dielectric material
Prior art date
Application number
PCT/US1998/005634
Other languages
English (en)
Inventor
Beth Ann Baumert
Li-Hsin Chang
Tse-Lun Tsai
Kenneth M. Seddon
Original Assignee
Motorola Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc. filed Critical Motorola Inc.
Priority to AU67686/98A priority Critical patent/AU6768698A/en
Publication of WO1999028972A1 publication Critical patent/WO1999028972A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

Definitions

  • This invention relates, in general, to electronic components, and more particularly, to dielectric materials used in the manufacture of electronic components.
  • Dielectric materials such as silicon dioxide and silicon nitride are used in a variety of applications including use as the insulating material between two conductive plates in a capacitor structure.
  • the effective capacitance value of a given capacitor is determined in part by the dielectric constant of the dielectric material and the area of the dielectric material between the two plates. In order to decrease the relative size of the capacitor and yet form a capacitor having the same capacitance value, there has to be a proportional increase in the dielectric constant of the material used in the capacitor.
  • conventional dielectric materials suffer from one of four problems: they are incompatible with the materials used to form electronic components; they do not have a high enough dielectric constant; they have a Curie temperature within the operational range of the electronic component; or they have high leakage current densities.
  • dielectric material that can be used in the manufacture of electronic components that has a higher dielectric constant value and lower leakage current densities. It would also be advantageous if the dielectric material had a Curie temperature that was below the operational temperature of electronic component so the dielectric material does not change from a paraelectric state to a ferroelectric state during normal operation of the electronic component.
  • FIG. 1 illustrates enlarged cross-sectional views of electronic components formed in accordance with the present invention
  • FIG. 2 is cross-sectional view of a sputtering deposition system
  • FIGs. 3-6 illustrate enlarged cross-sectional views of semiconductor devices formed in accordance with the present invention.
  • the present invention provides a novel dielectric material that can be used in the manufacture of electronic components in a variety of applications. More particularly, the present invention provides examples of how this dielectric material can be used in capacitor structures as the charge storage device for dynamic random access memories (DRAMs) or embedded DRAM structures in either capacitor-over-bit line (COB) or capacitor-under-bit line (CUB) structures.
  • DRAMs dynamic random access memories
  • COB capacitor-over-bit line
  • CB capacitor-under-bit line
  • the present invention can be used to manufacture integrated circuits such as microprocessors, microcontrollers, sensors, embedded DRAMs, static random access memories (SRAMs), an electrically erasable and programmable read only memory (EEPROM), a flash electrically programmable read only memory (flash EPROM), or a flash electrically erasable and programmable read only memory (flash EEPROM).
  • integrated circuits such as microprocessors, microcontrollers, sensors, embedded DRAMs, static random access memories (SRAMs), an electrically erasable and programmable read only memory (EEPROM), a flash electrically programmable read only memory (flash EPROM), or a flash electrically erasable and programmable read only memory (flash EEPROM).
  • EEPROM electrically erasable and programmable read only memory
  • flash EPROM flash electrically programmable read only memory
  • flash EEPROM flash electrically erasable and programmable read only memory
  • the dielectric material of the present invention can also
  • the present invention can be used to replace conventional dielectric materials.
  • the dielectric material of the present invention can be used to replace silicon dioxide or silicon nitride as the insulating material in a gate structure, a capacitor structure, or a non- volatile memory device.
  • the dielectric material of the preferred embodiment comprises barium, titanium, tin, and an oxide. More particularly, the dielectric material can be represented by the formula:
  • X can range from a value greater than zero to about 1.
  • This formula is intended to represent the solid solution form of the dielectric material of the present invention. It should be noted that the solid solution formula differs from a dielectric material that is lightly doped with either barium, titanium, or tin, because each of the elements in the formula (Ba, Ti, Sn, and O) is intended to be a major constituent of the compound. As one skilled in the art will appreciate, this is more than just impurity concentration levels.
  • One unexpected property of the dielectric material of the present invention is that the addition of Sn to a compound provides a material that is classified as a dielectric material. This is in contrast to what might be more commonly expected; a conductive material such as is used in the formation of interconnect structures or leadframes.
  • the addition of tin to the compound of the present invention provides a material that has a dielectric constant greater than 1 and a resistivity greater than 1 x 10 5 ohm-centimeters.
  • a dielectric constant greater than 1 has been the value used by those skilled in the art to classify a material as a dielectric material rather than a conductive or merely resistive material.
  • the material of the present invention is well suited for applications where the material is used to provide electrical isolation between conductive structures, and yet, provide capacitive coupling between the conductive structures. For example, if the dielectric material is placed between two conductive regions or plates, the dielectric material will retard the flow of current between the plates and allow the conductive plates to be capacitively coupled together.
  • the relative value of the concentration of tin in the compound can be varied to adjust the Curie temperature of the compound.
  • the value of X in the formula shown above can be varied to provide a compound having a different Curie temperature.
  • the Curie temperature of a material is the temperature at which the material changes from being paraelectric to ferroelectric or vice versa.
  • a paraelectric material is said to have a single polarization value at the voltage potential applied.
  • a ferroelectric material exhibits a hysteresis in polarization which depends on the previous and present voltage potential applied to the material.
  • the Curie temperature of the material must be below the normal operating temperatures of the electronic component so that the dielectric material does not pass through its Curie point. For example, if an electronic component is normally operated at about 0° Celsius (C) to 100°C, then ideally, the Curie temperature of the material should be - 25°C or lower.
  • a dielectric material In addition to changing its electrical characteristics as described above, a dielectric material also undergoes significant physical stress as it passes through its Curie temperature. Therefore, it is desirable to form the dielectric material so that its Curie temperature is outside of its normal operating temperature range. This prevents the dielectric material, and the electronic component containing the dielectric material, from being damaged during operation because the dielectric material does not transform from the paraelectric state to the ferroelectric state.
  • FIG. 1 illustrates enlarged cross-sectional views of examples of applications in which the dielectric material of the present invention can be used.
  • the dielectric material can be used to form a capacitor structure as shown in electronic components 40 and 50.
  • Electronic component 40 is a capacitor that is formed on a substrate 41.
  • Substrate 41 is preferably a semiconductor substrate, however, other substrate materials used by those skilled in the art can also be used.
  • Electronic component 40 has a layer of dielectric material 43, hereinafter referred to as dielectric layer 43, sandwiched between conductive plates 42 and 44.
  • dielectric layer 43 is preferably paraelectric so that electronic component 40 has a predictable and constant polarization value. Accordingly, the relative amount of tin in the Ba(Ti (1 . x) Sn x )0 3 compound should be adjusted so that the Curie temperature of dielectric layer 43 is less than the normal operating temperature of electronic component 40. For example, a value of x ranging from about 0.15 to 0.3 provides a dielectric material that has a Curie temperature ranging from about -25°C to -100°C. Therefore, as long as electronic component 40 remains above -25°C, dielectric layer 43 remains paraelectric.
  • Table 1 below provides other ranges for the value of X in the compound Ba(Ti (1 . x) Sn x )0 3 producing a dielectric material having various Curie temperatures. Table 1 also lists the property of the material at 0°C and -25°C, respectively.
  • the value of '>0' is used to indicate a concentration greater than zero and can have a value of 0.001, 0.0001, 0.00001, or less depending on the measurement capability.
  • the value of ' ⁇ Y is used to indicate a concentration less than 1 and can have a value of 0.99, 0.999, 0.9999, or greater depending on the measurement capability.
  • dielectric material 43 comprises the compound Ba(Ti (1 . x) Sn x )0 3 , which results in a dielectric material having a bulk dielectric constant ranging from about 28,000 to 35,000.
  • the dielectric constant of the material of the present invention is also greater than about 300, which exceeds the thin film dielectric constant of barium-strontium-titanium-oxide. This corresponds to a bulk dielectric constant for barium-strontium-titanium-oxide of about 15,000 to 20,000.
  • Table 1 a compound has been provided that includes tin, yet provides a dielectric material. It may also be possible to form other compounds that include tin, or tin and titanium, that provides a material having dielectric characteristics.
  • the compound of the preferred embodiment includes oxygen, but it should be understood that other oxides can also be used.
  • electronic component 40 includes conductive plates 42 and 44 that are in direct contact with dielectric material 43. It should be understood that it is not necessary for dielectric material 43 to be in direct contact with conductive plates 42 and 44 as other dielectric materials such as silicon nitride, silicon dioxide, or silicon oxy-nitride can be formed therebetween. Additionally, the lower conductive plate of the capacitor structure can be replaced with a doped region 52 formed in substrate 41 as illustrated in electronic component 50. Therefore, the dielectric material of the present invention can be placed between two conductive regions to provide a capacitor structure. The dielectric material of the present invention can also be used to form an electronic component 60 such as a non-volatile memory cell.
  • dielectric layers 61 and 63 comprising Ba(Ti (1 _ x) Sn x )0 3 can be used to electrically isolate a floating gate 62 from an underlying channel region 67 in substrate 41 and to electrically isolate floating gate 62 from a control gate 64.
  • Channel region 67 refers to the portion of substrate 41 between a source region 65 and a drain region 66.
  • dielectric layers 61 and 63 need not solely be formed using the dielectric material of the present invention and that it is not necessary that both layers comprise Ba(Ti (1 _ x) Sn x )0 3 .
  • the dielectric material of the present invention is ferroelectric when used in a nonvolatile memory.
  • x can have a value ranging from about 0.01 to 0.1 or from about 0.05 to 0.1.
  • FIG. 1 Also shown in FIG. 1 is an electronic component 70 that illustrates how the dielectric material of the present invention can be used as a gate dielectric material.
  • Electronic component 70 has a layer of dielectric material 71 between a gate structure 72 and substrate 41 that is used to electrically isolate gate structure 72 from a channel region 75.
  • a voltage potential is placed on gate structure 72 to modulate channel region 75 between a source region 73 and a drain region 74.
  • One method of forming dielectric materials 43, 61, 63, or 71 is to use a metal organic decomposition process or a solution-gelation (sol-gel) process.
  • a solution is prepared containing precursors of the desired elements in the proper ratios.
  • the solution is then dispensed or spun over the surface of a substrate to form a layer of the solution across the substrate.
  • the solution is then heated or annealed to drive off the organic materials in the solution, thereby forming a layer of dielectric material having the desired composition.
  • a source of tin can be added to the solution using a precursor such as tin beta-n-butoxide, tin chloride, tin acetate, tin nitrate, tin lactate, tin ammonium acetate, tin tetra-isopropoxide, or tin isopropoxide.
  • a precursor such as tin beta-n-butoxide, tin chloride, tin acetate, tin nitrate, tin lactate, tin ammonium acetate, tin tetra-isopropoxide, or tin isopropoxide.
  • a source of titanium can be added to the solution using a precursor such as titanium tetra-n-butoxide, titanium di-tertiary- butoxyl-tetramethyl heptanodionate, titanium tetra-tertiary butoxide, titanium ditetramethyl-heptano-dionate disopropoxide, titanium tetraethoxide, titanium lactate, titanium ammonium acetate, titanium tetra-isopropoxide, or titanium isopropoxide.
  • a precursor such as titanium tetra-n-butoxide, titanium di-tertiary- butoxyl-tetramethyl heptanodionate, titanium tetra-tertiary butoxide, titanium ditetramethyl-heptano-dionate disopropoxide, titanium tetraethoxide, titanium lactate, titanium ammonium acetate, titanium tetra-isopropoxide, or titanium isopropoxide.
  • a source of barium can be added to the solution using a precursor such as beta-diketonate complexes of barium tetramethylheptanodionate, barium hexaflouroacetylacetonate, barium(2,2,6,6-tetramethyl-3,5- heptanedione) 2 , barium hexaflouroacetylacetone, or barium tetrafluoroacetylacetone.
  • a precursor such as beta-diketonate complexes of barium tetramethylheptanodionate, barium hexaflouroacetylacetonate, barium(2,2,6,6-tetramethyl-3,5- heptanedione) 2 , barium hexaflouroacetylacetone, or barium tetrafluoroacetylacetone.
  • FIG. 2 illustrates a cross-sectional portion of a radio frequency (RF) sputtering system 10.
  • RF radio frequency
  • System 10 includes a sputtering chamber 11 in which the RF sputtering occurs.
  • a sputtering target 12 is utilized as a source of material for forming a film 16 such as a dielectric layer on a surface of a semiconductor substrate 13, which is placed on an heating element 14. Material is transferred from sputtering target 12 to film 16 by RF sputtering.
  • An RF voltage source 15 is coupled to target 12 and to substrate 13 to facilitate the RF sputtering operation.
  • Sputtering target 12 comprises the desired amounts of barium, titanium, and tin and can be formed by mixing barium oxide, titanium oxide, and tin oxide in the correct proportions to form a ceramic sputtering target. Subsequent to mixing, pressure and temperature are utilized to transform the mixture into sputtering target 12. For example, the mixture can be cold pressed at a pressure of about three hundred atmospheres (atm), and then sintered at a temperature of approximately 1200° C at atmospheric pressure. These pressures and temperatures can vary depending on furnace and target sizes and also on target composition. Thereafter, target 12 is placed in sputtering chamber 11 along with substrate 13.
  • Target 12 and substrate 13 are connected to RF voltage source 15 in order to provide an electric field and facilitate sputtering material from target 12 onto the surface of substrate 13.
  • voltage source 15 applies approximately five hundred volts to target 12 and substrate 13.
  • a plasma is formed using an argon-oxygen or oxygen ambient within chamber 11 in order to complete the RF sputtering.
  • RF sputtering operations are well known to those skilled in the art.
  • dielectric layer 16 it is also possible to form dielectric layer 16 using a sputtering target made from barium oxide, tin oxide, and titanium powder.
  • the sputtering target and substrate 13 are placed into sputtering chamber 11, which is filled with an ambient containing oxygen.
  • oxygen is incorporated in the desired proportion to form a dielectric material.
  • the dielectric material of the present invention uses a metallorganic chemical vapor deposition (MOCVD) process.
  • MOCVD metallorganic chemical vapor deposition
  • some of the precursors listed earlier are transported to a reaction chamber using a carrier gas in the desired proportions.
  • the reaction conditions depend in part on the precursors selected and will be understood by those skilled in the art.
  • a transistor 82 is formed on a substrate 81 using conventional techniques.
  • transistor 82 is a field effect transistor (FET) that has current carrying electrodes 87 and 88 formed in semiconductor substrate 81.
  • Current carrying electrodes 87-88 can be the source and drain regions of transistor 82.
  • transistor 82 has a gate structure 83 that is used to control a current flow between current carrying electrodes 87 and 88.
  • Gate structure 83 for example, can have a conductive layer 84 that is capacitively coupled to semiconductor substrate 81 by a gate oxide layer 85.
  • Gate structure 83 can also have sidewall spacers 86 that can be optionally formed to electrically isolate conductive layer 84 from neighboring structures (not shown).
  • An insulating layer 110 is then deposited over transistor 82 and a surface 111 of substrate 81.
  • a layer of silicon dioxide or phosphosilicate glass is deposited using either a chemical vapor deposition process (CVD) or a plasma enhanced chemical vapor deposition (PECVD) process.
  • the thickness of insulating layer 110 can vary as necessary and can range for example from about 300 angstroms (A) to 5,000 A.
  • a chemical mechanical polish (CMP) process is then used to planarize the top surface of insulating layer 110.
  • CMP chemical mechanical polish
  • a conventional photolithographic masking and etch process is used to form openings 112 and 113 that expose portions of current carrying electrodes 87 and 88, respectively.
  • a conductive material such as tungsten, titanium suicide, titanium nitride, polysilicon, or amorphous silicon is formed in openings 112 and 113 to form plugs 93 and 114.
  • the layers of titanium suicide 90 and 91 can improve the electrical connection between plugs 93 and 114 and current carrying electrodes 87 and 88 and retard the formation of an oxide layer on current carrying electrodes 87 and 88. If formed, layers of titanium suicide 90 and 91 can have a thickness of about 50 A to 500 A.
  • bit line 94 is formed from a conductive material such as aluminum or the like. Bit line 94 is formed using conventional deposition and etch techniques. Once formed, bit line 94 is connected to current carrying electrode 88 via plug 93. Thereafter, an insulating layer 89 is formed over bit line 94, plug 114, and insulating layer 110. Insulating layer 89 is preferably a layer of silicon dioxide that is about 300 A to 5,000 A thick. Depending on the thickness and planarization of insulating layer, a CMP process can be used after insulating layer 89 is formed to provide a sufficiently planar surface to allow further processing.
  • An opening 115 is formed in insulating layer 89 so that at least a portion of plug 114 is exposed.
  • a plug 92 is formed in opening 115 using a material that is compatible with plug 114 such as one of the materials listed above.
  • the combination of plug 92, plug 114, and perhaps layer of titanium suicide 90 provides an electrical connection between current carrying electrode 87 of transistor 82 and a capacitor structure 99 that is subsequently formed over transistor 82 as explained below.
  • capacitor structure 99 includes a layer of dielectric material 97 that is formed between an upper conductive plate 98 and a lower conductive plate 116.
  • conductive plate 116 is made from two layers, namely, a layer of platinum 96 on a layer of titanium nitride 95.
  • conductive plate 116 may be formed from a single layer or a plurality of layers.
  • conductive plate 116 can be made from a single layer of platinum, a single layer of iridium, a layer of platinum on a layer of iridium on a layer of titanium nitride, a layer of iridium oxide on a layer of iridium, a layer of iridium oxide on a layer of iridium on a layer of titanium nitride, a layer of ruthenium oxide on a layer of ruthenium, a layer of ruthenium oxide on a layer of iridium oxide, a layer of platinum doped with tin, a single layer of platinum alloy, a layer of palladium on a layer of titanium nitride, or a layer of strontium-ruthenium oxide on a layer of titanium nitride.
  • Conductive plate 116 can be form by depositing the desired materials using a sputtering, electroplating, electron beam vaporization, CVD, or similar process. A photolithographic masking and etch process are used to pattern conductive plate 116 as shown in FIG. 3. Dielectric layer 97 is then formed on conductive plate 116 using one of the techniques described above. In a DRAM application, dielectric material 97 should be paraelectric so that the capacitance value of capacitor structure 99 is consistent during the operation of semiconductor device 80. Accordingly, dielectric layer 97 includes Ba(Ti (1 - x) Sn x )0 3 and X is chosen so that dielectric layer 97 remains paraelectric over the anticipated operating temperatures of semiconductor device 80. In most applications, X should have a value greater than about
  • dielectric layer 97 does not become ferroelectric. More particularly, if semiconductor device 80 is to be operated between 0°C and 70°C, then X can range from about 0.15 to 0.3. Additionally, if semiconductor device 80 is to be operated between -25°C and 70°C, then X can range from about 0.18 to 0.3. As mentioned earlier, the presence of barium, titanium, and tin in the formula Ba(Ti (1 . x) Sn x )0 3 is intended to indicate the solid solution formula of dielectric material 97.
  • a dielectric material that has significantly higher dielectric constant than other materials such as barium strontium titanate (BST).
  • BST barium strontium titanate
  • the material of the present invention differs from previously known materials in that tin and titanium are used in the compound as major constituents as opposed to merely impurities.
  • dielectric layer 97 can vary so that capacitor structure 99 has the desired capacitance value.
  • dielectric layer 97 has a thickness ranging from about 50 A to 3,000 A so that capacitor structure 99 has a capacitance density value ranging from
  • conductive plate 98 is formed by depositing a material that is compatible with the interconnect structures (not shown) that are used to provide electrical connection to capacitor structure 99 and transistor 82.
  • conductive plate 98 can be a single layer of aluminum alloy or a plurality of layers suggested above for the formation of conductive plate 116.
  • a conventional photolithographic masking and etch process are used to pattern conductive plate 98 and dielectric layer 97 as is shown in FIG. 3.
  • FIG. 4 is an enlarged cross-sectional view of capacitor structure 120 as it might be formed on insulating layer 89 so that it would be connected to the source or drain region of a transistor 82 (see FIG. 3) by plug 92.
  • the capacitive coupling between the plates of capacitor structure 120 and its dielectric material is increased by increasing the surface area of the dielectric material that is covered by the plates.
  • a layer of titanium suicide 121 (indicated in FIG. 4 with a bracket 127) is provided by forming in sequence a layer of titanium suicide 121, a layer of titanium nitride 122, a layer of ruthenium 123, and a layer of ruthenium oxide 124 using conventional techniques.
  • the layer of titanium suicide 121 is used to improve the electrical conductivity of conductive plate 127 and the layer of ruthenium oxide 124 acts as a source of oxygen to replenish oxygen vacancies that may form in dielectric layer 97.
  • a conventional photolithographic masking and etch process are used to pattern layers 121-124 so that conductive plate 127 has sidewalls 128.
  • Dielectric layer 97 is then formed using one of the methods described above so that it is in contact with the sidewalls 128 of conductive plate 127.
  • the overall thickness of conductive plate 127 can range from about 500 A to over 10,000 A.
  • the thickness of conductive plate 127 contributes significantly to the overall surface area of conductive plate 127, and thus, contributes significantly to the capacitance value of capacitor structure 120.
  • Conductive plate 127 can have significant topography because sidewalls 128 are orthogonal to insulating layer 89. Therefore, it may be necessary to form dielectric layer 97 using the MOCVD process described above.
  • a CVD or MOCVD process may be necessary to form conductive plate 98 so that both dielectric layer 97 and conductive plate 98 have the proper thickness over the sidewalls 128 of conductive plate 127.
  • an alternative method of forming capacitor structure 120 is provided that reduces the problems of forming dielectric layer 97 and conductive plate 98 along the sidewalls 128 of conductive plate 127 (see FIG. 4).
  • the photolithographic mask and etch process can be modified such that conductive plate 127 has sidewalls 130 that are tapered. More particularly, the sputtered etch process used to pattern layers 121-124 can be directed at an angle other than orthogonal to substrate 81 (see FIG. 3) so that the sidewalls 130 of conductive plate 127 are tapered.
  • the angle of sidewalls 130 relative to the surface 111 of substrate 81 can be varied as necessary and can range for example from about 5° to 35° off from orthogonal as shown in FIG. 4.
  • conductive plate 127 consisted of 4 layers. It should be understood that conductive plate 127 can be a single layer or a plurality of layers as suggested above for the formation of conductive layer 116 (see FIG. 3).
  • capacitor structure 99 of FIG. 3 is provided.
  • the surface area of dielectric layer 97 can be increased by forming all or part of capacitor structure 99 in a recess 137.
  • recess 137 can be formed in insulating layer 89 so that it has sidewalls 135 and a bottom surface 136 using a wet etch process, a reactive ion etch (RIE) process, or a combination of the two.
  • Dielectric layer 97 and conductive plates 116 and 98 are then formed in recess 137 using the techniques described above.
  • the present invention provides a compound that can be used to form dielectric materials in electronic components.
  • the present invention also provides methods of forming the dielectric material, such as by forming a sputtering target, and provides applications for its use.
  • a dielectric layer formed in accordance with the present invention has a dielectric constant that is higher than previously known dielectric materials.
  • an electronic component such as a DRAM can be formed in less area, yet have the same capacitance value as if the electronic component had been formed using conventional materials. Therefore, the present invention allows electronic components to be formed using less surface area, and thus, at a lower manufacturing cost.
  • the present invention provides a variety of capacitor structures that employ the dielectric material of the present invention. These capacitor structures can be connected to transistors to form DRAM cells. DRAM cells formed in accordance with the present invention can have a smaller cell size than DRAMs formed using BST because the dielectric constant of the dielectric material of the present invention is higher. Accordingly, a smaller capacitor structure can be formed that has the same charge storage capability as a larger capacitor structure formed with BST.

Abstract

L'invention concerne un dispositif (08) à semi-conducteurs comprenant un transistor (82) et une structure capacitive (99. 120). Cette structure (99, 120) comprend un diélectrique (97) entre deux plaques conductrices (98, 116). Le transistor (82) présente des électrodes (87, 88) porteuses de courant, dont l'une se connecte à la structure capacitive (99, 120) à l'aide d'une fiche (92).
PCT/US1998/005634 1997-11-28 1998-03-20 Dispositif a semi-conducteurs a dielectrique capacitif ferroelectrique et procede de realisation WO1999028972A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU67686/98A AU6768698A (en) 1997-11-28 1998-03-20 Semiconductor device with ferroelectric capacitor dielectric and method for making

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US98043097A 1997-11-28 1997-11-28
US08/980,430 1997-11-28

Publications (1)

Publication Number Publication Date
WO1999028972A1 true WO1999028972A1 (fr) 1999-06-10

Family

ID=25527549

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1998/005634 WO1999028972A1 (fr) 1997-11-28 1998-03-20 Dispositif a semi-conducteurs a dielectrique capacitif ferroelectrique et procede de realisation

Country Status (2)

Country Link
AU (1) AU6768698A (fr)
WO (1) WO1999028972A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002078084A2 (fr) * 2001-03-23 2002-10-03 Infineon Technologies Ag Procede de fabrication de cellules de memoire ferroelectriques
EP1324392A1 (fr) * 2001-12-28 2003-07-02 STMicroelectronics S.r.l. Condensateur pour des dispositifs intégrés à semi-conducteur

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5343353A (en) * 1991-08-28 1994-08-30 Hitachi, Ltd. Semiconductor device and process of producing the same
WO1996002067A1 (fr) * 1994-07-11 1996-01-25 Symetrix Corporation Condensateurs pour circuits integres et leur procede de fabrication
US5499207A (en) * 1993-08-06 1996-03-12 Hitachi, Ltd. Semiconductor memory device having improved isolation between electrodes, and process for fabricating the same
US5605858A (en) * 1994-08-01 1997-02-25 Texas Instruments Incorporated Method of forming high-dielectric-constant material electrodes comprising conductive sidewall spacers of same material as electrodes

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5343353A (en) * 1991-08-28 1994-08-30 Hitachi, Ltd. Semiconductor device and process of producing the same
US5499207A (en) * 1993-08-06 1996-03-12 Hitachi, Ltd. Semiconductor memory device having improved isolation between electrodes, and process for fabricating the same
WO1996002067A1 (fr) * 1994-07-11 1996-01-25 Symetrix Corporation Condensateurs pour circuits integres et leur procede de fabrication
US5605858A (en) * 1994-08-01 1997-02-25 Texas Instruments Incorporated Method of forming high-dielectric-constant material electrodes comprising conductive sidewall spacers of same material as electrodes

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002078084A2 (fr) * 2001-03-23 2002-10-03 Infineon Technologies Ag Procede de fabrication de cellules de memoire ferroelectriques
WO2002078084A3 (fr) * 2001-03-23 2003-03-13 Infineon Technologies Ag Procede de fabrication de cellules de memoire ferroelectriques
US6806097B2 (en) 2001-03-23 2004-10-19 Infineon Technologies Ag Method for fabricating ferroelectric memory cells
EP1324392A1 (fr) * 2001-12-28 2003-07-02 STMicroelectronics S.r.l. Condensateur pour des dispositifs intégrés à semi-conducteur

Also Published As

Publication number Publication date
AU6768698A (en) 1999-06-16

Similar Documents

Publication Publication Date Title
US6555428B2 (en) Ferroelectric capacitor and method for fabricating the same
KR0183732B1 (ko) 반도체 장치의 캐패시터 제작방법
KR100297210B1 (ko) 강유전체커패시터및다른커패시터구조체를위한고온전극-배리어
US6930039B2 (en) Method of fabricating a contact structure having a composite barrier layer between a platinum layer and a polysilicon plug
US6900497B2 (en) Integrated circuit with a capacitor comprising an electrode
US6372286B1 (en) Barium strontium titanate integrated circuit capacitors and process for making the same
US6686620B2 (en) FRAM and method of fabricating the same
EP0911871A2 (fr) Dispositif de mémoire semi-conducteur avec couche mince ferroélectrique
Yoshida et al. Chemical vapor deposition of (Ba, Sr) TiO3
US6864146B2 (en) Metal oxide integrated circuit on silicon germanium substrate
KR100275853B1 (ko) 반도체장치 및 그 제조방법
KR100238249B1 (ko) 고유전체 커패시터의 제조방법
WO1999028972A1 (fr) Dispositif a semi-conducteurs a dielectrique capacitif ferroelectrique et procede de realisation
KR100282459B1 (ko) 강유전성램 캐패시터의 제조방법
US8102023B2 (en) Capacitor insulating film, capacitor, and semiconductor device
KR100231597B1 (ko) 반도체 소자의 캐패시터 제조방법
KR100398661B1 (ko) 집적화 전자기소자용 박막 커패시터 제조 방법
KR0151241B1 (ko) 강유전체막을 구비한 반도체장치
KR19990030185A (ko) 전자 구성 요소
KR20010001595A (ko) 캐패시터 제조 방법
JP4167792B2 (ja) 半導体装置及びその製造方法
KR100331781B1 (ko) 반도체 소자의 캐패시터 형성 방법
KR0150985B1 (ko) 산화물 전극을 이용한 커패시터 제조방법
KR19980066717A (ko) 에프램(fram)셀의 제조방법
KR20030025691A (ko) 이종 질화물의 이중 방지막을 갖는 커패시터 및 그의 전극형성 방법

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GE GH HU ID IL IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG UZ VN YU ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW SD SZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN ML MR NE SN TD TG

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: CA

NENP Non-entry into the national phase

Ref country code: KR

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

NENP Non-entry into the national phase

Ref country code: CA

122 Ep: pct application non-entry in european phase