WO1999028971A1 - Electronic hybrid component and method for the production thereof - Google Patents

Electronic hybrid component and method for the production thereof Download PDF

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Publication number
WO1999028971A1
WO1999028971A1 PCT/DE1997/002812 DE9702812W WO9928971A1 WO 1999028971 A1 WO1999028971 A1 WO 1999028971A1 DE 9702812 W DE9702812 W DE 9702812W WO 9928971 A1 WO9928971 A1 WO 9928971A1
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WO
WIPO (PCT)
Prior art keywords
chip
carrier
implanted
hybrid component
lowered
Prior art date
Application number
PCT/DE1997/002812
Other languages
German (de)
French (fr)
Inventor
Klaus-Dieter Preuss
Andreas Schmidt
Dieter Stollberg
Horst Wallerer
Arndt Steinke
Original Assignee
Cis Institut Für Mikrosensorik
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to DE19720300A priority Critical patent/DE19720300B4/en
Application filed by Cis Institut Für Mikrosensorik filed Critical Cis Institut Für Mikrosensorik
Priority to EP97954329A priority patent/EP1036416A1/en
Priority to PCT/DE1997/002812 priority patent/WO1999028971A1/en
Publication of WO1999028971A1 publication Critical patent/WO1999028971A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the invention relates to an electronic hybrid component with a chip
  • On chip arrangement in which at least one implanted chip is arranged on a silicon carrier and a method for producing this component.
  • the application of the invention makes it possible to make contact with implanted components which have electrical connections on the front and the back, while at the same time realizing an electrical contact between the back of the implanted component and the front of the carrier material.
  • Chip arrangement without electrical connection to the rear of the implanted component.
  • the structuring of the carrier material takes place on one level using the standard methods of microelectronics and microsystem technology. This will put the on assembling components and the connection, for example using conductive adhesive for the rear side contact on the carrier chip, and the electrical contacting of the front side contacts is realized by wire bonding or flip chip assembly.
  • the compensation takes place
  • the components are coplanarly embedded in the silicon substrate.
  • New products and sensory principles of action require the component to be implanted to be lowered into the carrier down to a depth of a few hundred micrometers in order to implement a mass technology that is capable of production.
  • the invention is based on the object of specifying an electronic hybrid component and a method for its production, the component having an electrical rear-side contacting of implanted components with a simultaneous coplanar chip-on-chip arrangement and the method for producing this component using the in the microelectronics and microsystem technology usual process engineering allowed.
  • the object is achieved with a component in which at least one cavity is incorporated in a carrier substrate, in which there is an electrical insulation layer with a metal layer arranged above it and in which a chip in the cavity is electrically contacted with the metal layer.
  • the component enables the implantation of active and / or passive electronic, optoelectronic, micromechanical and / or actuator components, which consist of solid materials and have semiconductor or microsystem functions. It can be used for conventional contacting techniques such as ultrasound and thermosonic bonding or conductive adhesive.
  • the front connection of the chip can be realized conventionally by Al ultrasonic bonding with a flat bridge height.
  • the arrangement of the LED is expediently such that its surface is a few micrometers below the surface level of the receiver chips. In this way, direct radiation of the emitted light onto the photosensitive surface is avoided.
  • reflection of the metallized trench surface means that almost the entire emitter power can be used to obtain the signal.
  • the manufacturing method according to the invention consists in that lowered regions introduced by anisotropic etching are produced in the silicon carrier and that the structuring for producing the electrically conductive ones
  • Connection thread the lowered areas and those on the planar Surface guideway structures are made by a multiple metallization system.
  • the lowered structures are expediently isolated by oxidation or by depositing insulator layers on the carrier, then the lower regions and the carrier material are metallized, and then the multiple metallization layer is structured within a photolithographic structuring process Adherence to certain minimal structure widths instead (the multiple metallization system is advantageously generated by the fact that the upper metallization layer is used as a masking layer for the subsequent etching processes), then the elements to be implanted are placed and contacted and then electrical contact is made between the carrier chip and the front of the implant.
  • the hybrid component comprising the carrier chip and implant can be electrically contacted on a circuit carrier (e.g. a printed circuit board) in the form of wire bonding, flip-chip contacting, TAB and the like.
  • a circuit carrier e.g. a printed circuit board
  • Silicon components are produced by anisotropic etching in the silicon-lowered regions, which are electrically insulated from the substrate material and have a metallization layer for contacting. This is at the same time an electrical contact between the back of the implanted component and the front of the
  • Carrier material generated generated.
  • the method according to the invention makes it possible to establish an electrically conductive connection between the lowered region and the surface of the carrier on which the circuit is located or is further implemented within a photolithographic structuring process. This creates the conditions for the simultaneous realization of an electrical contact between the back of the implanted component and the front of the carrier material.
  • Figure 1 a hybrid component of conventional design in
  • Figure 2 is a sectional view of a component manufactured according to the invention.
  • FIG. 1 shows a hybrid component in chip on chip design.
  • photosensitive layers are arranged on the chip, the direct irradiation of the photosensitive layer with disturbing scattered light leads to errors in the photoelectric evaluation.
  • Chip-on-chip arrangement has a planar structure of silicon carrier 1 and implanted chips of any substrate material. With this arrangement there is electrical contacting of the back of the implanted components.
  • the component can be produced using the methods customary in microelectronics and microsystem technology. In the case explained here, specially adapted method steps are used. In the example shown, an optical PIN diode array with eight diode arrays 3 grouped around the LED 2 to be implanted is used as the carrier.
  • the implanted component is assembled by microdispensing conductive adhesive with a tightly tolerated amount.
  • Process steps for the realization of lowered areas in the carrier by appropriate etching processes for use Subsequently, layers are deposited or oxidized to isolate the lowered structures on the carrier. Afterwards, a metallization of the lowered areas and of the carrier material is provided.
  • the electrically conductive connection between the lowered area and the structures on the planar surface of the carrier material is produced within a photolithographic structuring process while observing certain minimal structure widths. With these process steps, electrical contact is simultaneously achieved between the landing surface of the implanted component and the front of the carrier material.
  • the electrically conductive connection between the lowered areas and the interconnect structures located on the planar surface is realized by a triple metallization system.
  • the upper metallization layer serves as a masking layer for the subsequent etching processes.
  • the Proven resolution limit is 10 ⁇ m structure width up to the edge of the lowered area.
  • a carrier substrate is coated using a passivation layer made of silicon nitride.
  • the areas to be lowered are structured in a separate photolithographic step.
  • the silicon carrier 1 enables the implantation of active and / or passive electronic, optoelectronic, micromechanical and / or actuator components, which consist of solid materials and perform semiconductor and microsystem technical functions. After the hardening process, the electrical contacting of the carrier chip and implant is carried out by wire bonding.
  • the TiN layer on top forms a non-oxidizing metal surface and is therefore suitable for conventional contacting techniques such as
  • Ultrasonic and thermosonic bonding or conductive adhesive can be used.
  • the front connection of LED 2 is realized conventionally by Al-UI-ultrasound bonding with a flat bridge height.
  • the arrangement of the LED 2 is such that the upper edge is a few micrometers below the level of the receiver chips. In this way, direct radiation of the emitted light onto the photosensitive surface is avoided.
  • reflection of the metallized trench surface means that almost the entire emitter power can be used for signal generation.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Led Device Packages (AREA)

Abstract

The aim of the invention is to provide an electronic hybrid component and a method for the production thereof. The component has a reverse side electrical bonding of the implanted components and a coplanar chip-on-chip arrangement. The method for the production of said component enables the utilization of conventional process engineering methods used in microelectronics and microsystems technology. According to the invention, this is achieved by providing a component with at least one cavity on a carrier substrate comprising an electrical insulation coating with a superimposed metal coating. A chip is electrically bonded to the metal coating in the cavity. The invention relates to an electronic hybrid component with a chip-on-chip arrangement in which at least one implanted chip is arranged on a silicon carrier and to a method for the production of said component.

Description

Elektronisches Hybrid-Bauelement und Verfahren zu seiner Herstellung Hybrid electronic component and method for its production
Die Erfindung betrifft ein elektronisches Hybrid-Bauelement mit ChipThe invention relates to an electronic hybrid component with a chip
On Chip - Anordnung, bei dem mindestens ein implantiertes Chip auf einem Siliziumträger angeordnet ist und ein Verfahren zur Herstellung dieses Bauelementes.On chip arrangement, in which at least one implanted chip is arranged on a silicon carrier and a method for producing this component.
Die Anwendung der Erfindung ermöglicht eine Kontaktierung von implantierten Bauelementen, die elektrische Anschlüsse auf der Vorder- und der Rückseite aufweisen, bei gleichzeitiger Realisierung eines elektrischen Kontaktes zwischen der Rückseite des implantierten Bauelementes und der Vorderseite des Trägermaterials.The application of the invention makes it possible to make contact with implanted components which have electrical connections on the front and the back, while at the same time realizing an electrical contact between the back of the implanted component and the front of the carrier material.
Die im Stand der Technik bekannten Technologien zur Herstellung hybrider Bauelemente gestatten entweder die elektrische Ruckseitenkontaktierung aufgesetzter Bauelemente auf Leitbahnenstrukturen als Chip On Chip - Anordnung oder die quasimonolithische Chip OnThe technologies known in the prior art for producing hybrid components permit either the electrical rear-side contacting of components placed on interconnect structures as a chip-on-chip arrangement or the quasi-monolithic chip-on
Chip - Anordnung ohne elerktri-sche Verbindung zur Rückseite des implantierten Bauelementes.Chip arrangement without electrical connection to the rear of the implanted component.
Bei der Chip On Chip - Anordnung erfolgt die Strukturierung des Trägermaterials mit den Standardverfahren der Mikroelektronik und Mikrosystemtechnik in einer Ebene. Dabei wird das Aufsetzen der zu montierenden Bauelemente und das Verbinden z.B. mittels Leitkleber für den Rückseitenkontakt auf den Trägerchip vorgenommen und die elektrische Kontaktierung der Vorderseitenkontakte durch Drahtbondung oder Flipchip-Montage realisiert. Bei Anwendung der Hybrid- bauelemente in Flipchip-Montagen erfolgt der Ausgleich derIn the chip-on-chip arrangement, the structuring of the carrier material takes place on one level using the standard methods of microelectronics and microsystem technology. This will put the on assembling components and the connection, for example using conductive adhesive for the rear side contact on the carrier chip, and the electrical contacting of the front side contacts is realized by wire bonding or flip chip assembly. When using the hybrid components in flip-chip assemblies, the compensation takes place
Höhendifferenzen der Kontaktflächen von Trägerchip und aufgesetzten Bauelementen beispielsweise durch den Einsatz von Mehrfach-An-stud-bumps. Bei der quasimonolithischen Chip On Chip - Anordnung werden die Bauelemente koplanar in die Trägersubstrate aus Silizium eingebettet.Height differences of the contact surfaces of the carrier chip and the attached components, for example through the use of multiple an-stud bumps. In the quasi-monolithic chip-on-chip arrangement, the components are coplanarly embedded in the silicon substrate.
Dabei erfolgt keine elektrische Ruckseitenkontaktierung durch das Einkleben der zu montierenden Bauelemente. Die Oberflächenplanie- rung, .sowie die Kontaktierung der implantierten Bauelemente durch Dünn-schichtverfahren wird von der Vorderseite ausgeführt.There is no electrical contact from the rear by gluing the components to be assembled. The surface leveling, as well as the contacting of the implanted components by thin-layer processes is carried out from the front.
Es sind ferner eine Reihe von Verfahren zur monolithischen Integration verschiedener Halbleiterstrukturen und -materialien bekannt, z.B. durchA number of methods for monolithically integrating various semiconductor structures and materials are also known, e.g. by
Heteroepitaxie.Heteroepitaxy.
Mit den gegenwärtigen Lithografie- und Strukturierungsverfahren der Mikroelektronik und Mikrosystemtechnik werden Strukturen in einerWith the current lithography and structuring processes in microelectronics and microsystem technology, structures are combined in one
Ebene bis in den Submikromelerbereich realisiert, wobei maximale Topologieunterschiede bis zu einigen μm überwunden werden. Spezielle Verfahren der Mikrosystemtechnik erlauben nach einer KOH-Ätzung in das Silizium bis zu einer Tiefe von 50 μm eine gleich- zeitige Strukturierung auf der Oberfläche, den Grabenseiten und innerhalb des abgesenkten Gebietes.Level down to the submicron range, with maximum topology differences of up to a few μm being overcome. Special methods of microsystem technology allow for a simultaneous structuring on the surface, the trench sides and within the lowered area after a KOH etching into the silicon down to a depth of 50 μm.
Aufgrund der optischen Bedingungen für eine zufriedenstellende Auflösung auf der Oberfläche sind der fortschreitenden Tiefenabsenkung enge Grenzen gesetzt. Ferner ergeben sich Probleme für eine ausrei- chende und reproduzierbare Bedeckung der Grabenkanten mit Photore- sist bei größeren Tiefenabsenkungen. Bei diesen Tiefen reißt der Fotolack an den Kanten der abgesenkten Gebiete ab. Bei der Verwendung von Lötstopplacken, die aufgrund ihres Füllstoffanteiles eine bessere Kantenabdeckung gewährleisten, werden die erforderlichen minimalen Strukturbreiten von ca. 10 μm nicht aufgelöst. Bei der Anwendung eines Lift-off-Prozesses wird eine Lackfreiheit für die abgesenkten Grabengebiete bei gleichzeitiger Ausbildung der notwendigen überhängenden Lackkanten für das eigentliche Liften nicht erreicht. Damit werden für die üblichen fotolithografischen Prozeßschritte, das Beschichten, Belichten und Entwickeln Verfahrens- grenzen erreicht.Due to the optical conditions for a satisfactory resolution on the surface, the progressive depth reduction is limited. Furthermore, problems arise for adequate and reproducible covering of the trench edges with photoresist with greater subsidence. It breaks at these depths Photoresist from the edges of the lowered areas. When using solder resists, which guarantee better edge coverage due to their filler content, the required minimum structure widths of approx. 10 μm are not resolved. When using a lift-off process, no paint is achieved for the lowered trench areas with simultaneous formation of the necessary overhanging paint edges for the actual lifting. This means that process limits are reached for the usual photolithographic process steps, coating, exposure and development.
Anordnungen und Verfahren zur Herstellung hybrider Bauelemente, welche sowohl eine elektrische Ruckseitenkontaktierung der zu implantierenden Bauelemente als auch eine planare quasimonolithische Chip On Chip - Anordnung realisieren, sind dem Stand der Technik nach nicht bekannt.Arrangements and methods for the production of hybrid components which implement both an electrical rear-side contacting of the components to be implanted and a planar quasi-monolithic chip on chip arrangement are not known in the prior art.
Neue Produkte und sensorische Wirkprinzipien erfordern zur Realisierung einer produktionsfähigen Massentechnologic die Absenkung des zu implantierenden Bauelementes in den Träger bis zu einer Tiefe von einigen Hundert Mikrometern.New products and sensory principles of action require the component to be implanted to be lowered into the carrier down to a depth of a few hundred micrometers in order to implement a mass technology that is capable of production.
Der Erfindung liegt die Aufgabe zugrunde, ein elektronisches Hybrid- Bauelement und ein Verfahren zu seiner Herstellung anzugeben, wobei das Bauelement eine elektrische Ruckseitenkontaktierung von implantierten Bauelementen bei gleichzeitiger koplanarer Chip On «Chip- Anordnung aufweist und das Verfahren zur Herstellung dieses Bauelementes die Verwendung der in der Mikroelektronik und Mikrosystemtechnik üblichen Verfahrenstechnik gestattet. Erfindungsgemäß wird die Aufgabe mit einem Bauelement gelöst, bei dem in einem Trägersubstrat mindestens eine Kavitat eingearbeitet ist, in der sich eine elektrische Isolationsschicht mit einer darüber angeordneter Metallschicht befindet und bei dem in der Kavitat ein Chip mit der Metallschicht elektrisch kontaktiert ist.The invention is based on the object of specifying an electronic hybrid component and a method for its production, the component having an electrical rear-side contacting of implanted components with a simultaneous coplanar chip-on-chip arrangement and the method for producing this component using the in the microelectronics and microsystem technology usual process engineering allowed. According to the invention, the object is achieved with a component in which at least one cavity is incorporated in a carrier substrate, in which there is an electrical insulation layer with a metal layer arranged above it and in which a chip in the cavity is electrically contacted with the metal layer.
Vorteilhafte Ausgestaltungen des erfindungsgemäßen Bauelementes sind in den Unteransprüchen 2 bis 4 angegeben.Advantageous refinements of the component according to the invention are specified in subclaims 2 to 4.
Das Bauelement ermöglicht die Implantation von aktiven und/oder passiven elektronischen, optoelektronischen, mikromechanischen und/oder aktorischen Bauelementen, die aus Festkörpermaterialen bestehen und halbleiter- bzw. mikrosystemtechnische Funktionen haben. Es ist für konventionelle Kontaktierungstechniken, wie Ultraschall- und Thermosonikbondung oder Leitklebung verwendbar. Der Vorderseitenanschluß des Chips kann konventionell durch Al-Ultraschall-Bondung mit flacher Brückenhöhe realisiert werden. Beim Implantieren einer LED erfolgt die Anordnung der LED zweckmäßig so, daß deren Oberfläche wenige Mikrometer unter dem Oberflächenniveau der Empfängerchips liegt. Auf diese Weise wird eine Direkteinstrahlung des abgestrahlten Lichts auf die fotoempfindliche Oberfläche vermieden. Neben der direkten LED-Abstrahlung in das über der Gesamtanordnung liegende Gebiet kann durch Reflexion von der metallisierten Grabenoberfläche nahezu die gesamte Strahlerleistung zur Signalgewin- nung genutzt werden.The component enables the implantation of active and / or passive electronic, optoelectronic, micromechanical and / or actuator components, which consist of solid materials and have semiconductor or microsystem functions. It can be used for conventional contacting techniques such as ultrasound and thermosonic bonding or conductive adhesive. The front connection of the chip can be realized conventionally by Al ultrasonic bonding with a flat bridge height. When an LED is implanted, the arrangement of the LED is expediently such that its surface is a few micrometers below the surface level of the receiver chips. In this way, direct radiation of the emitted light onto the photosensitive surface is avoided. In addition to the direct LED radiation in the area above the overall arrangement, reflection of the metallized trench surface means that almost the entire emitter power can be used to obtain the signal.
Das erfindungsgemäße Herstellungsverfahren besteht darin, daß in dem Siliziumträger durch anisotrope Ätzung eingebrachte abgesenkte Gebiete erzeugt werden und daß die Strukturierung zur Erzeugung der elektrisch leitendenThe manufacturing method according to the invention consists in that lowered regions introduced by anisotropic etching are produced in the silicon carrier and that the structuring for producing the electrically conductive ones
Verbindung zwirnen den abgesenkten Gebieten und den auf der planaren Fläche befindlichen Leitbahnstrukluren durch ein Mehrfach-Metallisierungs- sy stem erfolgt.Connection thread the lowered areas and those on the planar Surface guideway structures are made by a multiple metallization system.
Dabei erfolgt zweckmäßigerweise nach dem Si-Ätzen eine Isolierung der abgesenkten Strukturen durch Oxidation oder durch Abscheiden von Isolatorschichten auf dem Träger, danach eine Metallisierung der abgesenkten Gebiete und des Trägermaterials, als nächstes findet eine Strukturierung der Mehrfach-Metallisierung- schicht innerhalb eines fotolithografischen Strukturierungsprozesses unter Einhaltung bestimmter minimaler Strukturbreiten statt (das Mehrfach- Metallisierungssystem wird vorteilhafterweisc dadurch erzeugt , .daß die obere Metallisierungsschicht als Maskierungsschicht für die nachfolgenden Ätzprozesse verwendet wird), danach werden die zu implantierenden Elemente plaziert und kontaktiert und anschließend erfolgt die elektrische Kontaktierung zwischen Trägerchip und Implantatvorderseite.In this case, after the Si etching, the lowered structures are expediently isolated by oxidation or by depositing insulator layers on the carrier, then the lower regions and the carrier material are metallized, and then the multiple metallization layer is structured within a photolithographic structuring process Adherence to certain minimal structure widths instead (the multiple metallization system is advantageously generated by the fact that the upper metallization layer is used as a masking layer for the subsequent etching processes), then the elements to be implanted are placed and contacted and then electrical contact is made between the carrier chip and the front of the implant.
Dabei ist es möglich, daß die elektrische Kontaktierung des Hybridbauelementes aus Trägerchip und Implantat auf einem Schaltungsträger (z.B. einer Leiterplatte) in Form von Drahtbondung, Flip-chip-Kontaktierung, TAB und ähnlichem vorgenommen wird.It is possible for the hybrid component comprising the carrier chip and implant to be electrically contacted on a circuit carrier (e.g. a printed circuit board) in the form of wire bonding, flip-chip contacting, TAB and the like.
Mit dem erfindungsgemäßen Verfahren können zur Herstellung vonWith the method according to the invention, the production of
Silizium-Bauelementen durch anisotrope Ätzung in dem Silizium abgesenkte Gebiete erzeugt werden, die elektrisch vom Substratmaterial isoliert sind und eine Metallisierungsschicht zur Kontaktierung aufweisen. Damit wird gleichzeitig ein elektrischer Kontakt zwischen der Rückseite des implantierten Bauelementes und der Vorderseite desSilicon components are produced by anisotropic etching in the silicon-lowered regions, which are electrically insulated from the substrate material and have a metallization layer for contacting. This is at the same time an electrical contact between the back of the implanted component and the front of the
Trägermaterials erzeugt. Das erfindungsgemäße Verfahren ermöglicht es, eine elektrisch leitende Verbindung zwischen dem abgesenkten Gebiet und der Oberfläche des Trägers herzustellen, an der sich die Schaltung befindet bzw. weiter innerhalb eines fotolithografischen Struklurierungsprozesses realisiert wird. Damit werden die Voraussetzungen zur gleichzeitigen Realisierung eines elektrischen Kontaktes zwischen Rückseite des implantierten Bauelementes und der Vorderseite des Trägermaterials geschaffen.Carrier material generated. The method according to the invention makes it possible to establish an electrically conductive connection between the lowered region and the surface of the carrier on which the circuit is located or is further implemented within a photolithographic structuring process. This creates the conditions for the simultaneous realization of an electrical contact between the back of the implanted component and the front of the carrier material.
Die Erfindung wird nachfolgend an einem Ausführungsbeispiel näher erläutert. In der zugehörigen Zeichnung zeigen:The invention is explained in more detail below using an exemplary embodiment. In the accompanying drawing:
Figur 1: ein hybrides Bauelement herkömmlicher Ausführung inFigure 1: a hybrid component of conventional design in
Chip On Chip - Anordnung undChip on chip arrangement and
Figur 2: eine Schnittdarstellung eines erfindungsgemäß hergestellten Bauelementes.Figure 2 is a sectional view of a component manufactured according to the invention.
Figur 1 zeigt ein hybrides Bauelement in Chip On Chip - Ausführung. Bei der Anordnung fotoempfindlicher Schichten auf dem Chip führt in diesem Fall die Direktbestrahlung der fotoempfindlichen Schicht mit störendem Streulicht zu Fehlern bei der fotoelektrischen Auswertung.FIG. 1 shows a hybrid component in chip on chip design. When photosensitive layers are arranged on the chip, the direct irradiation of the photosensitive layer with disturbing scattered light leads to errors in the photoelectric evaluation.
Das in Figur 2 dargestellte erfindungsgemäße hybride Bauelement mitThe hybrid component according to the invention shown in FIG. 2 with
Chip On Chip - Anordnung weist einen planaren Aufbau von Silizium- Träger 1 und implantierten Chips beliebigen Substratmaterials auf. Mit dieser Anordnung wird eine elektrische Kontaktierung der Rückseite der implantierten Bauelemente realisiert. Die Herstellung des Bauelementes ist mit den in der Mikroelektronik und der Mikrosystemtechnik gebräuchlichen Verfahren möglich. In dem hier erläuterten Fall kommen speziell angepaßte Verfahrensschritte zur Anwendung. Im dargestellten Beispiel wird als Träger ein optisches PIN- Diodenarray mit acht um die zu implantierende LED 2 gruppierten Diodenfeldern 3 verwendet. Die Montage des implantierten Bauelementes erfolgt durch Mikrodispensen von Leitkleber mit eng tolerierter Mengendosierung.Chip-on-chip arrangement has a planar structure of silicon carrier 1 and implanted chips of any substrate material. With this arrangement there is electrical contacting of the back of the implanted components. The component can be produced using the methods customary in microelectronics and microsystem technology. In the case explained here, specially adapted method steps are used. In the example shown, an optical PIN diode array with eight diode arrays 3 grouped around the LED 2 to be implanted is used as the carrier. The implanted component is assembled by microdispensing conductive adhesive with a tightly tolerated amount.
Bei der Herstellung der Silizium-Träger 1 kommen speziell entwickelteIn the manufacture of the silicon carrier 1 come specially developed
Verfahrensschritte für die Realisierung von abgesenkten Gebieten im Träger durch entsprechende Ätzverfahren zur Anwendung. Anschließend erfolgt eine Abscheidung oder Oxidation von Schichten zur Isolation der abgesenkten Strukturen auf den Träger. Danach ist eine Metallisierung der abgesenkten Gebiete und des Trägermaterials vorgesehen. Im folgenden wird die elektrisch leitende Verbindung zwischen abgesenktem Gebiet und den Strukturen auf der planaren Oberfläche des Trägermaterials innerhalb eines fotolithografischen Strukturierungs- prozesses unter Einhaltung bestimmter minimaler Strukturbreiten hergestellt. Mit diesen Verfahrensschritlen wird gleichzeitig ein elektrischer Kontakt zwischen der Landefläche des implantierten Bauelementes und der Vorderseite des Trägermaterials erzielt. In dem Strukturierungsprozeß wird die elektrisch leitende Verbindung zwischen den abgesenkten Gebieten und den auf der planaren Fl.äche befindlichen Leitbahnstrukturen durch ein Dreifach-Metallisierungssy- stem realisiert. Dabei dient die obere Metallisierungsschicht als Maskie- rungsschicht für die nachfolgenden Ätzprozesse. Es wird bei sicherer elektrischer Kontaktierung der abgesenkten Gebiete auf dem Trägerchip eine simultane Strukturierung der Verdrahtungsebene der Trägerchips ohne wesentliche Beeinflussung der Entwurfsregeln erreicht. Die nachgewiesene Auflösungsgrenze liegt bei 10 μm Strukturbreite bis an die Kante des abgesenkten Gebietes.Process steps for the realization of lowered areas in the carrier by appropriate etching processes for use. Subsequently, layers are deposited or oxidized to isolate the lowered structures on the carrier. Afterwards, a metallization of the lowered areas and of the carrier material is provided. In the following, the electrically conductive connection between the lowered area and the structures on the planar surface of the carrier material is produced within a photolithographic structuring process while observing certain minimal structure widths. With these process steps, electrical contact is simultaneously achieved between the landing surface of the implanted component and the front of the carrier material. In the structuring process, the electrically conductive connection between the lowered areas and the interconnect structures located on the planar surface is realized by a triple metallization system. The upper metallization layer serves as a masking layer for the subsequent etching processes. With reliable electrical contacting of the lowered areas on the carrier chip, a simultaneous structuring of the wiring level of the carrier chips is achieved without significantly influencing the design rules. The Proven resolution limit is 10 μm structure width up to the edge of the lowered area.
Im Rahmen der technologischen Teilschrittfolge zur Herstellung dieser Strukturen werden folgende Prozesse an <100> - Si - Wafermaterial durchgeführt.The following processes are carried out on <100> - Si wafer material as part of the technological step sequence for producing these structures.
Zur Herstellung der abzusenkenden Gebiete wird ein Trägersubstrat mittels einer Passivierungschicht aus Siliziumnitrid beschichtet. In einem getrennten fotolithografischen Schritt werden die abzusenkenden Gebiete strukturiert.To produce the areas to be lowered, a carrier substrate is coated using a passivation layer made of silicon nitride. The areas to be lowered are structured in a separate photolithographic step.
Dem schließt sich ein RIE-Ätzen von Si-Nitrid und ein Lackentfernen an.This is followed by RIE etching of Si nitride and paint removal.
Nach dem naßchemischen Ätzen des Feldoxides (thcrmi-sches Tauchätzen) erfolgt die Tiefenätzung ins Silizium und das Rückätzen der Oxidkanten. Anschließend erfolgt eine thermische Oxidation und dasAfter the chemical etching of the field oxide (thermal immersion etching), the deep etching into the silicon and the etching back of the oxide edges take place. This is followed by thermal oxidation and that
Entfernen des Nitrids mittels heißer Phosphorsäure. Danach wird das Material mit Schwefelsäure gereinigt. Dem folgt ein Überätzen vor der Metallisierung und anschließend eine Abscheidung des Dreifach-Metal- lisierungssystems mit der Schichtfolge AI - TiN - AI. In dem sich anschließenden Komplex zum Beschichten der Grabenkanten wird mit dem Aufbringen und Tempern von Flüssighaftvermittler begonnen. Anschließend werden die abgesenkten Gebiete mit einem modifizierten Positivlack aufgefüllt (Dispensen, Siebdruck o.a.) und getrocknet. Dem folgt das Aufbringen einer Positivlackschicht durch spin-coating einschließlich Trocknen, Belichten, Entwickeln und Härten der Lackmaske zur Erzeugung der Metallstrukturen. Nach dieser Schrittfolge wird die obere AI-Schicht naßchemisch geätzt und der Lack entfernt. Dem folgt ein RIE-Ätzen der TiN-Schicht und das naßchemi-sche Ätzen der unteren AI-Schicht, die nachfolgend durch H2-Tempern beh.andelt wird. Die elektrische Kontaktierung der Rückseile der implantierten Bauelemente auf die Landefläche im abgesenkten Gebiet wird durch Leitkle- bung auf der nichtoxidierenden TiN- Metallisierungsschicht des Silizium-Trägers erreicht. Erzielbare Toleranzen in der Ablagegenauig- keit betragen in Abhängigkeit vom Equipment ca. 10 μm in x- und y-Richtung und ca. 5 μm in z-Richtung.Remove the nitride using hot phosphoric acid. The material is then cleaned with sulfuric acid. This is followed by overetching before the metallization and then a deposition of the triple metallization system with the layer sequence AI - TiN - AI. In the subsequent complex for coating the trench edges, the application and tempering of liquid adhesion promoters is started. The lowered areas are then filled with a modified positive varnish (dispensing, screen printing or the like) and dried. This is followed by the application of a positive lacquer layer by spin coating, including drying, exposure, development and hardening of the lacquer mask to produce the metal structures. After this sequence of steps, the upper Al layer is etched wet-chemically and the lacquer is removed. This is followed by an RIE etching of the TiN layer and the wet chemical etching of the lower Al layer, which is subsequently treated by H 2 tempering. The electrical contacting of the back ropes of the implanted components on the landing area in the lowered area is achieved by conductive adhesive on the non-oxidizing TiN metallization layer of the silicon carrier. Achievable tolerances in the placement accuracy are, depending on the equipment, approx. 10 μm in the x and y direction and approx. 5 μm in the z direction.
Der Silizium-träger 1 ermöglicht die Implantation von aktiven und/oder pa-ssiven elektronischen, optoelektronischen, mikromechanischen und/oder aktori-schen Bauelementen, die aus Festkörpermaterialen bestehen und halbleiter- und mikrosystem technische Funktionen ausüben. Nach dem Härteprozeß wird die elektrische Kontaktierung von Trägerchip und Implantat durch Drahtbonden durchgeführt.The silicon carrier 1 enables the implantation of active and / or passive electronic, optoelectronic, micromechanical and / or actuator components, which consist of solid materials and perform semiconductor and microsystem technical functions. After the hardening process, the electrical contacting of the carrier chip and implant is carried out by wire bonding.
Die obenliegende TiN-Schicht bildet eine nichtoxidierende Metallober- fläche und ist damit für konventionelle Kontaktierungstechniken, wieThe TiN layer on top forms a non-oxidizing metal surface and is therefore suitable for conventional contacting techniques such as
Ultraschall- und Thermosonikbondung oder Leitklebung verwendbar. Der Vorderseitenanschluß der LED 2 wird konventionell durch Al-UI- traschall-Bondung mit flacher Brückenhöhe realisiert. Die Anordnung der LED 2 erfolgt so, daß die Oberkante wenige Mikrometer unter der Ebene der Empfängerchips liegt. Auf diese Weise wird eine Direkteinstrahlung des abgestrahlten Lichts auf die fotoempfindliche Oberfl∑tche vermieden. Neben der direkten LED-Abstrahlung in das über der Gesamtanordnung liegende Gebiel kann durch Reflexion von der metallisierten Grabenoberfläche nahezu die gesamte Strahlerleistung zur Signalgewinnung genutzt werden. Ultrasonic and thermosonic bonding or conductive adhesive can be used. The front connection of LED 2 is realized conventionally by Al-UI-ultrasound bonding with a flat bridge height. The arrangement of the LED 2 is such that the upper edge is a few micrometers below the level of the receiver chips. In this way, direct radiation of the emitted light onto the photosensitive surface is avoided. In addition to the direct LED radiation in the area above the overall arrangement, reflection of the metallized trench surface means that almost the entire emitter power can be used for signal generation.

Claims

P AT E N T A N S P R Ü C H E P AT REQUESTS
1. Elektroni.sches Hybrid-Bauelement mit Chip On Chip - Anordnung, bei dem mindestens ein implantiertes Chip auf einem Trägersubstrat angeordnet ist, dadurch gekennzeichnet, daß in dem Trägersubstrat mindestens eine1. Electronic hybrid component with chip-on-chip arrangement, in which at least one implanted chip is arranged on a carrier substrate, characterized in that at least one in the carrier substrate
Kavitat eingearbeitet ist, in der sich eine elektrische Isolationsschicht mit einer darüber angeordneten Metallschichl befindet und daß in der Kavitat ein Chip mit der Metallschicht elektrisch kontaktiert ist.Cavity is incorporated in which there is an electrical insulation layer with a metal layer arranged above it and that in the cavity a chip is electrically contacted with the metal layer.
2. Hybrides Bauelement nach Anspruch 1, dadurch gekennzeichnet, daß die Oberseite des implantierten Chips koplanar zur Substratoberfläche angeordnet ist.2. Hybrid component according to claim 1, characterized in that the top of the implanted chip is arranged coplanar to the substrate surface.
3. Hybrides Bauelement nach Anspruch 1 oder 2, dadurch gekennzeichnet, daß die Metallschicht als Mehrschichtsystem ausgebildet ist, wobei die obere Metallschicht aus einer nichtoxidierenden Schicht besteht.3. Hybrid component according to claim 1 or 2, characterized in that the metal layer is designed as a multilayer system, wherein the upper metal layer consists of a non-oxidizing layer.
4. Hybrides Bauelement nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß das Trägersubstrat als ein optisches PIN-Diodenarray mit um einer implantierten LED (2) gruppierten Diodenfeldern ausgebildet ist. 4. Hybrid component according to one of the preceding claims, characterized in that the carrier substrate is designed as an optical PIN diode array with an implanted LED (2) grouped diode arrays.
5. Hybrides Bauelement nach Anspruch 3, dadurch gekennzeichnet, daß die LED 2 so angeordnet sind, daß ihre Oberkanten wenige Mikrometer unter der Ebene der Diodenfelder liegt.5. Hybrid component according to claim 3, characterized in that the LED 2 are arranged so that their upper edges are a few micrometers below the level of the diode arrays.
6. Verfahren zur Herstellung eines elektronischer Hybrid-Bauelementes mit Chip On Chip - Anordnung, dadurch gekennzeichnet, daß in das Trägersubstrat durch anisotrope Ätzung abgesenkte Gebiete erzeugt werden und die Strukturierung zur Erzeugung der elektrisch leitenden Verbindung zwi.schen den abgesenkten Gebieten und den auf der planaren Räche befindlichen Leitbahnstrukturen durch ein Mehrfach-Metalli- sierungssystem erfolgt,6. A method for producing an electronic hybrid component with chip-on-chip arrangement, characterized in that lowered regions are produced in the carrier substrate by anisotropic etching and the structuring for producing the electrically conductive connection between the lowered regions and the ones on the interconnect structures located in planar areas are made by a multiple metallization system,
7. Verfahren nach Anspruch 6, dadurch gekennzeichnet, daß7. The method according to claim 6, characterized in that
- anschließend an das Ätzen eine Isolierung der abgesenkten Strukturen durch Oxidation oder durch Abscheiden von Isolatorschichten auf den Träger erfolgt,- after the etching, the lowered structures are isolated by oxidation or by depositing insulator layers on the carrier,
- danach eine Metallisierung der abgesenkten Gebiete und des Träger- materials vorgenommen wird und- Then the metallized areas and the carrier material are metallized and
- danach eine Strukturierung der Mehrfach-Metall.schicht innerhalb eines fotolithografischen Prozesses unter Einhaltung bestimmter minimaler Strukturbreiten hergestellt wird,a structure of the multiple metal layer is then produced within a photolithographic process while maintaining certain minimal structure widths,
- danach die zu implantierenden Elemente plaziert und kontaktiert werden und- Then the elements to be implanted are placed and contacted and
- anschließend die elektrische Kontaktierung des Trägerchips mit der Implantatvorderseite erfolgt. - The electrical contact is then made between the carrier chip and the front of the implant.
8. Verfahren nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß die obere strukturierte Metallisierungsschicht als Maskierungsschicht für die nachfolgenden Ätzprozessc dient.8. The method according to any one of the preceding claims, characterized in that the upper structured metallization layer serves as a masking layer for the subsequent etching process.
9. Verfahren nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß zur Bedeckung der Grabenkanten der abgesenkten Gebiete ein Beschichtungsverfahren angewendet wird, bei dem ein Auffüllen der abgesenkten Grabengebiete mit einem modifizierten Positivlack durch Dispensen oder Siebdrucken und Trocknen des .Lackes und danach ein9. The method according to any one of the preceding claims, characterized in that a coating method is used to cover the trench edges of the lowered areas, in which a filling of the lowered trench areas with a modified positive varnish by dispensing or screen printing and drying the .Lackes and then a
Aufbringen eines weiteren PositvIackes durch spin-coating, Sprühen oder Vorhanggießen und Trocknen des Lackes erfolgt.Another positive varnish is applied by spin coating, spraying or curtain casting and drying of the varnish.
10. Verfahren nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, daß die elektrische Kontaktierung der Rückseite der implantierten Bauelemente durch Leitklebung auf einer nichtoxidierenden TiN-Metallisie- rungsschicht des Silizium-Trägers erfolgt. 10. The method according to any one of the preceding claims, characterized in that the electrical contacting of the back of the implanted components is carried out by conductive adhesive on a non-oxidizing TiN metallization layer of the silicon carrier.
PCT/DE1997/002812 1996-06-03 1997-12-03 Electronic hybrid component and method for the production thereof WO1999028971A1 (en)

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DE19720300B4 (en) 2006-05-04
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