DE3925604A1 - Contacting housing-less semiconductor circuits or substrate - forms depressions in substrate such that circuit surfaces lie in substrate surface plane - Google Patents

Contacting housing-less semiconductor circuits or substrate - forms depressions in substrate such that circuit surfaces lie in substrate surface plane

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Publication number
DE3925604A1
DE3925604A1 DE3925604A DE3925604A DE3925604A1 DE 3925604 A1 DE3925604 A1 DE 3925604A1 DE 3925604 A DE3925604 A DE 3925604A DE 3925604 A DE3925604 A DE 3925604A DE 3925604 A1 DE3925604 A1 DE 3925604A1
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Germany
Prior art keywords
substrate
semiconductor
circuit
semiconductor circuits
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE3925604A
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German (de)
Inventor
Michael Kaindl
Werner Dipl Ing Piepenburg
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
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Siemens AG
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Application filed by Siemens AG filed Critical Siemens AG
Priority to DE3925604A priority Critical patent/DE3925604A1/en
Publication of DE3925604A1 publication Critical patent/DE3925604A1/en
Ceased legal-status Critical Current

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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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Abstract

The semiconductor circuits (2) are formed on a flat substrate (1) of insulating material, supporting conductive tracks (9). In the substrate are formed depressions such that the semiconductor circuit surfaces lie in the surface plane of the substrate, with the semiconductor circuit firmly secured in the depression. Between the substrate and the semiconductor circuits is formed a gap coated with an insulating layer (7). Then further conductive tracks (8) are applied for contacting the contact faces (3) with the first conductive tracks. Pref. the extra conductive tracks are applied by screen printing. USE/ADVANTAGE - For hybrid circuits or circuit plates, with simple application and no need for a special form of the semiconductor circuits.

Description

Die Erfindung betrifft ein Verfahren gemäß dem Oberbegriff des Patentanspruchs 1 und eine dadurch hergestellte Hybridschal­ tung.The invention relates to a method according to the preamble of Claim 1 and a hybrid scarf produced thereby tung.

Bei Hybridschaltungen erfolgt die Erzeugung der planaren Strukturen, wie Leiterbahnen, Überkreuzungen und Widerständen in der üblichen Dickschicht- oder Dünnfilmtechnik auf Keramik- oder Glassubstraten. Die Strukturen können hierbei ein- oder beidseitig aufgebracht sein. Ebenso sind Durchkontaktierungen möglich.In hybrid circuits, the planar is generated Structures such as conductor tracks, crossovers and resistors in the usual thick-film or thin-film technology on ceramic or glass substrates. The structures can be one or be applied on both sides. Vias are also used possible.

Die Verwendung von ungehäusten Halbleiterschaltungen auf Hy­ bridschaltungen oder Leiterplatten ergibt folgende Vorteile:
eine gute thermische Kopplung zwischen der Halbleiterschaltung und dem Substrat ergibt eine hohe Wärmeableitung;
der Platzbedarf für ungehäuste Halbleiterschaltungen ist we­ sentlich geringer als der für gehäuste;
die fehlende Bezeichnung auf den ungehäusten Halbleiterschal­ tungen ergibt einen erhöhten Nachbauschutz.The use of unhoused semiconductor circuits on hybrid circuits or printed circuit boards gives the following advantages:
good thermal coupling between the semiconductor circuit and the substrate results in high heat dissipation;
the space required for unhoused semiconductor circuits is considerably less than that for packaged ones;
the missing designation on the unhoused semiconductor circuits results in increased protection from replication.

Die gängigsten Verfahren zur Kontaktierung der Halbleiterschal­ tungen mit den Leiterbahnen der Hybridschaltungen bzw. Leiter­ platten sind folgende: Das Chip-and-Wire Verfahren, wobei jede Verbindung einzeln gebondet werden muß, und kritische interme­ tallische Verbindungen, wie die Purpurpest, zwischen dem Gold­ draht und den Anschlußflächen der Halbleiterschaltungen aus Aluminium entstehen können.The most common methods for contacting the semiconductor scarf connections with the conductor tracks of the hybrid circuits or conductors boards are as follows: The chip-and-wire process, each Connection must be bonded individually, and critical interme metallic connections, such as the purple plague, between the gold wire and the pads of the semiconductor circuits Aluminum can arise.

Das Tape-Automated-Bonding Verfahren, bei dem ein spezieller Aufbau von Höckern, sogenannten Bumps, auf der Halbleiterschal­ tung erforderlich ist, und chipindividuelle, geätzte Leiter­ bahnspinnen erforderlich sind. The tape automated bonding process, in which a special Build-up of bumps on the semiconductor scarf device is required, and chip-specific, etched conductors web spiders are required.  

Das Flip-Chip-Montage-Verfahren, bei dem ebenfalls Bumps auf dem Halbleiter erforderlich sind und Verbindungsstellen unter dem Chip liegen, so daß keine vollständige optische Kontrolle möglich ist.The flip-chip assembly process, which also bumps on the semiconductor are required and joints below the chip, so that no complete optical control is possible.

Das Beam-Lead-Bonding-Verfahren, bei dem spezielle Bändchen, die sogenannten Beam-Leads, auf der Halbleiterschaltung erfor­ derlich sind.The beam lead bonding process, in which special ribbons, the so-called beam leads, on the semiconductor circuit are such.

Der Erfindung liegt die Aufgabe zugrunde, ein Verfahren der eingangs genannten Art anzugeben, das einfach durchführbar und keine spezielle Ausführungsform der Halbleiterschaltung erfor­ dert.The invention has for its object a method of Specify the type mentioned that is easy to carry out and no special embodiment of the semiconductor circuit is required different.

Diese Aufgabe wird erfindungsgemäß durch die im Patentan­ spruch 1 angegebenen Merkmale gelöst.This object is achieved by the in the patent claim 1 specified features solved.

Ein Vorteil des erfindungsgemäßen Verfahrens besteht darin, daß alle Halbleiterschaltungen auf dem Substrat in einem Arbeits­ gang kontaktiert werden können (Simultankontaktierungsverfah­ ren).An advantage of the method according to the invention is that all semiconductor circuits on the substrate in one work can be contacted (simultaneous contact procedure ren).

Durch das erfindungsgemäße Verfahren wird weiter eine sehr gute thermische Kopplung der Halbleiterschaltung mit dem Trägersub­ strat erreicht. Zusätzliche Wärmesenken sind einfach zu montie­ ren. Der Wärmewiderstand zwischen der Sperrschicht der Halblei­ terschaltung und der Wärmesenke kann sehr gering gehalten wer­ den.The method according to the invention also makes a very good one thermal coupling of the semiconductor circuit to the carrier sub strat reached. Additional heat sinks are easy to install ren. The thermal resistance between the junction of the semi-lead terschaltung and the heat sink can be kept very low who the.

Das erfindungsgemäße Verfahren kann sowohl bei Hybridschaltun­ gen als auch bei Standart-Gehäusen verwendet werden.The method according to the invention can be used both in hybrid circuits conditions as well as standard housings.

Im folgenden wird die Erfindung an eines in der Zeichnung dar­ gestellten Ausführungsbeispieles beschrieben. Dabei zeigen In the following, the invention is illustrated by one in the drawing described embodiment described. Show  

Fig. 1 im Querschnitt ein Substrat mit einem in einer Ver­ tiefung liegenden Halbleiterschaltung, Fig. 1 in cross-section a substrate having an indentation lying in a Ver semiconductor circuit,

Fig. 2 einen Ausschnitt aus Fig. 1, wobei Leiterbahnen aufgebracht sind, FIG. 2 shows a detail from FIG. 1, conductor tracks being applied,

Fig. 3 eine Draufsicht auf das Substrat mit Halbleiterschal­ tung und Leiterbahn, und Fig. 3 is a plan view of the substrate with semiconductor scarf device and conductor track, and

Fig. 4 zusätzlich angebrachte Kühlkörper. Fig. 4 additionally attached heat sink.

In Fig. 1 ist im Querschnitt ein Substrat 1 aus Isoliermate­ rial (es kann sich hierbei auch um eine Leiterplatte handeln) mit einer nicht näher bezeichneten Vertiefung dargestellt, in die eine Halbleiterschaltung 2 (beispielsweise ein IC) einge­ legt ist. Um Kontaktflächen 3 der Halbleiterschaltung 2 unter Verwendung von in Dickschicht- oder Dünnfilmtechnick herge­ stellten Leiterbahnen ankontaktieren zu können, muß die Ober­ fläche der Halbleiterschaltung 2 mit der Oberfläche des Sub­ strats 1 eine Ebene bilden. Diese Vertiefungen im Substrat 1 können beispielsweise mit einem Excimer-Laser hergestellt wer­ den. Durch Verwendung von entsprechenden Blenden im Laserstrahl ist bei Einsatz mehrerer Halbleiterschaltungen 2 die Herstel­ lung aller Vertiefungen gleichzeitig möglich. Sollten es die Toleranzen der Halbleiterschaltung 2 erfordern, so können die Abmessungen der Vertiefungen über eine variable Blende den jeweiligen Abmessungen der Halbleiterschaltung 2 angepaßt werden.In Fig. 1, a substrate 1 made of insulating material (it can also be a printed circuit board) is shown in cross section with a recess, not specified, into which a semiconductor circuit 2 (for example an IC) is inserted. In order to be able to contact contact surfaces 3 of the semiconductor circuit 2 using conductor tracks made in thick-film or thin-film technology, the upper surface of the semiconductor circuit 2 must form a plane with the surface of the substrate 1 . These depressions in the substrate 1 can be produced, for example, with an excimer laser. By using appropriate diaphragms in the laser beam, the manufacture of all depressions is possible simultaneously when using several semiconductor circuits 2 . If the tolerances of the semiconductor circuit 2 require it, the dimensions of the depressions can be adapted to the respective dimensions of the semiconductor circuit 2 via a variable aperture.

Die genauen Abmessungen der Halbleiterschaltung 2 können mit einem optischen System vermessen werden, wobei dieses System zweckmäßigerweise mit dem Excimer-Laser rechnergekoppelt ist.The exact dimensions of the semiconductor circuit 2 can be measured using an optical system, this system advantageously being computer-coupled to the excimer laser.

Die Tiefe der Vertiefung ist beispielsweise über die Abtragrate oder andere Meßeinrichtungen, z.B. optisch oder mit Ultra­ schall, zu ermitteln. Nach dem Erreichen der erforderlichen Tiefe gibt die hierzu verwendete Meßeinrichtung ein Signal zum Abschalten des Lasers. Eine andere Möglichkeit zur Herstellung der Vertiefung besteht darin, diese in sogenannter grüner Keramik zu erzeugen. The depth of the depression is above the removal rate, for example or other measuring devices, e.g. optically or with ultra sound, to determine. After reaching the required Depth, the measuring device used for this gives a signal to Switch off the laser. Another way of making the deepening is this in so-called green To produce ceramics.  

Die Halbleiterschaltung 2 wird in der Vertiefung mit einem Kle­ ber 4 fixiert. Als Kleber 4 kann ein Leit- oder Isolierkleber (Epoxy-Die-Bonding) verwendet werden. Anschließend erfolgt die Aushärtung des Klebers 4.The semiconductor circuit 2 is fixed in the recess with an adhesive 4 . A conductive or insulating adhesive (epoxy die bonding) can be used as the adhesive 4 . The adhesive 4 is then cured.

Eine eventuell erforderliche elektrische Kontaktierung der Rückseite der Halbleiterschaltung 2 kann über eine oder mehrere Durchkontaktierungen 5 im verbleibenden Substrat 1 unter der Halbleiterschaltung 2 zur Rückseite des Substrats 1 erfolgen.Any necessary electrical contacting of the rear side of the semiconductor circuit 2 can take place via one or more plated-through holes 5 in the remaining substrate 1 under the semiconductor circuit 2 to the rear side of the substrate 1 .

Anhand von Fig. 2 werden die nächsten Arbeitsschritte erläu­ tert.Referring to Fig. 2, the next steps are tert erläu.

Ein zwischen Halbleiterschaltung 2 und Substrat 1 vorhandener Spalt 6 wird mit einer Isolierschicht 7 abgedeckt. Diese Iso­ lierschicht 7 kann durch das Aufbringen einer Isolierpaste mit­ tels Siebdruck erzeugt werden. Um hohe Genauigkeiten zu errei­ chen, ist auch der Einsatz von geätzten Metallmasken anstelle der gebräuchlichen Siebe möglich. Die Aushärtung der Isolier­ paste oder auch eines Isolierklebers muß unterhalb der max. zulässigen Sperrschichttemperatur der eingesetzten Halbleiter­ schaltungen 2 erfolgen. Um sogenannte Pinholes zu vermeiden, kann es erforderlich werden, diesen Druck zweimal auszuführen.A gap 6 present between the semiconductor circuit 2 and the substrate 1 is covered with an insulating layer 7 . This insulating layer 7 can be produced by applying an insulating paste by means of screen printing. To achieve high accuracy, it is also possible to use etched metal masks instead of the usual screens. The curing of the insulating paste or an insulating adhesive must be below the max. permissible junction temperature of the semiconductor circuits 2 used . In order to avoid pinholes, it may be necessary to perform this print twice.

Das Aufbringen der Isolierschicht 7 ist nötig, um Kurzschlüsse zwischen der nicht passivierten Kante der Halbleiterschaltung 2 und einer im nächsten Arbeitsgang aufgebrachten Ankontaktie­ rungsleiterbahn 8 zu vermeiden.The application of the insulating layer 7 is necessary in order to avoid short circuits between the non-passivated edge of the semiconductor circuit 2 and a contact conductor 8 applied in the next operation.

Die eigentliche Verbindung der Kontaktflächen 3 mit einer auf dem Substrat 1 aufgebrachten Schaltungsleiterbahn 9 erfolgt mit der Ankontaktierungsleiterbahn 8. Diese Leiterbahnen 8 wer­ den mit einer Leitpaste oder einem Leitkleber in Siebdruck­ technik ausgeführt. Bei hohen Anforderungen an die Genauigkeit bzw. bei Leiterbahnbreiten < 100 µ können geätzte Metallmasken anstelle der Siebe eingesetzt werden. Mit einem einzigen Sieb­ druckvorgang sind somit alle Verbindungen zwischen den Schal­ tungsleiterbahnen 9 auf dem Substrat 1 und den Kontaktflächen 3 der Halbleiterschaltung 2 herstellbar. Die Aushärtung muß wie­ derum unterhalb max. zulässigen der Sperrschichttemperatur erfolgen. Durch die übliche Passivierung der Oberfläche der Halbleiterschaltung 2 mit Siliziumnitrid oder Siliziumoxyd treten keine Kurzschlüsse auf. Anstelles eines Druckverfahrens kann auch ein Dünnfilmprozeß angewendet werden.The actual connection of the contact areas 3 to a circuit conductor track 9 applied to the substrate 1 takes place with the contacting conductor track 8 . These conductor tracks 8 who executed the with a conductive paste or a conductive adhesive in screen printing technology. If high demands are placed on the accuracy or if the track width is <100 µ, etched metal masks can be used instead of the sieves. With a single screen printing process, all connections between the circuit tracks 9 on the substrate 1 and the contact surfaces 3 of the semiconductor circuit 2 can be produced. The curing must again below max. permissible junction temperature. Due to the usual passivation of the surface of the semiconductor circuit 2 with silicon nitride or silicon oxide, no short circuits occur. Instead of a printing process, a thin film process can also be used.

Nach dem Ankontaktieren der Halbleiterschaltungen 2 wird im allgemeinen eine elektrische Prüfung durchgeführt. Werden hier­ bei fehlerhafte Halbleiterschaltungen 2 erkannt, so können diese platzselektiv mit einem Excimer-Laser abgetragen werden. Eine neue Halbleiterschaltung 2 wird anschließend durch platz­ selektives Ausführen der nötigen Verfahrensschritte fixiert und kontaktiert.After the semiconductor circuits 2 have been contacted, an electrical test is generally carried out. If defective semiconductor circuits 2 are detected here, they can be removed in a space-selective manner using an excimer laser. A new semiconductor circuit 2 is then fixed and contacted by space-selective execution of the necessary method steps.

Die Leiterbahnen 8, 9 einschließlich der Halbleiterschaltungen 2 können mittels Abdecklack vor Umwelteinflüssen geschützt wer­ den. Dieser Lack kann auch mittels Siebdruck aufgebracht wer­ den, da die Oberfläche der Schaltung plan ist. Die Hybridier­ plätze von eventuell noch erforderlichen Bauelementen sind da­ bei freizuhalten. Eine andere Möglichkeit der Passivierung be­ steht im Aufsputtern (Kathodenzerstäubung) von z.B. Silizium­ oxyd. Hierbei sind dann anschließend die Hybridierplätze bei­ spielsweise durch Ätzen oder mit der Abhebetechnik wieder frei­ zulegen.The conductor tracks 8 , 9 including the semiconductor circuits 2 can be protected from environmental influences by means of a resist. This lacquer can also be applied by screen printing because the surface of the circuit is flat. The hybridization places of any components that are still required are to be kept free. Another possibility of passivation is sputtering (sputtering) of, for example, silicon oxide. In this case, the hybridization sites are then cleared again, for example by etching or using the lifting technology.

Werden für die Funktion der Hybridschaltung zusätzliche ge­ häuste Bauelemente benötigt (integrierte Schaltkreise, Kon­ densatoren, Dioden, Transistoren u.a.), so können diese Bau­ teile beispielsweise mit elektrisch leitendem Kleber montiert werden. Der Kleber kann entweder mit üblichen Verfahren (bei­ spielsweise mit einem numerisch gesteuerten Dosiergerät) oder mittels Siebdrucktechnik aufgebracht werden. Letzteres ist nur dadurch möglich, daß mit dem erfindungsgemäßen Verfahren eine plane Oberfläche der Hybridschaltung erreicht wird. Are additional ge for the function of the hybrid circuit housed components required (integrated circuits, Kon capacitors, diodes, transistors, etc.), so this construction parts assembled with electrically conductive adhesive, for example will. The adhesive can either be applied using standard methods (at for example with a numerically controlled dosing device) or applied using screen printing technology. The latter is only possible that with the method according to the invention flat surface of the hybrid circuit is reached.  

In Fig. 3 ist in Draufsicht die in die Vertiefung eingebettete Halbleiterschaltung 2 zu sehen. Weiter sind die die Kontakt­ flächen 3 mit den Schaltungsleiterbahnen 9 verbindenden An­ kontaktierungsleiterbahnen 8 dargestellt, die über die Isolier­ schicht 7 gelegt sind.The semiconductor circuit 2 embedded in the depression can be seen in plan view in FIG. 3. Next, the contact surfaces 3 with the circuit traces 9 connecting to contacting traces 8 are shown, which are placed over the insulating layer 7 .

Werden zur besseren Wärmeableitung noch zusätzliche in Fig. 4 dargestellte Kühlelemente 10,11 benötigt, so ist die Montage dieser Elemente 10, 11 auf der Vorder- oder Rückseite des Substrates 1 möglich. Das Kühlelement 11 auf der Vorderseite des Substrates 1 muß mit einem gut wärmeleitenden Isolations­ kleber 12 aufgebracht werden. Um einen definierten Abstand zwischen Kühlelement 11 und der Substratoberfläche zu erhalten, ist ein gefüllter Klebstoff, beispielsweise mit Keramikgranu­ lat, zu bevorzugen. Da sich die temperaturerzeugende Sperr­ schicht der Halbleiterschaltung 2 an der Oberfläche befindet, kann mit einem sehr geringen Wärmewiderstand zwischen Sperr­ schicht und diesem Kühlelement 11 gerechnet werden.Be additional to improve heat dissipation for cooling elements 10,11 shown in Fig. 4 is required, the assembly of these elements 10, 11 is possible on the front or back of the substrate 1. The cooling element 11 on the front of the substrate 1 must be applied with a good heat-conducting insulation adhesive 12 . In order to maintain a defined distance between the cooling element 11 and the substrate surface, a filled adhesive, for example with ceramic granules, is preferred. Since the temperature-generating barrier layer of the semiconductor circuit 2 is on the surface, a very low thermal resistance between the barrier layer and this cooling element 11 can be expected.

Die Kühlelemente 10, 11 halten zusätzlich schädliche Umwelt­ einflüsse von der Hybridschaltung ab.The cooling elements 10 , 11 additionally prevent harmful environmental influences from the hybrid circuit.

Claims (5)

1. Verfahren zur elektrischen Kontaktierung von ungehäusten Halbleiterschaltungen (2) auf einem plattenförmigen Substrat (1) aus Isoliermaterial mit darauf aufgebrachten Leiterbahnen (9), dadurch gekennzeichnet, daß
Vertiefungen in dem Substrat (1) erzeugt werden, so daß die Oberflächen der Halbleiterschaltungen (2) in der Oberflächen­ ebene des Substrats (1) liegen,
die Halbleiterschaltungen (2) in den Vertiefungen fixiert werden,
auf einen Spalt (6) zwischen dem Substrat (1) und den Halblei­ terschaltungen (2) jeweils eine Isolierschicht (7) aufgebracht wird, und
weitere Leiterbahnen (8) zur Kontaktierung der Kontaktflächen (3) mit den Leiterbahnen (9) aufgebracht werden.1. A method for electrical contacting of unhoused semiconductor circuits ( 2 ) on a plate-shaped substrate ( 1 ) made of insulating material with conductor tracks ( 9 ) applied thereto, characterized in that
Depressions are produced in the substrate ( 1 ) so that the surfaces of the semiconductor circuits ( 2 ) lie in the surface plane of the substrate ( 1 ),
the semiconductor circuits ( 2 ) are fixed in the depressions,
an insulating layer ( 7 ) is applied to a gap ( 6 ) between the substrate ( 1 ) and the semiconductor circuits ( 2 ), and
further conductor tracks ( 8 ) for contacting the contact surfaces ( 3 ) with the conductor tracks ( 9 ) are applied. 2. Verfahren nach Anspruch 1 dadurch gekennzeichnet, daß die weiteren Leiterbahnen (8) in Siebdrucktechnik aufgebracht werden.2. The method according to claim 1, characterized in that the further conductor tracks ( 8 ) are applied using screen printing technology. 3. Verfahren nach Anspruch 1 dadurch gekennzeichnet, daß die weiteren Leiterbahnern (8) mit einem Dünnfilmprozeß aufge­ bracht werden.3. The method according to claim 1, characterized in that the further conductor tracks ( 8 ) are brought up with a thin film process. 4. Hybridschaltung gekennzeichnet durch
mindestens eine in eine Vertiefung eines Substrates (1) eingebettete Halbleiterschaltung (2),
durch eine einen Spalt (6) zwischen Halbleiterschaltung (2) und Substrat (1) abdeckende Isolierschicht (7), und
durch Leiterbahnen (8), die Kontaktflächen (3) der Halbleiter­ schaltung (2) über die Isolierschicht (7) hinweg mit auf dem Substrat (1) befindlichen Schaltungsleiterbahnen (9) zu kon­ taktieren. 4. Hybrid circuit characterized by
at least one semiconductor circuit ( 2 ) embedded in a recess of a substrate ( 1 ),
by an insulating layer ( 7 ) covering a gap ( 6 ) between the semiconductor circuit ( 2 ) and the substrate ( 1 ), and
by conductor tracks ( 8 ) to contact the contact surfaces ( 3 ) of the semiconductor circuit ( 2 ) over the insulating layer ( 7 ) with circuit conductor tracks ( 9 ) located on the substrate ( 1 ). 5. Hybridschaltung nach Anspruch 4, gekennzeichnet durch mindestens ein auf der Hybridschaltung aufgebrachtes Kühlele­ ment (10, 11) .5. Hybrid circuit according to claim 4, characterized by at least one applied to the hybrid circuit cooling element ( 10 , 11 ).
DE3925604A 1989-08-02 1989-08-02 Contacting housing-less semiconductor circuits or substrate - forms depressions in substrate such that circuit surfaces lie in substrate surface plane Ceased DE3925604A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE3925604A DE3925604A1 (en) 1989-08-02 1989-08-02 Contacting housing-less semiconductor circuits or substrate - forms depressions in substrate such that circuit surfaces lie in substrate surface plane

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0516170A2 (en) * 1991-05-28 1992-12-02 Oki Electric Industry Co., Ltd. Semiconductor chip mounted circuit board assembly and method for manufacturing the same
DE19520676A1 (en) * 1995-06-07 1996-12-12 Deutsche Telekom Ag Hybrid circuit and method of making the same
DE19720300A1 (en) * 1996-06-03 1997-12-04 Cis Inst Fuer Mikrosensorik E Chip-on-chip hybrid electronic component
EP0923130A1 (en) * 1997-12-12 1999-06-16 ELA MEDICAL (Société anonyme) Electronic circuit, in particular for implantable active medical device, like a heart stimulator or defibrillator, and its manufacturing method
WO2003081669A1 (en) * 2002-03-26 2003-10-02 Thales Integrated circuit module and method for making same

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
IBM TDB, 1983, Vol. 26, Nr. 6, S. 2730-2731 *
JP 61-2 14 444 A, in: Pat. Abstr. of JP, E-480 *
JP 61-2 92 929 A, in: Pat. Abstr. of JP, E-509 *
JP 63-1 47 339 A, in: Pat. Abstr. of JP, E-675 *
Productions, 5-1989, S. 14-16 *

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0516170A2 (en) * 1991-05-28 1992-12-02 Oki Electric Industry Co., Ltd. Semiconductor chip mounted circuit board assembly and method for manufacturing the same
EP0516170A3 (en) * 1991-05-28 1993-04-14 Oki Electric Industry Co., Ltd. Semiconductor chip mounted circuit board assembly and method for manufacturing the same
DE19520676A1 (en) * 1995-06-07 1996-12-12 Deutsche Telekom Ag Hybrid circuit and method of making the same
DE19720300A1 (en) * 1996-06-03 1997-12-04 Cis Inst Fuer Mikrosensorik E Chip-on-chip hybrid electronic component
DE19720300B4 (en) * 1996-06-03 2006-05-04 CiS Institut für Mikrosensorik gGmbH Hybrid electronic component and method for its production
EP0923130A1 (en) * 1997-12-12 1999-06-16 ELA MEDICAL (Société anonyme) Electronic circuit, in particular for implantable active medical device, like a heart stimulator or defibrillator, and its manufacturing method
FR2772516A1 (en) * 1997-12-12 1999-06-18 Ela Medical Sa ELECTRONIC CIRCUIT, IN PARTICULAR FOR AN ACTIVE IMPLANTABLE MEDICAL DEVICE SUCH AS A CARDIAC STIMULATOR OR DEFIBRILLATOR, AND ITS MANUFACTURING METHOD
US6256206B1 (en) 1997-12-12 2001-07-03 Ela Medical S.A. Electronic circuit for an active implantable medical device and method of manufacture
WO2003081669A1 (en) * 2002-03-26 2003-10-02 Thales Integrated circuit module and method for making same
FR2837982A1 (en) * 2002-03-26 2003-10-03 Thales Sa INTEGRATED CIRCUIT MODULE AND MANUFACTURING METHOD THEREOF

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