WO2004112136A1

WO2004112136A1 - Electronic device

Info

Publication number: WO2004112136A1
Application number: PCT/IB2004/050864
Authority: WO
Inventors: Ronald Dekker; Godefridus A. M. Hurkx; Andreas B. M. Jansman; Antonius L. A. M. Kemmeren; Jozef R. M. Bergervoet; Gerben W. De Jong; Aalbert Stek
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2003-06-12
Filing date: 2004-06-08
Publication date: 2004-12-23

Abstract

The electronic device of the invention comprises a substrate with semiconductor elements, in which substrate one or more cavities are provided. Further active devices are provided in the cavities and coupled to the semiconductor elements through one common multilayer interconnect structure.

Description

Electronic device

The invention relates to an electronic device comprising a first semiconductor device and a second semiconductor device each having a substrate of a semiconductor material in which semiconductor elements are defined, which first and second semiconductor devices have a common package.

Such an electronic device is generally known as a multi-chip module (MCM). The common package includes both a single leadframe or carrier with interconnects and a single encapsulation of insulating material. Both semiconductor devices are provided on the carrier and electrical connections are provided with bumps or wire bonding. Multi-chip modules have become important since modern electronics require functionalities that can be provided on a single chip only at high costs, if at all. The multi-chip module provides such functionality as a whole, and in fact, for a customer it does not matter that the package comprises two semiconductor devices instead of one if it provides the desired functionality. Thereto, the carrier may comprise direct interconnects between the first and the second semiconductor devices.

It is, however, a drawback of current multi-chip modules, that their suitability to higher frequencies turns out to be limited. At such high frequencies, for instance those higher than 2 GHz and particularly those higher than 10 GHz, each interconnect acts as an inductor. The inductance of bond wires and bumps forms a serious obstacle for the high frequency signal resulting in attenuation and signal distortion. Even worse is the effect of the bond pads to which the bond wires and/or bumps are connected. These serve as capacitances to ground and provide other discontinuities.

It is therefore an object of the invention to provide an electronic device of the kind mentioned in the opening paragraph, wherein attenuation and signal distortion can be reduced considerably.

This object is achieved in an electronic device comprising: - a substrate of a semiconductor material having a first and a second opposite side, and on its first side provided with a plurality of semiconductor elements which are mutually interconnected so as to form an integrated circuit;

- an active device, that has a coupling surface provided with connection pads and is present in a cavity in the substrate, the cavity having an aperture on the first side of the substrate, at which aperture the coupling surface is present, and

- a multilayer interconnect structure being provided on the first side of the substrate extending over the first cavity and the plurality of semiconductor elements, and interconnecting according to a desired circuit the semiconductor elements and the active device.

In the device according to the invention, the first semiconductor device is present in a cavity of the second semiconductor device, and the devices are provided with a common interconnect structure. In fact, the interconnect structure of the second semiconductor device is completely part of that of the common interconnect structure. Herewith the signal distortion and attenuation are substantially reduced, as the parasitic inductance and capacitance responsible are substantially reduced. First of all, wirebonds are not needed due to the common interconnect structure. Secondly, the connection between the first and the second device is made on or near to the substrate surface, and not on the surface of a carrier. Since the resolution on the substrate surface is much higher, the resulting parasitic capacitance is less. A third factor contributing to the reduced signal distortion is that transmission lines can be defined in the common interconnect structure without substantial discontinuities. Such discontinuities are usually present in the prior art multi-chip module.

The device of the present invention has a number of advantages. The common interconnect structure reduces the cost of manufacturing, as all interconnects can be provided in a single process. In the multi-chip module, both devices and carrier are provided with interconnects. Moreover, in view of the generally limited number of connections at the carrier, the design of the individual devices is generally more complex. Furthermore, the common interconnect adds functionality in that it allows that the first device - or parts thereof - can be directly incorporated in the circuit of the second device.

An example hereof is the combination of an RF circuit and an oscillator. The RF circuit is for instance a transceiver, a mixer or an optical switch network. In such a network a good source is needed for providing an electrical signal of a desired frequency (bit rate generator). An InP active device is suitable therefor. Subsequently, the signals can be processed in semiconductor elements in another substrate, such as SiGe. Due to the coupling of the interconnect structures at the third of fourth level, these parasitics are reduced considerably. It is furthermore advantageous that the inductor of the oscillator can have a larger surface area than that of the active device. The same applies to the positioning of amplifiers. Here, an optimal linearization can be achieved, and such optimization is not counteracted by substantial parasitics of the interconnects. Also, the semiconductor elements in the substrate can be used for feedback and as control logic for the amplifier provided in another technology, for instance GaAs or GaN.

A further example of the device of the present invention is a device that is able to convert a signal coming from an optical fiber into an electrical signal that is amplified according to need. Therefore, use is made of a photodiode, one or more amplifiers, various circuits. The photodiode may be provided on a semiconductor substrate of InP, the amplifiers may be implemented on a substrate of GaAs and the filters can be implemented on a silicon substrate. If desired, a transmitter IC based on SiGe may be provided as well. In a preferred modification hereof, the photodiode is provided in the substrate of semiconductor material, and the amplifier is the active device which is present in the cavity in the substrate. This combination is suitable for use as an optical receiver for instance for advanced optical storage technologies such as DVD and BluRay .

Good results have been found with a substrate of high-resistive silicon, for instance with a resistivity of more than 1 kΩcm, preferably of more than 3 k kΩcm. Since such photodiodes have a very large depletion region in this lowly doped material, in the order of tens of microns, there is a much larger area in which the so-called fast part (25 GHz.μm) of the photocurrent is generated. If desired, the total width between a first and a second electrode of the photodiode may be depleted. As a consequence hereof, generated electrons and holes experience an electric field over the whole distance between these electrodes. This also causes the junction capacitance to be very low, which is needed to achieve a high noise- limited bandwidth. For a photodiode segment of about 50 μm x 50 μm, a junction capacitance in the order of a few fF is achievable. Lateral pindiodes are used as photodiodes. Within the process with a substrate of high-resistive silicon, these pindiodes show a good performance. It is not problematic that these lateral pindiodes are defined at the surface only, as the penetration of light in silicon is very small. This problem will particularly then be absent, if the wavelength of the incoming light is small (as is for instance the case in BluRay™). If desired, high density capacitors can be integrated in or on the substrate of high-resistive silicon for filtering of power lines. The amplifier is a low-noise amplifier. If this amplifier is integrated with a signal processor, it is highly suitably made in a BICMOS process, such as that on the basis of a SiGe substrate and known per se to the skilled person. In a suitable embodiment, the device is provided with a heatsink that will provide thermal grounding to the amplifier. Additionally, the thin-film interconnect structure that may be free of wirebonds and flip-chip connections offers a low capacitance of the terminals of the low-noise amplifier, resulting in low noise figures for this amplifier.

A third suitable example is the combination of bipolar and CMOS technology. The device of such an embodiment is an alternative to BiCMOS technology. A first advantage in comparison therewith, is that different substrate materials, and also different resolutions can be used for the bipolar and the CMOS part. A second advantage is that both types of the devices can be provided in a technology that is as cheap as desired, whereas the combined BiCMOS results in a comparatively expensive process. The bipolar elements may be provided in the active device, but alternatively in the substrate. Further examples of active devices are memory devices, sensors, micro- electromechanical system (MEMS) switches, capacitors, resonators, bulk and surface acoustic wave filter and ceramic antennas. The advantage of the combination of these elements with the semiconductor elements in the substrate is that, on the one hand, the processing is separated partially, and on the other hand, the semiconductor elements needed as drivers and for the logic, including microprocessors, can be positioned near to the active devices. Examples of memory devices made in different technology from the transistors are magnetic random access memories (MRAM), Schottky devices, and memories on the basis of phase-change materials.

The electronic device of the present invention could be regarded as a special embodiment of a chip in a cavity approach, such as known per se from US4,739,389.

However, there are important differences. First of all, the substrate in the known device does not contain semiconductor elements, which together form an integrated circuit. The substrate is used in that prior art document as a carrier for passive elements. Secondly, the active device is connected to passive elements on the substrate with wirebonds. Therewith, not only is its applicability for high frequencies limited, but also the number of electric connections between the active device and the rest of the circuit. More importantly, due to the common interconnect structure in the device of the invention and the planarity thereof, the electrical connections between the active device and selected parts of the semiconductor elements of the integrated circuit can be very small. The connection of the active device to the common interconnect structure is found on the substrate surface, where the resolution is generally high. Specific epitaxial layers are present just below this surface, which layers are vulnerable to diffusion of charge carriers and to contamination. The problem of diffusion can be counteracted by using adequate design rules. Furthermore, it is preferable for the interconnect structures to be only coupled at the third or higher level. Moreover, the interconnect structures can be mutually electrically insulated at the non-connected levels. The connection pads present in the active device may have any size as needed for the specific interconnect technology used. In principle, the connection pads can be vertical interconnect areas. In a suitable embodiment, the interconnect structure comprises passive elements. Passive elements are needed in a large variety of applications. The interconnect structure allows implementation thereof. At very high frequencies, the passive element may build up from one or more transmission lines. At lower frequencies, it can be an inductor. It is particularly preferred that the interconnect structure comprises a capacitor and an inductor or an equivalent transmission line. An LC-network can be provided with such a combination, which network is desired for a large number of applications.

It is preferred that the device is provided with a means for heat dissipation, such as a heat sink. The miniaturization and increased functionality of the device leads to increased heat dissipation. Such a heat sink may be provided on the second side of the substrate. The heat sink can have a support function at the same time. For this purpose, the substrate is particularly preferred to be thinned before the heatsink is provided. This allows the path for the active elements to the heat sink to be very short. Alternatively, the heat sink can be provided in a leadframe that is attached to the device afterwards. Furthermore, the means for heat dissipation can be active means such as heat pipes. Such means might be assembled to the interconnect structure. A further possibility for the provision of such means is that thermally conductive connections are present on the first side of the substrate, which connections are coupled to heat dissipators, such as heat pipes, fans, ventilators and the like. It is furthermore preferred that the device is provided with a ground plane. In case where a heat sink is present, it could function as a ground plane as well. Alternatively, the ground plane is in the interconnect structure, and coupled to an external ground by a contact in the interconnect structure.

The device may further be processed, packaged and assembled as any conventional semiconductor device. The device may contain more than one active devices. In case where the device is used for high-frequency applications, the device is preferably provided with multiplexers and demultiplexers which enable a transformation between a low-frequency input signal and a high-frequency signal of desired frequency that is used for the signal transmission in the device. This implies that all input signals are low- frequency signals. The input signals are those signals provided from other units than the device within an audio/video transmission apparatus such as a video player, a computer, a mobile phone. The term 'low-frequency signal' is herein understood to be a signal that can be transmitted by bond wires, flex foil connections or whatever conventional coupling means. The only other supply to the device is then the voltage supply. The advantage hereof is that the device will include all relevant high- frequency functions. It can then be used as a plug-and-play module. Moreover, the high- frequency part can be designed as a whole, without having any undesired and uncontrollable distortion of the high-frequency behavior. The integration of all high-frequency functions into the device implies the integration of antenna, matching circuits, and band-pass filters, band switches so as to separate incoming and outgoing signals and/or signals of different frequency bands, power amplifiers and low-noise amplifiers for the specific frequency bands, transmitter and receiver integrated circuits, voltage controlled oscillators, power control and multiplexers and demultiplexers for conversion between low and high frequencies.

It will be understood that it is highly preferable that all these elements are either provided as part of the interconnect structure, or are provided as active elements defined in the substrate or are active devices provided in cavities in the substrate. It is herewith not necessary, that each active device is present in a separate cavity. Such active devices in a single cavity are for example different amplifier stages to be coupled to each other directly The device of the invention can be suitably used for hand-held devices, in which a plurality of frequency bands need to be processed individually. Examples of the frequency bands include GSM, Bluetooth, Wireless LAN, 802.11, UMTS and LDMS. The device may further be used for specific high-frequency applications, such as needed for anticollision radars, which are intended for use in vehicles, and cars in particular. It is preferable that the device of the invention comprises the signal transmission means for at least two frequency bands.

The device of the invention is further suitable for use in consumer and professional applications in which an optical signal needs to be converted into an electrical signal. Such applications are foreseen in respect of the use of optical fibers for communication. A photo-diode, and in case the communication is bidirectional, a laser diode will replace therein the antenna(s) used in case of wireless communication. A system to realize this is known from EP-A 733288. This is a system with independent photodiode and laser diode that are placed in-line. However, lateral pin diodes are very suitable as well for use as photodiodes. The device of the invention can be advantageously used therewith in view of the good broadband properties of the transmission lines in the interconnect structure.

The device of the invention is furthermore very suitable to comprise both optical coupling means and wireless coupling means. The optical coupling can then be used as a broadband connection to an external fiber network, and the wireless coupling can be used for communication to internal different functions, such as for instance amplifiers and loadspeakers, or light switches. Applications hereof are advanced television and also video telephones. Alternatively, the device is included in a hand-held apparatus, such as a mobile phone, or a portable computer. The wireless communication is then the main communication medium, but the optical communication can be used in addition thereto, for instance in that a fiber is temporally attached to the apparatus.

These and other aspects of the invention will be further elucidated with reference to the Figs., in which: Figs. 1 - 8 show schematic cross-sectional views of different stages of the first method according to the present invention;

Fig. 9 shows a SEM microphotograph of a semiconductor device obtainable in Fig. 7; and

Fig. 10 - 22 show diagrammatical cross-sectional views of further stages of the first method according to the present invention;

Fig. 23 shows a diagrammatical cross-sectional view of the resulting device;

Fig. 24-30 show diagrammatical cross-sectional views of different stages of the second method according to the invention;

Fig. 31 shows a diagrammatical cross-sectional view of the resulting device; Figs. 32 and 33 show diagrammatical cross-sectional views of further embodiments of the device;

Fig. 34 shows a detailed cross-sectional view of a part of Fig. 33;

Fig. 35 shows a graph showing the transmissions of coupling made with bond wires, metal balls and thin film interconnects. Fig. 36 shows a block diagram of an electronic device according to the invention.

Identical reference numbers indicate identical structural components.

Figs. 1 - 8 show schematic cross-sectional views of different stages of the method according to the present invention.

Fig. 1 shows a 700 μm thick silicon substrate 1, having a first side 2 and an opposed second side 3. The substrate 1 is provided with a thermal oxide layer 4, e.g. 1 μm thick on its first side 2. The resistivity of the substrate 1 will depend on the active semiconductor to be obtained eventually, the resistivity of the substrate usually ranging from 20 ohm.cm for bipolar semiconductors to 20 mohm.cm for CMOS semiconductors. In the latter case, the substrate 1 may comprise fully processed IC wafers.

On the first side 2 of the substrate 1 shown in Fig. 1 a layer of a patternable material 5, such as a 10 μm thick resist mask, is applied. The patternable material 5 is then patterned leaving a pattern of the patternable material on the first side 2 of the substrate. Then, first cavity or cavities 6 are formed in the first side 2 of the substrate 1 by removing a part of the substrate 1 that is not provided with the layer of patternable material 5, e.g. by etching (see Fig. 2). The person skilled in the art will readily understand that the first cavity 6 may also be formed into a via (see second cavities 13 in Figs. 10 and 16), if desired. Further the cavities 6 may have the same or different depths (which are usually obtained in different steps). Preferably, the first cavities 6 are formed using the Bosch process, as the first cavities 6 will then have very good side wall slopes.

In Fig. 3 the patternable material 5 has been removed from the first side 2 of the substrate 1, e.g. in a thermal or chemical way.

As shown in Fig. 4, the first side 2 of the substrate 3 is coated with a layer 7 of benzocyclobutene (BCB) to allow the electronic element 8 (shown in Fig. 5) to be adhered to the first side 2 of the substrate 1. The electronic elements 8 may be an IC, die, etc. which may be placed in the first cavities 6 by using standard "pick and place" techniques. The first cavity 6 in the substrate 1 and the electronic element 8 together define a gap 9, the gap 9 surrounding the electronic element 8.

As shown in Fig. 6 the gaps 9 are filled with a material 10, preferably BCB. In the embodiment shown this is done by placing a small droplet of the material 10 just above the gap 9, which material 10 may then be spread over the gap 9 by capillary action. g

Then, the first side 2 of the substrate is planarized by applying a layer 11 of e.g. BCB or a polyamide on the first side 2 of the substrate 1. IfBCB is used for both filling the gap between the electronic element 8 and cladding the walls of the first cavity 6, the electronic element 8 is then enveloped in BCB (see Fig. 7). Typically the layer 11 has a thickness of 5 - 10 μm. As is shown in the SEM microphotograph of Fig. 9, a remarkable planar first side 2 may be obtained with the method according the present invention.

Finally, contacts 12 are defined (see Fig. 8) by removing a part of the layer 11 at selected positions on the first side 2 of the substrate 1. For example, this may be done by etching. The product obtained in Fig. 8 may be further processed or interconnected to other semiconductor devices.

Fig. 9 shows a SEM microphotograph of a cavitied IC after planarization of the first side 2 with the layer 11 (cf. Fig. 7). Note the remarkable planar surface of the first side 2. Figs. 10 - 23 show schematic cross-sectional views of different stages of the method according to the present invention.

The method of the present invention may be continued on the basis of the semiconductor device obtained in Fig. 8, or on the basis of a ready-made (intermediate) semiconductor device. The semiconductor device obtained in Fig. 8 is further processed. If desired, second cavities 13 are formed in the substrate 1 in order to allow vias to be formed after thinning of the substrate 1 (see Fig. 16). However, these second cavities 13 may already have been formed at the same time as the first cavities 6 in Fig. 2.

The second cavities may e.g. be formed by applying a layer 14 of a patternable material on the first side 2 of the substrate 1 obtained in Fig. 8; then patterning the layer 14 leaving a pattern of the patternable material on the first side 2 of the substrate 1; and forming second cavities 13 on the first side 2 of the substrate by removing a part of the substrate 1 not provided with the layer 14. The result is shown in Fig. 10.

Subsequently, the patterned layer 14 is removed from the first side 2 of the substrate 1. Then a seed layer 15 of an electronically conducting material (e.g. copper, Cr/Cu, Ti/Cu, etc.) is applied on the first side 2 of the substrate 1 (see Fig. 11), thereby at least covering the contacts 12 obtained in Fig. 8.

As shown in Fig. 12 a plating mask 16 is then applied on the first side of the seed layer 15. Thereafter, a layer 17 of an electronically conducting material (e.g. copper) is applied on the top face of the seed layer 15, thereby at least partially filling up the plating mask 16 (see Fig. 13). Then, the plating mask 16 is removed from the first side 2 of the substrate 1 (Fig. 14).

As a further step the substrate 1 is thinned thereby exposing the bottom face of the electronic elements 8 and opening the second cavities 13 to the second side 3 of the substrate 1 (see Fig 16.).

However, previously, as shown in Fig. 15, the first side 2 of the substrate may have been provided with a releasable support 18 to improve mechanical stability of the substrate 1. The support 18 may be connected to the substrate 1 using a layer of an adhesive 19. The person skilled in the art will readily understand that the support 18, which may e.g. comprise metal, glass, plastics, etc., may also be provided using any other suitable means. For example the support 18 may be an UV releasable foil. The bottom face of the support 18 being connected to the first side 2 of the substrate 1 is preferably as planar as possible.

In Fig. 16 the result of the thinning of the substrate 1 is shown. The substrate 1 may be thinned by e.g. grinding to a thickness of less than 100 μm. If desired the substrate 1 may be thinned to a thickness of less than 20 μm.

As shown in Fig. 17 the second cavities 13 opened in Fig. 16 are filled with an electronically conducting material 20 (e.g. copper). The material 20 may be filled in the second cavities 13 by electroplating, while the layer 17 is used as a plating base. Then seed layer 21 of an electronically conducting material (e.g. copper) is applied on the second side 3 of the substrate 1 obtained in Fig. 17. Subsequently, a saw lane pattern 22 (e.g. from SU8 resist) is applied on the seed layer 21 (see Fig. 18).

As shown in Fig. 19 then a layer of an electronically conducting material 23 (e.g. copper) is then applied on the second side of the seed layer 21, preferably by electroplating, thereby at least partially filling up the saw lane pattern 22.

In Fig. 20 the substrate 1 is mounted on a standard separation foil 24. Thereafter, as shown in Fig. 21, the releasable support 18 and adhesive 19 are removed.

Then, the part of the seed layer 15 that is exposed after removing the plating mask 16 from the first side 2 of the substrate 1 in Fig. 14 is removed (see Fig 22). Finally, the semiconductor devices are separated by separating at the saw lane

22, e.g. by sawing. An active semiconductor device as shown in Fig. 23 is then obtained. Next, the individual devices may be further processed, e.g. soldered into or onto a package and subsequently connected (e.g. using wire bonding, flip chip and other conventional packaging techniques, etc.). The semiconductors according to the present invention are extremely suitable for use at frequencies above 10 and even 20 GHz.

Fig. 24-Fig. 31 shows schematically different stages of the second method resulting in the device of the invention. This second method differs from the first method, in that the active devices 8 are not provided in cavities 6 extending from the first side 2, but in cavities from the second side 3.

Fig. 24 is a diagrammatical cross-sectional view of a first stage in this method. Basically, it shows a fully processed wafer of a semiconductor material, in this case silicon, on top of which an interconnect structure 40 is provided. The interconnect structure 40 comprises transmission lines 17 and vertical interconnects 27 extending to the first side of the semiconductor substrate 1 and through the thermal oxide layer 4. The interconnect structure 40 may further comprise any passive elements as desired. Contrary to conventional processing, there are vertical interconnects 27 that are not connected to underlying semiconductor elements. The interconnect structure 40 further comprises bond pads 29 for external connection. These bond pads could be used for wirebonding. However, for a good high frequency behavior the use of solder balls is preferred. It is even more preferred that all high-frequency functions will be integrated on and in the substrate 1. In that case the connections are needed only for power and relatively low-frequency input and output signals. A flex foil can then be used therefore. For reasons of clarity a one-layer interconnect structure 40 is shown. However, in order to interconnect the active elements in the substrate, a multilayer interconnect structure is necessary.

Fig. 25 shows the substrate 1 in a second stage of the processing. First of all, the substrate 1 as shown in Fig. 24 is provided with a mechanical support 18 on its first side 1. In this case, a glass support wafer 18 is used which is attached to the substrate 1 using UV releasable glue 19. Thereafter, the substrate 1 is thinned from its second side. These steps are identical with the steps shown in Figs. 15 and 16. Finally, a suitable etching mask 31 is deposited and patterned. In this case an etching mask of aluminum is used, that has been provided by chemical vapor deposition and that has been patterned photolithographically. Such an etching mask 31 may also be provided in different manners, for instance with any kind of printing, with sputtering through a mask and the like.

Fig. 26 shows the substrate 1 in a third stage, after the substrate has been etched through the etching mask 31 The etching mask 31 is suitable for dry etching, but also for wet etching with for instance potassium hydroxide or tetramethylammonium hydroxide. The result of this wet etching is cavities 6 with side walls that enclose an angle of about 45- 50 ° with respect to the plane of the substrate 1. These tapered side walls have the advantage that placement of active devices gets easier as the fit in the cavity is less tight.

This second method of the invention has the advantage that the substrate 1 at the second or at the third stage as shown in Fig. 25 and Fig. 26 can be transferred to an assembly plant for further processing. This further processing is done at a larger scale and involves standard steps such as die placement, electroplating and separation.

Fig. 27 shows the substrate 1 in a fourth stage, after placement of active devices 8. In order to ensure good contact, it is preferable for the vertical interconnects 27 which have appeared on the surface in the cavity 6 to be provided with metal contacts, particularly of Au, through electroless deposition of Ni/Au. The active devices 8 are provided with solder or metal bumps 32. After the placement, an underfill is provided and a heat treatment is performed so as to provide a metallic contact between the bumps 32 and the vertical interconnects 27. Instead of an underfill, use can be made of a liquifying layer which is provided in the cavity 6 before placement of the active devices 8. A good example of such liquifying layer is an acrylate layer, that will liquify under heating to about 60-100 ⁰C. Another example is benzocyclobutene (BCB), which becomes a waterlike fluid at about 17O⁰C. When the temperature is brought to over 200 ⁰C, the BCB cures into a hard adhesive layer. A further alternative to the underfill is the provision of a glue layer on the surfaces of the active devices. The glue layer is preferably patterned, so as to enable the provision of bumps 32. A preferred glue layer is BCB.

Fig. 28 shows the substrate 1 in a fifth stage, after provision of the underfill and after planarization of the rear sides of the active devices 8 and the second side 3 of the substrate 1.

The device 100 is now ready, but for the cavities 6 to be filled and the heatsink 23 to be applied. In this embodiment, the heatsink 23 fills the cavities 6, and it covers substantially the complete second side 3 of the substrate 1. It is however not necessary to fill the cavities with the heatsink. The cavities may be filled with a material having a thermal expansion coefficient that matches the thermal expansion of the active devices 8. Alternatively, an elastic material may be chosen so, that mechanical stress between the active devices 8 and the substrate 1 is absorbed.

Fig. 29 shows the substrate 1 after a plating base 21 has been applied to the second side 3 of the substrate 1, and after a resist 22 has been provided and patterned in areas at which no heatsink is desired. A suitable plating base is Cr/Cu. A suitable resist is SU8. Fig. 30 shows the substrate 1 after that the heatsink 23 of copper has been grown by electroplating. The advantage of the electroplated copper is that it has low stress. An advantage of the filling of the cavities 6 with copper is that the active devices 8 get surrounded by metal. This metal acts as a Faraday cage, therewith suppressing electromagnetic coupling to the surroundings. The heat sink 23 may have a thickness of more than 100 μm. Mechanical stability is optimized thereby. This is not necessary, however, particularly not if the device is attached to a leadframe and encapsulated in a protecting mold.

Fig. 31 shows the device 100 after removal of the support wafer 18 and the separation. It will be understood that vertical interconnects may be provided between the interconnect structure and the heat sink, such as shown in Fig. 19. Although the Figure provides the suggestion that the substrate 1 is removed to a large extent, this need not be and is generally not the case.

Fig. 32 shows a diagrammatical cross-sectional view of another embodiment of the device 100 of the invention. In this embodiment, the heat sink does not completely extend over the second side 3 of the substrate 1. Instead thereof, contacts 43 are provided in addition to the heatsink 23, therewith enabling the placement of the device 100 on a carrier without the need for a leadframe. Nevertheless, the pattern of the contacts 43 and the heatsink 23 is at least largely identical with that of conventional leadframes, as for instance the HVQFN (high voltage quad flat non-leaded) leadframe. In order to realize this, the heatsink 23 may cover the active devices 8 only partially, as is shown in the Figure.. In a further embodiment (not shown), the heatsink could be applied in two steps, the first layer of the heatsink having a different pattern than the second heatsink. This can be called "rerouting" of the heatsink.

In this embodiment, the first side 2 of the substrate 1 is provided with an encapsulating layer 41. This material is for instance a filled epoxy or a polyimide, as is known to the skilled person. This encapsulating layer 41 can be provided on wafer level, e.g. before separation of the device. It may have any desired thickness, for instance in the order of 0.1-100 μm, and is chosen such that it can be cut easily with conventional sawing apparatus. The encapsulating layer may be provided before the attachment of the support wafer, or after the removal of the support wafer. In principle, it could be used instead of the support wafer. Then however, the encapsulating layer is preferred to have sufficient thickness. Preferably, it is then provided as a multilayer stack. This stack could for instance include a security coating that is not transparent and cannot or can hardly be removed so as to prevent reverse engineering of the underlying circuit. Fig. 33 shows a further embodiment of the device 100 of the invention. In this embodiment, the substrate 1 comprises active elements, in this case field effect transistors 81, 82, 83 having source electrode, drain electrode and gate electrode. The interconnect structure 40 in this embodiment includes not only the interconnects between the active devices 8 and other elements, but also the interconnects between the individual transistors 81,82,83, within the integrated circuit itself. In this case the interconnect structure 40 further includes vertical interconnects 27 extending to contacts 43 on the second side 3 of the substrate 1.

Although not shown here, it is preferred that the connection between the contacts 43 and the interconnect structure is made at the third or higher level of the interconnect structure only. In order to realize this, the interconnect structure is partitioned into an area for the integrated circuit and an area for the active device 8. These areas are mutually insulated by insulating material at the non-interconnected lower levels, so that the signal to the active device 8 does not affect the signal of the individual transistors 81,82,83.

Fig. 34 shows a detail of Fig. 33 showing more clearly the connection to the contact 43 which is at the same level as the transistor 81. The connection to the active device 8 is basically the same as that to the contact 43. The semiconductor wafer is shown here to have various doping zones 51, 52,53,54,55. The main part 51 of the substrate 1 that is partially removed, is a p⁺-zone. The transistor 81 is formed in and on an p-type epilayer 52. The source and drain electrodes 53, 54 are highly doped zones at the surface of this epilayer 52. Finally, there is a highly doped

55 acting as an interconnect. The transistor is further provided with a gate electrode 59, which is separated from the epilayer 52 through a non-shown thin gate oxide. The substrate 1 is provided with a thermal oxide 4 on its first side 2. This thermal oxide 4 is patterned and vertical interconnect 27, as well as contacts 63,64 to the source, drain and gate electrode are provided (the contact to the gate is not shown). It is understood that a metal connection that is suitably insulated from the semiconductor substrate may be used instead of the highly doped zone in the silicon itself. The undesired interaction between vertical interconnects and transistors can be prevented through the use of adequate design rules, such as for instance a minimal distance of 5 to 10 μm. The resulting effect is neglegible in view of the fact that the epilayer 52 generally has a very limited thickness only.

Fig. 35 shows a graph in which the transmission as a function of the frequency is compared for various coupling techniques. The continuous lines show from the bottom to the top the transmission of a bond wire, of a metal or solder ball and of an thin-film interconnect. The dotted line shows a bond wire compensated with a capacity at 30 GHz. The graph is the result of a simulation done for the transfer of a source of 50 Ω to another source of 50 Ω. The result of the use of bond wires without compensation is a transmission of —3 dB at 30 GHz. This corresponds to a reduction of the signal intensity by 50 %. The compensated bond wires provides a better result at those frequencies, but have the disadvantage that only for exactly 30 GHz the transmission is unaffected. At about 25 GHz the transmission is only -IdB. This is already problematic, in view of the large number of signals to be processed and particularly in view of the fact, that the signals are preferably kept small at these frequencies so as to reduce heat dissipation.

Fig. 36 shows a block diagram of an electronic device according to the invention, which contains only low-frequency input signals. The device 100 comprises a transceiver 111, which is provided with six inputs. These input signals and the corresponding output signals are converted through a multiplexer and demultiplexer unit 119. Coupled to the transceiver are a VCO tank 116, a PLL loop filter 117 and a supply decoupling unit 118. The transceiver 111 is capable of sending signals to the antenna 131 and receiving signals from the antenna 131. A TX/RX switch 114 is present for switching from the receiver to the transmitter function and vice versa. The transmit path between the transceiver 111 and the switch 114 comprises a power amplifier 121 and an impedance matching function 122, as well as a filter 123. The power amplifier 121 generally comprises two or more stages, one of which may be bypassed. The receive path between the switch 114 and the transceiver 111 comprises a filter 124, and a low noise amplifier 125. This low noise amplifier can be integrated in the transceiver 111. A bandpass filter 126 is present between the antenna 131 and the switch 114.

Although not shown here for reasons of clarity, the TX/RX switch 114 generally comprises the switching function between different frequency bands, such as the DSC band, the GSM band, the Bluetooth band and any further band. The TX/RX switch comprises furthermore the passive elements and switches needed to prevent any amplified signal from reaching a receive path in which it will blow up the amplifier. However, particularly if high frequencies are present, it is advantageous to use two separate antennas for different frequency ranges. Antennas for high frequencies of 20 GHz can be very small, and the band separation gets easier.

In the present invention, the TX/RX switch 114 and the impedance matching function is realized with MEMS-capacitors and switches, which are provided as part of the interconnect structure. The power amplifier 121 is realized as an active device with a substrate of a III- V material, such as GaAs of GaN. Good results have been obtained in that the active device comprises transistors of the HBT-type. The transceiver 111 is embodied as an active device with a substrate of a III- V material, particularly of InP, that is suitable for frequencies from 10-40 GHz. For the Voltage Controlled Oscillator 116 use is made of an active device of a SiGe substrate. All these active devices are provided in cavities, except for the VCO 116, which is embodied in the substrate itself. The VCO 116 may operate at a lower frequency than the transceiver and be upconverted afterwards, for instance from 20 to 40 GHz. The interconnect structure comprises the inductor (non-shown), which is needed as VCO coil. The PLL loop filter 115 is spread over the interconnect structure and the substrate. The band pass filters and other filters can be baluns and LC filters that are integrated in the interconnect structure. Alternatively, at least some of them can be BAW-fϊlters. These can be suitably provided as separate blocks in cavities in the substrate or with bumps on the interconnect structure. Such passive functions can be provided on top of the substrate with bumps, since they do not need any connection to a heat sink.

Claims

CLAIMS:

1. An electronic device comprising:

- a substrate of a semiconductor material having a first and a second opposite side, and on its first side provided with a plurality of semiconductor elements which are mutually interconnected so as to form an integrated circuit; - an active device, that has a coupling surface provided with connection pads and is present in a cavity in the substrate, the cavity having an aperture on the first side of the substrate, at which aperture the coupling surface is present, and

2. An electronic device as claimed in claim 1, characterized in that the active device comprises a substrate of a compound semiconductor material in which semiconductor elements are defined.

3. An electronic device as claimed in claim 2, wherein the active device comprises a high-frequency power amplifier.

4. An electronic device as claimed in claim 3, wherein the compound material is

GaAs.

5. An electronic device as claimed in claim 2, wherein the active device comprises an RF circuit and at least part of the semiconductor elements in the substrate define an oscillator.

6. An electronic device as claimed in claim 5, wherein the compound material is InP.

7. An electronic device as claimed in claim 1, characterized in that:

- the substrate comprises silicon;

- the semiconductor elements are CMOS transistors, and

- the active device comprises a bipolar transistor.

8. An electronic device as claimed in claim 1, characterized in that individual conducting layers in the interconnect structure are separated by air gaps or porous layers.

9. An electronic device as claimed in claim 1, characterized in that the active device is provided with a plurality of semiconductor elements and an internal interconnect structure, through which only part of the semiconductor elements is mutually interconnected according to the desired circuit.

10. An electronic device as claimed in claim 1, characterized in that the connection pads of the active device are electrically connected to the interconnect structure via highly doped diffusion zones in the semiconductor substrate.

11. An electronic device as claimed in claim 1, characterized in that the interconnect structure comprises a passive element.

12. An electronic device as claimed in claim 1, characterized in that a ground plane is present on the second side of the substrate, vertical interconnects being present between the ground plane and the interconnect structure.