Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
  • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region

Definitions

• the present invention relates to methods for forming and connecting regions in a semiconductor device, and more particularly for connecting drain regions in P-channel flash memory cells to reduce memory array device sizes .
• a flash memory array comprises an array of flash memory cells.
• a prior art P channel flash EPROM cell 100 for use in such an array is shown in Figs. 1-3.
• a top view of memory cell 100 shows a drain contact 110, a P+ drain region 120, a floating gate 130, a control gate 140, field oxide regions 150a and 150b, and P+ source regions 160a and 160b, with source region 160a being the source of memory cell 100 and source region 160b being an extended portion of region 160a used to connect source regions of adjacent memory cells .
• Fig. 2 is a cross sectional view of memory cell 100 along line A-A' of Fig. 1.
• P+ drain 120 and P+ source 160 are formed in an N well 200 with a channel formed therebetween.
• Floating gate 130 is insulated from the channel region by a tunnel oxide 210.
• tunnel oxide 210 is used to refer to what often is called “gate oxide” because in these kinds of memory devices, i.e., flash memory cells, the oxide under the gate must allow the tunneling of electrons back and forth between the floating gate and the silicon substrate.
• the term “tunnel oxide” is used to reflect the dual function of the gate oxide (i.e., to insulate and to allow tunneling of electrons) in this type of memory.
• an interpoly dielectric 220 provides insulation from control gate 140.
• a doped oxide 230 such as boron-phosphorous silicate glass (BPSG) or other suitable material insulates the underlying layers.
• Drain contact 110 includes a titanium nitride (TiN) layer 240 and a titanium (Ti) layer 250 located between drain 120 and a tungsten (W) plug 260.
• Fig. 3 is a cross sectional view of memory cell 100 along line B-B' of Fig. 1, showing field oxide 150 and tunnel oxide 210 separating N well 200 from floating gate 130, interpoly dielectric 220, and control gate 140.
• drain contact 110 One area of the cell 100 which has been difficult to reduce is the region between drain contact 110 and floating gate 130 and control gate 140, shown in Figs. 1 and 2. Reduction is difficult because of the need to protect gates 130 and 140 from being etched during the formation of drain contact 110.
• a masking operation first defines a contact region above drain 120. The unprotected areas of oxide layer 230 are then etched to expose the desired drain contact region.
• a tungsten plug 260 is then formed within this region, separated by a barrier layer of Ti 250 and TiN 240, to create drain contact 110. If the masking operation is misaligned such that areas over control gate 140 and/or floating gate 130 are unprotected, the subsequent etching of oxide layer 230 will remove portions of these gates, thereby damaging cell 100. As a result, drain region 120 and the region of oxide 230 separating drain contact 110 from gates 130 and 140 must be larger than ideally necessary to insure that portions of gates 130 and 140 will not be etched away during formation of drain contact 110 if a masking misalignment occurs.
• a flash memory cell which has a decreased oxide separation between a drain contact and the floating and control gates, resulting in a smaller memory cell and thus a higher density memory array.
• a process flow for forming self-aligned drain contacts in flash memory cells is provided which reduces the oxide separation between drain contacts and the floating and control gates.
• a silicon dioxide layer and a nitride layer are formed on stacked-polysilicon floating and control gates and then etched to form oxide spacers and nitride spacers along the sidewalls of the stacked-gate structures .
• a dielectric such as BPSG or BPTEOS, deposited over the nitride spacers, the stacked-gate structures, and drain and source regions, is planarized for masking and etching.
• a drain contact mask exposes drain portions between nitride spacers, and the dielectric is etched to expose drain contact regions. Tungsten is deposited in these regions and etched back to form the drain contacts. Because the nitride layer around the polysilicon gates prevents polysilicon from being etched away during the oxide etch, additional oxide between the polysilicon gates and the drain contact is no longer needed to protect against the consequences of contact mask misalignment. As a result, the drain contact can be much closer to the polysilicon gates, thereby reducing cell size and increasing memory array density.
• FIG. 1 is a top view of a conventional PMOS flash memory cell
• Fig. 2 is a cross sectional view of the memory cell of Fig. 1 along lines A-A' ;
• Fig. 3 is a cross sectional view of the memory cell of Fig. 1 along lines B-B' ;
• Figs. 4-10 are cross sectional views of a self- aligned drain contact PMOS flash EPROM process flow according to the present invention.
• Fig. 11 is a top view of a PMOS flash memory cell according to the present invention.
• Fig. 12 is a cross sectional view of the memory cell of Fig. 11 along lines C-C ;
• Fig. 13 is a cross sectional view of the memory cell of Fig. 11 along lines D-D' . Use of similar reference numbers in different figures indicates similar or like elements.
• a process and structure are provided which allow a reduction in size of flash memory cells by reducing the oxide separation between drain contacts and polysilicon gates through the use of a nitride layer.
• Figs. 4-10 are side views illustrating a process flow for forming self-aligned drain contacts in flash EPROM cells according to one embodiment of this invention.
• a tunnel oxide layer 410 is first formed on a silicon substrate or well 400.
• a first layer of polysilicon (Polyl) 420 which will later form floating gates for the memory array, is then deposited on tunnel oxide 410.
• an interpoly dielectric layer 430 is formed on Polyl 420.
• dielectric layer 430 can be an oxide-nitride-oxide (ONO) layer formed by growing or depositing a layer of silicon dioxide on Polyl 420, followed by depositing a layer of silicon nitride or other suitable insulating nitride and then growing or depositing another layer of silicon dioxide.
• a second layer of polysilicon (Poly2) 440 or a layer of polycide is then deposited on dielectric layer 430, where Poly2 440 will eventually form the control gates for the memory array.
• Another layer of silicon dioxide 450 is formed on Poly2 440, followed by a layer of silicon nitride (Nitridel) 460 formed on silicon dioxide layer 450. Silicon dioxide 450 provides padding between Poly2 440 and Nitridel 460. The ranges and preferred thicknesses of these layers are provided in Table 1 below.
• stacked-gate structures 500 can be formed, as shown in Fig. 5.
• a layer of silicon dioxide (not shown) is first thermally grown on the polysilicon sidewalls of the stacked-gate structures, followed by deposition of another layer of silicon dioxide 610 over the surface of the structure. Because this deposited silicon dioxide layer conforms to the top surface of the structure shown in Fig. 5, a blanket etch, i.e., an oxide etch without a photomask, removes the thinner horizontal portions of this conformal silicon dioxide layer, but leaves the thicker vertical portions of this conformal silicon dioxide layer to form oxide spacers 610 on the vertical sidewalls of stacked-gate structures 500.
• a second layer of silicon nitride (Nitride2) 620 is subsequently deposited as a conformal layer and etched isotropically, thereby forming nitride spacers 710 in Fig. 7, which protect the stacked-gate edges during a later drain contact etch.
• a conventional self-aligned source (SAS) etch may now be performed to decrease the size of the to-be-formed source regions.
• SAS self-aligned source
• field oxide 150b is etched away, which exposes the silicon substrate underneath where dopant implantation for source regions is to occur.
• the SAS etch aligns floating gate 130 and control gate 140 with the source doping region, thereby eliminating the need for field oxide region 150b to separate the polysilicon gates 130 and 140 from the source region.
• Dopants can then be implanted during a subsequent step to form source regions 800a and 800b, as shown in Fig. 11. As a result, source region 160b (Fig. 1) is no longer necessary since source region
• 800b can now connect the source regions from adjacent memory cells.
• an SAS etch is used as a method to reduce source regions, which reduces overall cell size, during a flash EPROM process flow by etching away unnecessary field oxide.
• the self-alignment of source regions allows closer placement of polysilicon gates, thereby requiring less physical separation between (i.e, allowing closer placement of) one memory cell to the next memory cell.
• P+ regions for the sources 800 and drains 810 are formed, for example, by ion implanting dopants to form source and drain regions and then annealing the resulting structure at 800°C for 20-40 minutes.
• a layer of boron-phosphorous doped TEOS (BPTEOS) 820 or other suitable dielectric such as BPSG is deposited and smoothed using a reflow process at 850°C for 15-20 minutes.
• Chemical/mechanical polishing (CMP) is then performed to planarize and reduce BPSG layer 820 down to a thickness of 3000-3500 A. Table 1 below lists the ranges and preferred values of these various layers .
• drain contact regions 910 Conventional masking or direct write techniques can then be used to define drain contact regions. For example, in Fig. 9, after a layer of photoresist (not shown) is deposited on BPSG layer 820, the photoresist is masked to define drain contact region 910. A self- aligned contact etch or high selectivity oxide-to- nitride etch then removes the desired areas of BPSG to form drain contact regions 910.
• Ti titanium
• TiN titanium nitride
• both Ti and TiN are annealed at 585°C for 20 minutes in N 2 to form barrier layers for deposition of tungsten (W) plugs.
• a 6000 A thick tungsten layer is deposited into the drain contact region in a well known manner, for example using chemical vapor deposition (CVD) .
• Self-aligned drain contacts 1010 are then formed after CMP or another suitable etchback method planarizes the tungsten layer into tungsten plugs 1020.
• Figs. 11-13 show different views of one of stacked gate memory cells 500 formed in accordance with this invention.
• Fig. 11 is a top view of cell 500 showing drain contact 1010, P+ drain 810, P+ sources 800a and 800b, field oxide 1100, floating gate 420, and control gate 440.
• Figs. 12 and 13 are cross sectional views of memory cell 500 along lines C-C and D-D' , respectively, of Fig. 11. As seen from Figs. 11 and
• the size of memory cell 500 is reduced in both the source and the drain regions as compared with memory cell 100 of Figs. 1 and 2.
• Source regions are reduced by removing field oxide 150b between source 160b and polysilicon gates 130 and 140 in Fig. 1 through a conventional SAS etch.
• drain regions are reduced because drain contacts can be formed much closer to the polysilicon gates, thereby substantially reducing the amount of oxide between the polysilicon gates and the drain contacts. The result is a much smaller memory cell, which leads to denser memory arrays.
• the additional oxide, which was needed for possible misalignment of drain contact masks, is eliminated because nitride spacers formed around the polysilicon gates prevent the oxide etch from removing portions of the polysilicon gates.
• the stacked-gate etch can be performed to allow more stacked-gate structures 500 to be formed on substrate 400 by reducing the amount of space between each stacked-gate structure 500, as shown in Fig. 5.
• the drain contact etch can now be performed without preserving the additional oxide needed to protect the polysilicon gates, which greatly decreases the separation between successive memory cells 500, as shown in Fig. 9. Therefore, using the self-aligned drain contact flow process according to this invention, smaller memory cell sizes and higher density memory arrays are possible.

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• 1998
  • 1998-09-10 TW TW087115074A patent/TW463331B/zh not_active IP Right Cessation
  • 1998-09-24 WO PCT/US1998/002977 patent/WO1999017360A1/en active Application Filing
  • 1998-09-24 AU AU95648/98A patent/AU9564898A/en not_active Abandoned
  • 1998-09-25 CN CN98119593.8A patent/CN1212468A/zh active Pending

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