WO1999013510A1

WO1999013510A1 - Esd protection technique using mos transistor with thick gate oxide

Info

Publication number: WO1999013510A1
Application number: PCT/US1998/018164
Authority: WO
Inventors: James C. Moyer
Original assignee: Micrel, Incorporated
Priority date: 1997-09-11
Filing date: 1998-09-10
Publication date: 1999-03-18

Abstract

An ESD protection technique is described which incurs virtually zero leakage current and, in certain embodiments, uses no additional silicon area for ESD protection. In this technique, an input MOS transistor for a circuit, such as an operational amplifier, on an integrated circuit chip is provided with a very thick gate oxide which does not break down upon application of an ESD voltage. The MOS transistor functions within the circuit itself, yet also provides ESD protection. Thus, no area is used for a dedicated ESD protection circuit, and the leakage current is insignificant (i.e., on the order of femtoamps).

Description

ESD PROTECTION TECHNIQUE USING MOS TRANSISTOR WITH THICK GATE OXIDE

FIELD OF THE INVENTION

This invention relates to an MOS transistor structure, and, in particular, to an MOS transistor structure which is used to provide electrostatic discharge (ESD) protection for a circuit, such as an operational amplifier.

BACKGROUND

It is very common for a packaged integrated circuit (IC) to have an ESD protection circuit connected between a lead on the package and an input into the main circuit on the chip. Fig. 1 shows a prior art IC package 10 containing conventional ESD protection circuits 12 on an IC chip 14. Each ESD protection circuit 12 is shown connected between a chip contact pad 15 and the main circuit 16 on the chip 14. A package lead 18 is connected to a pad 15 via a wire or other conductor 19.

Fig. 2 shows a magnified portion of package 10. As shown in Fig. 2, an ESD protection circuit 12 is typically a series diode circuit 20 which shunts a high ESD voltage applied to lead 18 to a positive voltage rail 22 and shunts a negative ESD voltage to ground or a negative voltage rail 24 to prevent the ESD voltage from destroying the input circuitry of the main circuit 16 on the chip. Such input circuitry of the main circuit 16 typically consists of one or more conventional MOS transistors 26 or bipolar transistors, where the ESD voltage would cause a disruption of the gate oxide of the MOS transistor or a breakdown of the bipolar transistor, destroying the input circuitry. Thus, dedicated ESD protection circuits 12 are typically provided around the perimeter of the chip 14 to prevent damage to the main circuitry. Such conventional ESD protection circuits have a leakage current typically in the range of lOOpA to InA. This leakage current becomes significant in certain applications .

Hence, it is desirable to reduce the leakage current into ESD protection circuitry.

SUMMARY

An ESD protection technique is described which incurs virtually zero leakage current and requires no silicon area for a dedicated ESD protection circuit. In this technique, an input MOS transistor for a circuit, such as an operational amplifier, on an integrated circuit chip is provided with a very thick gate oxide which does not break down upon application of an ESD voltage. The MOS transistor functions within the circuit itself and is not susceptible to ESD damage up to the rupture voltage of the thick oxide. Thus, the circuit can be handled by normal means and the leakage current is insignificant (i.e., on the order of femtoamps) . In certain embodiments, the resulting die may be smaller than a die using a dedicated ESD protection circuit.

In one embodiment, the gate oxide is field oxide. Although using field oxide as the gate oxide reduces the transconductance of the transistor, this effect may be counteracted by making the transistor larger. Other transistors within the main circuitry may be conventional MOS transistors, using a conventional thin gate oxide for high speed, or may be bipolar transistors .

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a top down view of a conventional IC package containing an IC with ESD protection.

Fig. 2 is a magnified portion of Fig. 1 illustrating a conventional ESD protection circuit.

Fig. 3 is a top down view of an IC package incorporating an IC chip using the present invention, where an ESD protection transistor is also used as part of a circuit on the chip.

Fig. 4 is a top down view of an MOS transistor which provides ESD protection for a circuit while also performing a function in the circuit.

Fig. 5 is a cross-sectional view of the MOS transistor of Fig. 4 along line 5-5 in Fig. 4.

Fig. 6 is cross-sectional view of a conventional MOS transistor. Figs. 7A and 7B constitute a schematic diagram of an operational amplifier incorporating ESD protection transistors as well as bipolar transistors.

Figs . 8A and 8B constitute a schematic diagram of a trim circuit for the operational amplifier of Figs. 7A and 7B .

DETAILED DESCRIPTION OF THE EMBODIMENTS

Fig. 3 illustrates an integrated circuit package 30 incorporating one embodiment of the present invention. The package body 32 may consist of a ceramic, plastic, or metal base having metal leads 34 extending therefrom. Leads 34 may also be in the form of solder bumps on the underside of body 32 or any other known terminal for a package. Leads 34 are connected via wires or other conductors 35 to pads 36 on a IC chip 38.

A circuit 40, such as an operational amplifier, is formed on chip 38 using photolithographic, deposition, and etching techniques. Internal to circuit 40 is at least one MOS transistor 42 whose gate is connected directly to a pad 36. Transistor 42 provides an input function for circuit 40 as well as provides ESD protection for circuit 40. Circuit 40 contains other transistors, which may be conventional, for carrying out the remainder of the functions of circuit 40. MOS transistor 42 is formed to have a thick gate oxide so as to sustain a high ESD voltage between its gate and its source/drain/channel region. In one embodiment, this thick gate oxide is field oxide, which also insulates the metal conductors on the surface of the chip from the underlying silicon surface of the wafer. While conventional MOS transistors have a gate oxide thickness on the order of about 100 angstroms to 1000 angstroms to achieve a desired performance, the thick field oxide used as gate oxide in transistor 42 has a thickness greater than about 0.5 micron (5000 angstroms) . A practical upper thickness is about 1 micron. The thickness of the gate oxide for transistor 42 depends upon the level of ESD protection desired. Oxide has a dielectric strength of about 800 volts per micron. Therefore, a thick oxide of 6000 angstroms provides ESD protection of up to about 500 volts. This is compared to a dielectric breakdown of only 10-70 volts for conventional MOS transistors, which use a separate ESD protection circuit to prevent dielectric breakdown.

In one embodiment, circuit 40 uses an operating voltage of less than or equal to approximately 30 volts, and an intended input voltage applied to the gate of transistor 42 for normal operation of circuit 40 is also less than or equal to 30 volts. In other embodiments, the operating voltage is less than or equal to 5 volts, and the specified input voltage applied to the gate of transistor 42 for normal operation of circuit 40 is within the range of ± 5 volts.

Fig. 4 is a top down view of one embodiment of the MOS transistor 42 having a thick gate oxide, and Fig. 5 is a cross-sectional view of transistor 42 along line 5-5 in Fig. 4. Assuming transistor 42 is a P-type, an annular P+ source region 50 (partially obscured by metal) is formed in an N-type semiconductor wafer 52 or an N-type epitaxial layer. A ring of source metal 54 is in contact with the P+ source region 50. A P+ drain region 56 is shown in the middle of the transistor 42 contacted by drain metal 58. Between source region 50 and drain region 56 is a very lightly doped P-type channel region 59 obscured by a polysilicon gate 60 overlying the channel region 59. Doping the channel region 59 with P-type dopants reduces the turn-on voltage of the transistor 42 and, if sufficient to cause the channel region to be P-type, may be used to form a depletion mode transistor. The channel implant may be adjusted to form an enhancement transistor.

A layer of oxide 62 (Fig. 5) grown over the polysilicon gate 60 prior to metallization insulates the metal 54 and 58 from gate 60.

A thick field oxide 64 (Fig. 5) , insulating gate 60 from the channel region 59, is grown or deposited on substrate 52 and may serve a variety of purposes in addition to insulating gate 60 from channel region 59. One purpose is to insulate substrate 52 from the overlying metal 54 and 58 and other metal lines. It is important that field oxide 64 be relatively thick (e.g., 0.5-1 micron) so that voltages applied to the metal lines do not invert the conductivity type of the underlying substrate. The doping of channel region 59 with P-type dopants lowers the threshold voltage of transistor 42 so that gate 60 can more efficiently control the conductance of transistor 42 through the thick oxide 64. In one embodiment, the threshold voltage is 0 volts. In one embodiment, field oxide 64 also serves as a composite mask for forming various doped regions. Such a composite mask is described in PCT Publication No. W0/96/30936, entitled Self-Alignment Technique for Semiconductor Devices, by Martin Garnett et al . , assigned to the present assignee and incorporated by reference. In that PCT publication, a single oxide layer is patterned using a single mask, and the resulting pattern is used to self-align various doped regions for different components. The thick oxide 18 in Fig. 6A of the PCT publication would be also utilized as a gate oxide for an N-channel or P-channel MOS transistor to provide ESD protection for a circuit in accordance with the present invention. The composite mask may be used to form bipolar transistors and other MOS transistors.

The self-alignment technique described in U.S. Patent No. 5,141,881 to Takeda et al . , incorporated herein by reference, may also be used to form regions of transistors self-aligned with one another. The technique described by Takeda et al . is easily modified to form a gate of an ESD protection transistor overlying the field oxide 26 in the various figures of the Takeda et al . patent. Any technique for forming transistor 42 having a thick oxide 64 may be used, as would be understood by those skilled in the art, and the optimum technique would depend on various factors. For example, the oxide 64 insulating gate 60 may be formed in a step separate from, or in addition to, the steps used to form any field oxide to achieve the desired ESD protection.

The MOS transistor having the thick gate oxide may also be an N-channel type, by using N-type source and drain regions, and may be an enhancement mode or depletion mode device. Fig. 6 is a cross-section of a conventional MOS transistor to illustrate the relative gate oxide thicknesses. In Fig. 6, a thin gate oxide 66 of about 100-1000 angstroms insulates gate 67 from channel region 68. A source region 69, drain region 70, field oxide 71, and metal lines 72 are also shown.

In one embodiment, MOS transistor 42 is an input transistor for a circuit using other types of transistors, although the circuit may use all MOS transistors having the same oxide 64. The other transistors which may be incorporated in the circuit include MOS transistors having a thin gate oxide (e.g., 100-1000 angstroms thick) or bipolar transistors.

Figs. 7A and 7B constitute an operational amplifier incorporating the present invention. The input MOS transistors 76 and 78 are formed with thick gate oxides between 5000-6000 angstroms to provide ESD protection of up to 500 volts. Transistors 76 and 78 are connected in a differential amplifier configuration, with inputs Nl and INV, as part of the operational amplifier. The gates of transistors 76 and 78 are directly connected to leads of an integrated circuit package. No additional ESD protection is required. The operational amplifier may be the main circuit 40 identified in Fig. 3.

The output of the operational amplifier is provided at node 80 in Fig. 7B .

Figs. 8A and 8B illustrate a trim circuit 82 for the operational amplifier of Figs. 7A and 7B with the various connections identified.

The ESD protection provided by transistors 42 (Figs. 3-5), 76, or 78 (Fig. 7A) is a function of the thickness of its gate oxide. The thickness of the gate oxide is not based on the specified intended range of operating or input voltages for circuit 40 (Fig. 3) , as in the prior art, but on the ESD protection desired. A reasonable level of ESD protection is up to 500 volts; however, the present invention can be used to increase the level of ESD protection to greater than 2000 volts. Since typical operating voltages are less than 30 volts, the MOS transistors of this invention provide ESD protection of greater than ten times the operating voltage. For operating voltages of 5 or less volts, the ESD protection is between approximately 100 to 400 times the operating voltage. The maximum sustained voltage for an MOS transistor is about 40% of the gate oxide rupture voltage, so MOS transistors providing ESD protection up to 500 volts can be reliably operated at 200 volts or less . The MOS transistors in accordance with the present invention may serve as input transistors for virtually any circuit which requires an extremely low input current while providing ESD protection.

Adjusting the channel width of the MOS transistor to achieve the desired transconductance and adjusting the threshold voltage enables the transistor to substitute for conventional MOS transistors in an input circuit while providing low leakage current and ESD protection. Adding a resistor (e.g., a polysilicon resistor) in series between the contact pad and the gate of the transistor to achieve an RC time constant will smooth an ESD spike and further increase the ESD protection provided by the transistor. While particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from this invention in its broader aspects and, therefore, the appended claims are to encompass within their scope all such changes and modifications as fall within the true spirit and scope of this invention.

Claims

CLAIMSWhat is claimed is:

1. An integrated circuit device comprising: an integrated circuit die having formed on it a circuit for performing a function, said integrated circuit die having contact pads for connection to leads of a package containing said die, at least one of said contact pads on said die being connected to a gate of an MOS transistor, said MOS transistor providing electrostatic discharge protection for said circuit while also carrying out a portion of said function of said circuit, said MOS transistor having a conductive gate insulated from a channel region of said MOS transistor by a gate oxide, a thickness of said gate oxide being selected to withstand an electrostatic discharge voltage up to a specified amount, said MOS transistor obviating a need for a separate electrostatic discharge circuit connected to said at least one of said contact pads, a specified input voltage applied to said gate for normal operation of said circuit being less than approximately 1/10 of said electrostatic discharge voltage of said specified amount.

2. The device of Claim 1 further comprising: a package housing said integrated circuit die, said package having external terminals, said terminals being connected to said contact pads of said die via conductors .

3. The device of Claim 2 wherein said gate oxide of said MOS transistor is also a field oxide formed on a substrate of said die for insulating metal lines on said die from said substrate.

4. The device of Claim 2 wherein said gate oxide is approximately 5000 angstroms or greater.

5. The device of Claim 2 wherein said gate oxide is a portion of a field oxide layer over a substrate of said die, wherein said field oxide layer is used as a composite mask for forming various doped regions in said substrate.

6. The device of Claim 2 wherein said circuit is an operational amplifier.

7. The device of Claim 2 wherein said gate of said MOS transistor is directly connected to said at least one of said contact pads, which is, in turn, connected to one of said terminals of said package.

8. The device of Claim 2 wherein said MOS transistor is an N-channel type.

9. The device of Claim 2 wherein said MOS transistor is a P-channel type.

10. The device of Claim 2 wherein said transistor is an enhancement mode type.

11. The device of Claim 2 wherein said transistor is a depletion mode type.

12. The device of Claim 2 wherein said transistor forms part of an amplifier circuit.

13. The device of Claim 12 wherein said transistor forms part of a differential amplifier.

14. The device of Claim 2 wherein said channel region is counterdoped to reduce a threshold voltage of said transistor.

15. The device of Claim 2 wherein said specified input voltage applied to said gate for normal operation of said circuit is approximately 30 volts or less.

16. The device of Claim 2 wherein said specified input voltage applied to said gate for normal operation of said circuit is approximately 5 volts or less.

17. The device of Claim 2 wherein said specified input voltage applied to said gate for normal operation of said circuit is less than approximately 1/100 of said electrostatic discharge voltage of said specified amount .

18. The device of Claim 2 wherein said MOS transistor withstands an electrostatic discharge voltage of at least 500 volts without rupturing said gate oxide .

19. The device of Claim 2 wherein said MOS transistor withstands an electrostatic discharge voltage of at least 1000 volts without rupturing said gate oxide .