CN112701158A - Power device and electronic equipment - Google Patents
Power device and electronic equipment Download PDFInfo
- Publication number
- CN112701158A CN112701158A CN201911006756.6A CN201911006756A CN112701158A CN 112701158 A CN112701158 A CN 112701158A CN 201911006756 A CN201911006756 A CN 201911006756A CN 112701158 A CN112701158 A CN 112701158A
- Authority
- CN
- China
- Prior art keywords
- layer
- diode
- resistor
- metal
- power device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002184 metal Substances 0.000 claims abstract description 80
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 239000010410 layer Substances 0.000 claims description 119
- 239000011229 interlayer Substances 0.000 claims description 13
- 238000002161 passivation Methods 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
Abstract
The invention relates to the electronic field, disclose a power device and electronic device, comprising: a substrate; the device comprises a device layer formed on a substrate, wherein the device layer comprises an on diode, an off diode and a polycrystalline resistor, the on diode and the off diode respectively comprise a cathode, an anode and an N well, and the polycrystalline resistor comprises an on resistor and an off resistor; the metal layer is formed on one side, away from the substrate, of the device layer and comprises a first metal leading-out part, a first connection region, a second connection region and a second metal leading-out part; the first metal leading-out part is electrically connected with the cathode of the turn-on diode and the anode of the turn-off diode; the first connecting area is used for connecting the anode of the switching-on diode and the switching-on resistor; the second connecting area is used for connecting the cathode of the turn-off diode and the turn-off resistor; the second metal lead-out part is used for connecting the on-resistance and the off-resistance, and the grid on-resistance and the off-resistance are integrated into a device chip of the IGBT through a simple circuit, so that the design of a system-level circuit is simplified.
Description
Technical Field
The present invention relates to the field of electronic technologies, and in particular, to a power device and an electronic apparatus.
Background
An Insulated Gate Bipolar Transistor (IGBT) is a composite fully-controlled voltage-driven power Semiconductor device composed of a Bipolar Junction Transistor (BJT) and an Insulated Gate Field Effect Transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), and has a switching speed lower than that of a power MOS but much higher than that of the BJT.
In general, in the application of an IGBT product, a driver IC needs to be matched with appropriate on-resistance and off-resistance to match the on-off characteristics of the IGBT, reduce gate voltage oscillation, and control the IGBT from being turned on by mistake. Usually, the resistor is implemented externally on a circuit board or integrated in a driving IC chip, and is very difficult to control.
Disclosure of Invention
The invention discloses a power device and electronic equipment, which are used for integrating a grid on-resistance loop and a grid off-resistance loop into a device chip of an IGBT (insulated gate bipolar translator) through a simple circuit so as to simplify the design of a system-level circuit.
In order to achieve the purpose, the invention provides the following technical scheme:
in one aspect, the present invention provides a power device comprising:
a substrate;
the device layer is formed on the substrate and comprises an on diode, an off diode and a polycrystalline resistor, the on diode and the off diode respectively comprise a cathode, an anode and an N well, and the polycrystalline resistor comprises an on resistor and an off resistor;
the metal layer is formed on one side, away from the substrate, of the device layer and comprises a first metal leading-out part, a first connection region, a second connection region and a second metal leading-out part, wherein the first metal leading-out part is used for being connected with a grid lead of the power device, and the second metal leading-out part is used for being connected with a grid driving output end of a driving IC; the first metal lead-out part is electrically connected with the cathode of the turn-on diode and the anode of the turn-off diode; the first connecting region is connected with the anode of the switching-on diode and one end of the switching-on resistor; the second connection region is connected with the cathode of the turn-off diode and one end of the turn-off resistor; the second metal lead-out part is connected with the other end of the on-resistance and the other end of the off-resistance.
In the prior art, a resistor is realized through an external circuit board or is integrated in a driving IC chip, but because the characteristics of an adjusting resistor for switching on and off a gate are strongly related to the characteristics of an IGBT device, if the adjusting resistor is integrated in the driving IC chip, the characteristics of the driving IC chip are single, and the applicability is reduced. In the power device provided by the invention, the grid resistance circuit is integrated on the power device chip, so that the peripheral grid resistance circuit does not need to be designed on a circuit board to be matched at an application end. The specific grid resistance circuit comprises an on diode formed on a substrate and an on resistor formed on the substrate, wherein the on resistor is connected in series through a first connecting area in a metal layer to form a first series circuit, an off diode formed on the substrate and an off resistor formed on the substrate are connected in series through a second connecting area in the metal layer to form a second series circuit, two ends of the first series circuit are connected in parallel through a first metal leading-out part and a second metal leading-out part respectively, and the directions of the on diode and the off diode are opposite. When the power device is applied, the first metal leading-out part is connected with a grid electrode lead of the power device, and the second metal leading-out part is connected with a grid electrode driving output end of the driving IC. The power device integrates the on-resistance and the off-resistance in the IGBT, simplifies the circuit of the drive IC and increases the applicability.
Optionally, the substrate includes a first P-type layer and a first N-type layer arranged along a thickness direction of the substrate to form a PN junction; the device layer is formed on one side, away from the first N-type layer, of the first P-type layer.
Optionally, an N-well region is formed in the first P-type layer, and the N-well region is located on a side of the first P-type layer away from the first N-type layer;
the turn-on diode and/or the turn-off diode include a second P-type layer and a second N-type layer formed in the N-well region to form a PN junction.
Optionally, an insulating medium layer is arranged between the metal layer and the device layer, a first contact hole and a second contact hole are formed in the insulating medium layer, and the metal layer penetrates through the first contact hole and is connected with the on diode or the off diode; the metal layer penetrates through the second contact hole and is connected with the connecting end of the polycrystalline resistor.
Optionally, the insulating dielectric layer includes an oxide layer and an interlayer dielectric layer, which are stacked, where the oxide layer is located on one side of the substrate facing the metal layer; the polycrystalline resistor is embedded on one side of the interlayer dielectric medium close to the oxide layer;
the first contact hole penetrates through the oxide layer and the interlayer dielectric layer, and the second contact hole penetrates through the interlayer dielectric layer.
Optionally, the materials of the polycrystalline resistor are all polysilicon materials.
Optionally, the power device further includes a passivation layer covering the metal layer, and the passivation layer is located on a side of the metal layer facing away from the substrate;
in the metal layer, at least part of the first metal leading-out part and the second metal leading-out part are exposed outside the passivation layer.
Optionally, the power device further includes a gate formed on the substrate, and the gate is connected to the first metal lead-out portion.
Optionally, the polycrystalline resistor has an integrated structure, one end of the polycrystalline resistor is formed with a first connection end for connecting with the first connection region, the other end of the polycrystalline resistor is formed with a second connection end for connecting with the second connection region, and a middle part of the polycrystalline resistor is formed with a third connection end for connecting with the second metal lead-out portion, wherein a part of the polycrystalline resistor between the first connection end and the third connection end forms the on-resistor, and a part of the polycrystalline resistor between the second connection end and the third connection end forms the off-resistor.
In another aspect, the present invention further provides an electronic device, including any one of the power devices provided in the above technical solutions.
Drawings
Fig. 1 is a schematic diagram of a simple circuit of a gate matching resistor in a power device according to an embodiment of the present invention;
fig. 2 is a structural plan view of a gate matching resistor structure in a gate region in a power device according to an embodiment of the present invention;
fig. 3 is a schematic plan view of a contact hole of a gate matching resistor structure in a power device according to an embodiment of the present invention;
fig. 4 is a schematic plan view of a metal layer of a gate matching resistance structure in a power device according to an embodiment of the present invention;
FIG. 5 is a cross-sectional view taken along line A-A of FIG. 4;
fig. 6 is a sectional view taken along line B-B in fig. 4.
In the figure: 1-a substrate; 2-turning on a diode; 3-turn off the diode; 4-switching on the resistance; 5-turn off resistance; 6-a metal layer; 7-an oxide layer; 8-an interlayer dielectric layer; 9-a passivation layer; 61-a first metal lead-out; 62-a first connection region; 63-a second attachment zone; 64-second metal lead out.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the prior art, a resistor is realized through an external circuit board or is integrated in a driving IC chip, but because the characteristics of an adjusting resistor for switching on and off a gate are strongly related to the characteristics of an IGBT device, if the adjusting resistor is integrated in the driving IC chip, the characteristics of the driving IC chip are single, and the applicability is reduced. As shown in fig. 1 to 6, an embodiment of the present invention provides a power device, including:
a substrate 1;
the device comprises a device layer formed on a substrate 1, wherein the device layer comprises an on diode 2, an off diode 3 and a polycrystalline resistor, the on diode 2 and the off diode 3 respectively comprise a cathode, an anode and an N well, and the polycrystalline resistor comprises an on resistor 4 and an off resistor 5;
the metal layer 6 is formed on one side of the device layer, which is far away from the substrate 1, and the metal layer 6 comprises a first metal leading-out part 61 used for being connected with a grid lead of the power device, a first connection region 62, a second connection region 63 and a second metal leading-out part 64 used for being connected with a grid driving output end of the driving IC; wherein, the first metal lead-out part 61 is electrically connected with the cathode of the on diode 2 and the anode of the off diode 3; the first connection region 62 is connected to the anode of the turn-on diode 2 and one end of the turn-on resistor 4; the second connection region 63 is connected to the cathode of the turn-off diode 3 and one end of the turn-off resistor 5; the second metal lead-out portion 64 is connected to the other end of the on-resistance 4 and the other end of the off-resistance 5.
In the power device provided by the invention, the grid resistance circuit is integrated on the power device chip, so that the peripheral grid resistance circuit does not need to be designed on a circuit board to be matched at an application end. Specifically, as shown in fig. 1 and 4, the gate resistance circuit includes an on diode 2 formed on a substrate 1 and an on resistor 4 formed on the substrate 1, which are connected in series through a first connection region 62 in a metal layer 6 to form a first series circuit, an off diode 3 formed on the substrate 1 and an off resistor 5 formed on the substrate 1 are connected in series through a second connection region 63 in the metal layer 6 to form a second series circuit, two ends of the first series circuit are connected in parallel through a first metal lead-out portion 61 and a second metal lead-out portion 64, and the directions of the on diode 2 and the off diode 3 are opposite. When the metal lead-out structure is used, the first metal lead-out part 61 is connected with a grid electrode lead of the power device, and the second metal lead-out part 64 is connected with a grid electrode driving output end of the driving IC. The power device integrates the on-resistance 4 and the off-resistance 5 in the IGBT, simplifying the circuit of the driver IC, and increasing its applicability.
Optionally, the power device further includes a gate formed on the substrate 1, and the gate is connected to the first metal lead-out portion 61.
In a specific embodiment, the gate of the power device is electrically connected to the first metal lead 61, the driving IC is electrically connected to the second metal lead 64, and the gate on resistor 4 and the gate off resistor 5 are integrated into the device chip of the IGBT through a simple circuit.
Optionally, the substrate 1 includes a first P-type layer and a first N-type layer arranged along the thickness direction of the substrate 1 to form a PN junction; the device layer is formed on one side of the first P type layer, which is far away from the first N type layer.
In a specific embodiment, the manufacturing process of the substrate 1 is as follows: defining PN junction of terminal ring of power device and P-Well junction of grid region on N type doped monocrystalline silicon wafer by means of photoetching and ion implantation, and making diffusion advance.
Optionally, an insulating medium layer is arranged between the metal layer 6 and the device layer, a first contact hole and a second contact hole are formed in the insulating medium layer, and the metal layer 6 penetrates through the first contact hole and is connected with the turn-on diode 2 or the turn-off diode 3; the metal layer 6 penetrates through the second contact hole and is connected with the connecting end of the polycrystalline resistor.
Optionally, the insulating dielectric layer includes an oxide layer 7 and an interlayer dielectric layer 8, which are stacked, where the oxide layer 7 is located on a side of the substrate 1 facing the metal layer 6; the polycrystalline resistor is embedded on one side of the interlayer dielectric medium close to the oxide layer 7;
the first contact hole penetrates the oxide layer 7 and the interlayer dielectric layer 8, and the second contact hole penetrates the interlayer dielectric layer 8.
Optionally, the materials of the polycrystalline resistor are all polysilicon materials.
Preferably, the polycrystalline resistor has an integrated structure, one end of the polycrystalline resistor is formed with a first connection end for connecting with the first connection region 62, the other end of the polycrystalline resistor is formed with a second connection end for connecting with the second connection region 63, and a third connection end for connecting with the second metal lead-out portion 64 is formed at the middle part of the polycrystalline resistor, wherein a part of the polycrystalline resistor between the first connection end and the third connection end forms an on-resistance 4, and a part of the polycrystalline resistor between the second connection end and the third connection end forms an off-resistance 5.
In a specific embodiment, the process of fabricating the poly resistor on the substrate 1 comprises: a gate oxide layer 7 is grown on the first P-type layer, i.e. P-Well, a polysilicon film is deposited by a Vapor Deposition method (CVD), and a polysilicon gate and a polysilicon resistor structure of the power device are formed by photolithography and etching.
Optionally, an N-well region is formed in the first P-type layer, and the N-well region is located on a side of the first P-type layer away from the first N-type layer;
the on diode 2 and/or the off diode 3 include a second P-type layer and a second N-type layer formed in the N-well region to form a PN junction.
In a specific embodiment, the process of manufacturing the diode on the basis of the substrate 1 comprises:
and forming an N-Well structure in the P-Well of the gate region by photoetching and ion implantation and performing diffusion drive-in. Through photoetching, ion implantation and diffusion, P + and N + are formed in the N-Well, so that two PN junction diodes are formed.
The manufacturing process of forming the metal layer 6 is as follows:
forming a contact hole by photoetching and etching;
and forming electrical interconnections of an on-resistance Rgon, an off-resistance Rgoff and a Diode PN Diode and a Gate Pad Pad metal layer through metal sputtering, photoetching and etching.
Optionally, the power device further includes a passivation layer 8 covering the metal layer 6, and the passivation layer 8 is located on a side of the metal layer 6 away from the substrate 1;
in the metal layer 6, the first metal lead-out portion 61 and the second metal lead-out portion 64 are at least partially exposed outside the passivation layer 8.
In a specific embodiment, the passivation protection layer and PAD window are formed by passivation layer 8 thin film level, lithography and etching.
The power device can be added with the steps of N trap injection, P + injection and the like in the common power device manufacturing process flow to integrate the grid resistance circuit on the power device chip, so that the peripheral grid resistance circuit does not need to be designed on the circuit board at the application end, and the design of a system level circuit is simplified.
Based on the same inventive concept, an embodiment of the present invention further provides an electronic device, which specifically includes any one of the power devices described above.
It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A power device, comprising:
a substrate;
the device layer is formed on the substrate and comprises an on diode, an off diode and a polycrystalline resistor, the on diode and the off diode respectively comprise a cathode, an anode and an N well, and the polycrystalline resistor comprises an on resistor and an off resistor;
the metal layer is formed on one side, away from the substrate, of the device layer and comprises a first metal leading-out part, a first connection region, a second connection region and a second metal leading-out part, wherein the first metal leading-out part is used for being connected with a grid lead of the power device, and the second metal leading-out part is used for being connected with a grid driving output end of a driving IC; the first metal lead-out part is electrically connected with the cathode of the turn-on diode and the anode of the turn-off diode; the first connecting region is connected with the anode of the switching-on diode and one end of the switching-on resistor; the second connection region is connected with the cathode of the turn-off diode and one end of the turn-off resistor; the second metal lead-out part is connected with the other end of the on-resistance and the other end of the off-resistance.
2. The power device of claim 1, wherein the substrate includes a first P-type layer and a first N-type layer aligned in a thickness direction of the substrate to form a PN junction; the device layer is formed on one side, away from the first N-type layer, of the first P-type layer.
3. The power device of claim 2, wherein an N-well region is formed in the first P-type layer and located on a side of the first P-type layer facing away from the first N-type layer;
the turn-on diode and/or the turn-off diode include a second P-type layer and a second N-type layer formed in the N-well region to form a PN junction.
4. The power device according to claim 1, wherein an insulating medium layer is arranged between the metal layer and the device layer, a first contact hole and a second contact hole are arranged on the insulating medium layer, and the metal layer penetrates through the first contact hole and is connected with the on diode or the off diode; the metal layer penetrates through the second contact hole and is connected with the connecting end of the polycrystalline resistor.
5. The power device according to claim 4, wherein the insulating dielectric layer comprises an oxide layer and an interlayer dielectric layer which are stacked, wherein the oxide layer is positioned on one side of the substrate facing the metal layer; the polycrystalline resistor is embedded on one side of the interlayer dielectric medium close to the oxide layer;
the first contact hole penetrates through the oxide layer and the interlayer dielectric layer, and the second contact hole penetrates through the interlayer dielectric layer.
6. The power device of claim 1, wherein the material of the polycrystalline resistor is a polysilicon material.
7. The power device of claim 1, further comprising a passivation layer overlying the metal layer, wherein the passivation layer is located on a side of the metal layer facing away from the substrate;
in the metal layer, at least part of the first metal leading-out part and the second metal leading-out part are exposed outside the passivation layer.
8. The power device of claim 1, further comprising a gate formed on the substrate, the gate being connected to the first metal lead.
9. The power device according to claim 1, wherein the poly resistor has an integrated structure, one end of the poly resistor is formed with a first connection terminal for connecting to the first connection region, the other end of the poly resistor is formed with a second connection terminal for connecting to the second connection region, and a middle portion of the poly resistor is formed with a third connection terminal for connecting to the second metal lead-out portion, wherein a portion of the poly resistor between the first connection terminal and the third connection terminal forms the on-resistance, and a portion of the poly resistor between the second connection terminal and the third connection terminal forms the off-resistance.
10. An electronic device, characterized in that it comprises a power device according to any one of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911006756.6A CN112701158A (en) | 2019-10-22 | 2019-10-22 | Power device and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911006756.6A CN112701158A (en) | 2019-10-22 | 2019-10-22 | Power device and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112701158A true CN112701158A (en) | 2021-04-23 |
Family
ID=75504595
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911006756.6A Pending CN112701158A (en) | 2019-10-22 | 2019-10-22 | Power device and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112701158A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116666380A (en) * | 2023-05-19 | 2023-08-29 | 北京贝茵凯微电子有限公司 | Grid integrated resistor of power device, power device and preparation method of power device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100321092A1 (en) * | 2009-06-18 | 2010-12-23 | Fuji Electric Systems Co. Ltd. | Semiconductor device |
| CN104638021A (en) * | 2015-02-15 | 2015-05-20 | 电子科技大学 | Lateral current regulative diode and manufacturing method thereof |
| US20170062412A1 (en) * | 2015-08-25 | 2017-03-02 | Mitsubishi Electric Corporation | Transistor element and semiconductor device |
| CN109524396A (en) * | 2017-09-20 | 2019-03-26 | 株式会社东芝 | Semiconductor device |
-
2019
- 2019-10-22 CN CN201911006756.6A patent/CN112701158A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100321092A1 (en) * | 2009-06-18 | 2010-12-23 | Fuji Electric Systems Co. Ltd. | Semiconductor device |
| CN104638021A (en) * | 2015-02-15 | 2015-05-20 | 电子科技大学 | Lateral current regulative diode and manufacturing method thereof |
| US20170062412A1 (en) * | 2015-08-25 | 2017-03-02 | Mitsubishi Electric Corporation | Transistor element and semiconductor device |
| CN109524396A (en) * | 2017-09-20 | 2019-03-26 | 株式会社东芝 | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116666380A (en) * | 2023-05-19 | 2023-08-29 | 北京贝茵凯微电子有限公司 | Grid integrated resistor of power device, power device and preparation method of power device |
| CN116666380B (en) * | 2023-05-19 | 2024-03-12 | 北京贝茵凯微电子有限公司 | Grid integrated resistor of power device, power device and preparation method of power device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI443836B (en) | Power device integration on a common substrate | |
| US5602046A (en) | Integrated zener diode protection structures and fabrication methods for DMOS power devices | |
| TWI634620B (en) | Power device integration on a common substrate | |
| US6462382B2 (en) | MOS type semiconductor apparatus | |
| TWI623083B (en) | Power device integration on a common substrate | |
| JP5321768B1 (en) | Semiconductor device | |
| EP1331672B1 (en) | Double diffusion MOSFET | |
| US20150364597A1 (en) | Double-sided vertical semiconductor device with thinned substrate | |
| US20060131685A1 (en) | Semiconductor device and method of fabricating the same | |
| KR20030005385A (en) | Field effect transistor structure and method of manufacture | |
| JP2004055803A (en) | Semiconductor device | |
| KR20010024977A (en) | Monolithically integrated trench mosfet and schottky diode | |
| US6373100B1 (en) | Semiconductor device and method for fabricating the same | |
| US8436419B2 (en) | Semiconductor device with high-breakdown-voltage transistor | |
| JP3173268B2 (en) | Semiconductor device having MIS field-effect transistor | |
| JPH0832031A (en) | Structure of terminating end of high voltage planer and manufacture thereof | |
| US9553085B2 (en) | Fabricating method for high voltage semiconductor power switching device | |
| US11322610B2 (en) | High voltage lateral junction diode device | |
| US5825065A (en) | Low voltage DMOS transistor | |
| JPH07202199A (en) | Active clamping device of integrated structure | |
| US11482615B2 (en) | Super-junction power MOSFET device with improved ruggedness, and method of manufacturing | |
| CN111370479A (en) | Trench gate power device and manufacturing method thereof | |
| CN112701158A (en) | Power device and electronic equipment | |
| JP2000294778A (en) | Semiconductor device | |
| CN116314335A (en) | Manufacturing method of groove type MOSFET device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210423 |
|
| RJ01 | Rejection of invention patent application after publication |