CN116666380B - Grid integrated resistor of power device, power device and preparation method of power device - Google Patents
Grid integrated resistor of power device, power device and preparation method of power device Download PDFInfo
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- CN116666380B CN116666380B CN202310574185.6A CN202310574185A CN116666380B CN 116666380 B CN116666380 B CN 116666380B CN 202310574185 A CN202310574185 A CN 202310574185A CN 116666380 B CN116666380 B CN 116666380B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
- H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
- H01L27/067—Lateral bipolar transistor in combination with diodes, or capacitors, or resistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
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- General Physics & Mathematics (AREA)
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Abstract
The invention discloses a grid integrated resistor of a power device, the power device and a preparation method thereof, which are used for a grid voltage control type power device, wherein the grid integrated resistor comprises: a plurality of resistor units arranged between the grid PAD and the grid bus bar; one end of the resistor unit is connected with the grid PAD, and the other end of the resistor unit is connected with the grid bus bar or suspended through the resistor lead-out electrode; at least one resistor lead-out electrode is connected with the grid bus bar; the resistor lead-out poles are electrically isolated and can be connected through external leads. The power device with the grid integrated resistor with the adjustable resistance value is adopted at the packaging end, and an adjustable built-in integrated resistor network is formed between the grid and the grid bus bar, so that the power device has the advantages of convenience in resistance adjustment, no need of chip design and development, wide applicable frequency range, good current sharing effect and the like.
Description
Technical Field
The invention relates to the technical field of power devices, in particular to a grid integrated resistor of a power device, the power device and a preparation method of the power device.
Background
In high current power modules, the IGBT chip and the FRD chip often need to be packaged together in parallel, e.g., three 200A chips are connected together in parallel to form a 600A chip unit group, as shown. The collector electrode of the IGBT is welded to the same copper foil area on the DBC board; the collector needs to conduct large current, and is welded to the collector copper foil wiring of the DBC plate through a row of dense aluminum wire binding wires; the gate of each IGBT is then led to the gate conductor on the DBC via a thin metal line, which is in turn connected to the gate metal terminal of the module.
Since the gate metal line of the IGBT is generally thin, a certain parasitic inductance is generated, and the thinner and longer the metal line is, the larger the parasitic inductance is, generally, several nH to several tens nH. In addition, due to the difference of placement positions of different parallel chips, a certain gap exists between the distances from the grid electrode to the grid metal terminal finally connected to the module, namely, the grid electrode of each parallel IGBT is connected to the grid terminal of the module through different parasitic inductances, and under the condition of multi-chip parallel connection, the parasitic inductances of the near-end IGBT and the far-end IGBT can even reach a gap of several times. As shown in FIG. 1, after the IGBT module receives the turn-on signal, the parasitic inductance generates a certain voltage division V under the rapid change of current (di/dt) L =l (di/dt). Then the voltage eventually dropped on the gate of the IGBT is V g -V L Due to parasitic power of the near-end IGBT and the far-end IGBTThe sense of the difference is a certain distance, even a distance in multiple levels, that is, V L There is a comparable difference. Eventually drop the voltage V on the gates of the parallel chips g -V L Obvious imbalance occurs, resulting in an out-of-sync opening between the individual chips. Some phenomena such as those described below occur in which some of the chips are already on, and some are not uniform in the current flowing through each of the parallel chips during the turn-on process. The IGBT current sharing problem is very focused in the field of power devices.
As shown in fig. 2, a gate resistor is added in front of each IGBT chip, so that the problem can be solved. At the moment of the turn-on of the IGBT, on each parallel branch, current flows through the inductor, which is nH level, and the gate resistance, which is ohm level. The voltage division across the inductor is negligible compared to the voltage division across the resistor. Thus, the IGBT gate potential of each parallel chip can be made to be substantially uniform.
The prior art has the following two technical routes according to the principle: firstly, a grid resistance method is externally connected nearby outside a chip, and a patch resistor with the same resistance value is welded on a DBC board at the nearby position of a grid of each parallel chip, so that a certain effect can be achieved, but because a certain distance is kept from a grid binding wire point of the chip to a binding wire point of an external resistor, that is, a certain parasitic inductance still exists between the resistor and the grid, the parasitic inductance is not completely solved. Secondly, a grid resistor is integrated in a chip, and the grid resistor is directly integrated in the chip, and the current mainstream method for integrating the grid resistor is to form the grid resistor by utilizing an etching process of a polysilicon deposition layer in the IGBT preparation process, and is mainly integrated near a grid PAD; the method can enable the integrated resistor to be maximally close to the cell region or even the grid electrode of each cell, and can effectively solve the problem of current sharing.
The prior art discloses a polysilicon built-in grid resistor technology; and etching one or more polysilicon areas connected with the gate PAD and the gate bus bar by utilizing a polysilicon deposition process in the IGBT preparation process, wherein the polysilicon areas can be etched into any shape with a certain resistance value. The polysilicon resistor area with a certain resistance value forms a grid integrated resistor Rgint of the IGBT. The scheme has certain limitations: the resistance of the integrated grid resistor in the chip is determined by a process layout, and once the resistance is determined, the resistance cannot be adjusted. If the resistance value needs to be adjusted, the chip layout needs to be modified, then the chip is reflowed, tested and the like, the period is long and the circuit is continuous and complicated, and the modification of one resistance value is basically equivalent to the redevelopment of one chip. And secondly, the integrated grid resistor in the chip is difficult to simultaneously compatible with a large-range application frequency, and the external resistor has limited regulation effect. As shown in fig. 3, in practical applications, the gate resistance needs to be greatly adjusted according to the topology of the application circuit, the application frequency, and the like. Because the charge and discharge time t-RC of the grid electrode is equal to the charge and discharge time t-RC, the value is basically determined because the C of the power device is generated by parasitic internal structure, and the external resistor is generally added on an external circuit and regulated to adapt to the switching application of various frequencies. It is possible to create the following scenario: for example, two groups of IGBT chips and FRD chips are connected in parallel in an IGBT module of a certain specification, the integrated gate resistance of the IGBT is 15 ohms, the external resistance is 20 ohms, and the IGBT module is suitable for 15kHz application; the IGBT of this specification is now applied to an application circuit of some 30 kHz. Even if the 20 ohm external resistor is completely removed, the switching speed is slow, so that the high-frequency circuit application is difficult to meet. Because the on-chip integrated gate resistance has been determined, there has been no way to continue to decrease. Conversely, if the resistance of the gate resistor of the internal integration is low only to satisfy the high-frequency application, the current sharing problem caused by the internal parasitic inductance may also occur in some low-frequency high-current application scenarios. And thirdly, the grid resistance is externally arranged, so that the grid can be connected with the resistor at the DBC position nearby the chip in the packaging process of the power module, but parasitic inductance generated by connection from the grid to the external resistor cannot be effectively avoided.
Disclosure of Invention
The embodiment of the invention aims to provide a grid integrated resistor of a power device, the power device and a preparation method thereof, wherein an adjustable built-in integrated resistor network is formed between a grid and a grid bus bar by adopting the power device with the grid integrated resistor with an adjustable resistance value at a packaging end, and the power device has the advantages of convenience in resistance adjustment, no need of chip design and development, wide applicable frequency range, good current sharing effect and the like.
To solve the above technical problem, a first aspect of an embodiment of the present invention provides a gate integrated resistor of a power device, for a gate voltage controlled power device, where the gate integrated resistor includes: a plurality of resistor units arranged between the grid PAD and the grid bus bar;
one end of the resistor unit is connected with the grid PAD, and the other end of the resistor unit is connected with the grid bus bar or suspended by a resistor lead-out electrode;
at least one of the resistor extraction electrodes is connected with the grid bus bar;
the resistor leading-out poles are electrically isolated and can be connected through external wires.
Further, the resistor lead-out electrode is correspondingly connected with at least one resistor unit;
at least one resistance leading-out electrode is connected with the grid bus bar, and the rest resistance leading-out electrodes are arranged in a suspending manner and can be connected with each other through external leads.
Further, a plurality of the resistor leading-out poles are correspondingly connected with the resistor units;
the other resistance lead-out electrode is only connected with the grid bus bar, and the resistance lead-out electrode only connected with the grid bus bar can be connected with the other resistance lead-out electrodes through an external lead.
Further, the resistor unit is a polysilicon resistor obtained by etching a polysilicon layer below the metal layers of the resistor leading-out electrode and the grid electrode;
an oxide layer for isolation is arranged between the polysilicon resistor and the resistor lead-out electrode metal layer;
and two ends of the polysilicon resistor are respectively connected with the grid electrode and the resistor leading-out electrode through holes.
Further, the resistance value of the gate resistor of the power device is a resistance value of the parallel connection of the resistor unit directly connected with the gate bus bar and/or indirectly connected with the gate bus bar via the external lead:
1/Rgint＝(1/R1)+……+(1/Rn)；
wherein Rgint is the resistance of the grid resistor, and R1-Rn are the resistances of n resistor units directly or indirectly connected with the grid.
Further, the resistor unit and the corresponding resistor lead-out electrode are arranged on at least one side of the grid electrode.
Further, the external lead is one of an aluminum wire, a copper wire, a silver wire, a gold wire or an alloy lead.
Accordingly, a second aspect of the embodiments of the present invention provides a power device, including any one of the above-mentioned power device gate integration resistors.
Accordingly, a third aspect of the embodiments of the present invention provides a method for manufacturing a power device, which is used for manufacturing the power device, including the following steps:
forming an oxide layer in the gate region on the surface of the silicon to isolate the substrate and serve as a gate oxide layer;
depositing a layer of in-situ doped polysilicon material, and tiling on the surface of the substrate;
etching the surface polysilicon material through an etching process to form electrical isolation between the grid polysilicon and the bus bar polysilicon;
depositing an oxide layer on the polysilicon layer to serve as an insulating passivation layer;
opening holes in the polysilicon of the gate region and the polysilicon extending to the resistor region for connection with the metal layer;
depositing a layer of metal on the surface of the gate region in a sputtering or vapor deposition mode, and connecting the polysilicon of the gate region and the polysilicon of the resistor electrode region through the through hole;
etching metal to form electric isolation of a grid PAD and a resistor lead-out electrode, wherein the grid PAD is connected with the resistor lead-out electrode through a resistor Rn, and at least one resistor lead-out electrode is connected with a grid bus bar and extends to each cell of an active region.
Accordingly, a fourth aspect of the embodiments of the present invention provides a method for manufacturing a power device, which is used for manufacturing the power device, including the following steps:
etching a groove distribution in a grid region on the surface of silicon;
forming a compact oxide layer serving as gate oxide on the surfaces of the groove and the silicon through an oxidation process;
depositing a layer of in-situ doped polysilicon material, and filling the trench to form a grid in a primitive cell;
removing the surface polysilicon material through an etching process or a grinding process to form mutually independent trench gates;
depositing an oxide layer on the surface of the grid electrode to serve as an insulating passivation layer;
opening holes in the polysilicon trench of the gate region and the polysilicon trench extending to the resistor lead-out region for connection with the metal layer;
depositing a layer of metal on the surface of the gate region in a sputtering or vapor plating mode, and connecting the polysilicon of the gate region and the polysilicon of the resistor lead-out region through the through hole;
etching metal to form electric isolation of a grid PAD and a resistor leading-out area, wherein the grid PAD and the resistor leading-out area are respectively connected through a plurality of resistor units, the resistor leading-out area is connected with a grid bus bar, and the resistor leading-out area extends to each cell of an active area.
The technical scheme provided by the embodiment of the invention has the following beneficial technical effects:
the power device with the grid integrated resistor with the adjustable resistance value is adopted at the packaging end, and an adjustable built-in integrated resistor network is formed between the grid and the grid bus bar, so that the power device has the advantages of convenience in resistance adjustment, no need of chip design and development, wide applicable frequency range, good current sharing effect and the like.
Drawings
FIG. 1 is a schematic diagram of a conventional chip set circuit;
FIG. 2 is a schematic diagram of a prior art parallel current sharing solution;
FIG. 3 is a schematic diagram of the solution of FIG. 2 with resistors added to adjust frequency;
FIG. 4 is a schematic diagram of a power device gate integrated resistor according to an embodiment of the present invention;
FIG. 5 is a second schematic diagram of a power device gate integrated resistor according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a parallel circuit of resistor units according to an embodiment of the present invention;
fig. 7a is a schematic diagram of a parallel resistor of stripe or polysilicon according to an embodiment of the present invention;
FIG. 7b is a schematic diagram of an S-type polysilicon resistor according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a TPAD provided by an embodiment of the present invention;
FIG. 9 is a schematic diagram of a cut-plane of a grid integrated resistor of a power device according to an embodiment of the present invention;
fig. 10 is a schematic diagram of a polysilicon bus bar layout of a first power device manufacturing method according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of a metal bus layout of a first power device manufacturing method according to an embodiment of the present invention;
fig. 12 is a schematic diagram of a polysilicon bus bar layout of a second method for manufacturing a power device according to an embodiment of the present invention.
Fig. 13 is a schematic diagram of a metal bus bar layout of a second method for manufacturing a power device according to an embodiment of the present invention.
Detailed Description
The objects, technical solutions and advantages of the present invention will become more apparent by the following detailed description of the present invention with reference to the accompanying drawings. It should be understood that the description is only illustrative and is not intended to limit the scope of the invention. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the present invention.
Referring to fig. 4 and 5, a first aspect of an embodiment of the present invention provides a gate integrated resistor of a power device, for a gate voltage controlled power device, the gate integrated resistor includes: a plurality of resistor units arranged between the grid PAD and the grid bus bar; one end of the resistor unit is connected with the grid PAD, and the other end of the resistor unit is connected with the grid bus bar or suspended through the resistor lead-out electrode; at least one resistor lead-out electrode is connected with the grid bus bar; the resistor lead-out poles are electrically isolated and can be connected through external leads.
Referring to fig. 4, in an exemplary embodiment of the present invention, a resistor lead-out electrode is correspondingly connected to at least one resistor unit; at least one resistor lead-out electrode is connected with the grid bus bar, and other resistor lead-out electrodes are suspended and can be connected with each other through external leads.
Specifically, a plurality of resistor lead-out poles are designed between the grid PAD and the grid bus bar and are represented by R1-Rn, the resistor lead-out poles surround the periphery of the grid, and each resistor lead-out pole represents an integrated resistor in a chip. The gate metal layer and the metal layer of each resistor lead-out electrode are isolated from each other through an etching process. One of the resistor lead-out poles is connected with the grid bus bar, the corresponding resistance value is used as a basic integrated resistor, and the other resistor lead-out poles are electrically isolated. The resistor formed by etching the polysilicon layer is arranged below each resistor leading-out electrode and the metal layer of the grid, an oxide layer is arranged between the polysilicon resistor layer and the electrode metal layer for isolation, the two ends of the polysilicon resistor are connected with the resistor leading-out electrode and the G electrode in a through hole mode, each resistor leading-out electrode forms a built-in grid resistor Rn connected with the grid, and the resistance can be any value according to design requirements.
Mode of adjusting gate Rgint integration resistance: in the step of packaging the power module, any two or more resistor lead-out poles are short-circuited in a binding metal wire mode. A series of power modules with different rgints can be packaged by the same chip according to the requirements of clients, application requirements, frequency requirements and the like.
Referring to fig. 5, in another implementation of the embodiment of the present invention, a plurality of resistor lead-out electrodes (rpad) are correspondingly connected to the resistor units; the other resistor lead-out electrode (TPAD) is only connected with the grid bus bar, and the resistor lead-out electrode only connected with the grid bus bar can be connected with other resistor lead-out electrodes through an external lead.
The TPAD and RPAD surround the form near the grid. The characteristics of the R PAD are the same as described above. The TPAD is only connected with the bus bar, and the integrated grid resistor is not arranged below the metal layer, and is only used as a metal wire connection island in the packaging process, so that the adjustable integrated resistor range of the chip is larger.
Specifically, the resistor unit is a polysilicon resistor which is obtained by etching a polysilicon layer under the metal layers of the resistor leading-out electrode and the grid electrode; an oxide layer for isolation is arranged between the polysilicon resistor and the resistor lead-out electrode metal layer; the two ends of the polysilicon resistor are respectively connected with the grid electrode and the resistor leading-out electrode through the through holes.
Further, the resistance value of the gate resistor of the power device is a resistance value of parallel connection of a resistor unit directly connected with the gate bus bar and/or indirectly connected with the gate bus bar through an external wire:
1/Rgint＝(1/R1)+……+(1/Rn)；
wherein Rgint is the resistance of the grid resistor, and R1-Rn are the resistances of n resistor units directly or indirectly connected with the grid.
In the two specific embodiments, the principle is that an adjustable and variable built-in integrated resistor network is formed between a grid electrode and a grid electrode BUS bar, as shown in fig. 6, a plurality of resistors with parallel connection relationship are arranged between a G PAD (grid electrode) and a G BUS (grid electrode BUS bar), and the resistance values are R1-Rn. Each resistor is connected to a gate PAD, but at most one R is connected to a gate bus bar (in the mode where tsad is present, no R PAD is connected to the bus bar), such as R1. If the R1 PAD is connected with the R2 PAD in the process of chip packaging wire bonding, the grid integrated resistance at the moment is determined by the following formula: 1/rgint= (1/R1) + (1/R2); similarly, according to the principle, the number of n+ (n-1) + (n-2) + … +1 Rgint, n is R PAD, can be regulated by a simple packaging layer wire bonding mode. The R electrode connected to the gate bus bar may be any one.
Referring to fig. 7a and 7b, the resistances of each R-pole may be the same or may be set to any resistance value independently of each other. The resistance value determining formula is rn=rs= (L/W) = (ρ/d) = (L/W), wherein Rs is the sheet resistance of the resistive material, ρ is the polysilicon resistivity, d is the polysilicon thickness, L is the length of the resistive material, W is the width of the resistive material, and when a plurality of resistive materials are connected in parallel, the width w=w1+w2+ … +wn, wherein wn is the width of any resistive material. According to the principle, the resistance value of the polysilicon resistor can be formed into various polysilicon patterns through the layout and the process of the IGBT preparation process. Through a resistance formula, the strip-shaped polycrystal is connected in parallel, and W is increased to form a smaller integrated resistance (shown in FIG. 7 a); since Rs is inversely proportional to the thickness d of the material layer, the poly-parallel connection of the trench gate can form a smaller integrated resistance; the high-resistance integrated resistor can also be formed by a method of decreasing the width or increasing the length (as shown in fig. 7 b).
Specifically, the bonding wire (bonding) on the surface of the chip in the packaging process can be various metal and alloy materials such as aluminum wires, copper wires, silver wires, gold wires and the like. According to the surface metal of the chip, packaging difference and the like. And flexible wiring is performed between the grid electrodes T PAD and R PAD, so that the grid electrode integrated resistor is flexible and adjustable at the packaging side, and a plurality of integrated resistors can be formed. If r1=30Ω, r2=15Ω, r3=10Ω, the tsad can be connected with any one of R1, R2, R3 by a metal wire to form a 10-30Ω resistor; or connecting the T PAD with any two R PADs to form Rgint of 6-10Ω; t PAD can also be connected with 3R PADs to form a Rgint of 5Ω, since the number of R PADs can be extended to Rn, theoretically any value from 0 to Rmax (the maximum value in Rn). Binding wires between the T PAD and the R PAD do not affect the grid and emitter routing of the chip.
In addition, referring to fig. 8, in another embodiment, a T PAD connected only to the gate Bus (G Bus) may be provided, where no integrated resistor is under the metal layer of the T PAD, and is not connected to the G PAD, and is not connected to any R PAD. The real-time mode in FIG. 8 is the T PAD layout mode in FIG. 5 for realizing Rg from 0 to Rmax; when rg=0, only T PAD needs to be directly connected with G PAD by wire bonding.
In addition, for the case of fig. 4, R1 PAD may be directly connected to the G PAD wire to implement rg=0, and although there is a polysilicon resistor layout under R1, rg is 0 between R1 PAD and G PAD through metal wire short circuit (fig. 8 shows a manner of implementing rg=0 by wire connection in the case of the layout of fig. 4).
Referring to fig. 9,R, the electrode 0 and the gate bus bar can be connected by a polysilicon layer under the metal layer or by the metal layer. The forming material of the resistor R is polysilicon, and the polysilicon arrangement can be as follows: the substrate is tiled on the surface of the substrate (first power device manufacturing method) and deposited in the groove (second power device manufacturing method). And (3) taking A-A' as an axis to look at different connection methods of two polysilicon resistor arrangement modes.
Further, the resistor unit and the corresponding resistor lead-out electrode are arranged on at least one side of the grid electrode.
Accordingly, a second aspect of the embodiments of the present invention provides a power device, including any one of the above-mentioned power device gate integration resistors.
Accordingly, referring to fig. 10 and 11, a third aspect of the embodiment of the present invention provides a method for manufacturing a power device, which is used for manufacturing the power device, and includes the following steps:
in step S110, an oxide layer is formed on the gate region of the silicon surface to isolate the substrate and serve as a gate oxide layer.
Step S120, a layer of in-situ doped polysilicon material is deposited and tiled on the surface of the substrate.
In step S130, the surface polysilicon material is etched by an etching process, electrical isolation is formed between the gate polysilicon and the bus bar polysilicon, and the polysilicon layer can be etched to form various patterns according to the resistance requirement.
And step S140, depositing an oxide layer on the polysilicon layer to serve as an insulating passivation layer to protect the formed grid polysilicon resistor and the polysilicon bus bar.
In step S150, openings are formed in the polysilicon of the gate region and the polysilicon extending to the resistor region for connection to the metal layer.
In step S160, a layer of metal is deposited on the surface of the gate region in the form of sputtering or vapor deposition, and the polysilicon connected to the gate region through the via hole and the polysilicon of the resistive electrode region are deposited.
Step S170, etching metal to form electrical isolation between the gate PAD and the resistor extraction electrode, where the gate PAD and the resistor extraction electrode are connected by a resistor Rn, and at least one resistor extraction electrode is connected to a gate bus bar (polysilicon bus bar is shown in fig. 10 and metal bus bar is shown in fig. 11) and extends to each cell of the active region.
Accordingly, referring to fig. 12 and 13, a fourth aspect of the present invention provides a method for manufacturing a power device, which includes the following steps:
in step S210, a trench distribution is etched in the gate region of the silicon surface.
In step S220, a dense oxide layer is formed on the trench and the silicon surface as gate oxide by oxidation process.
In step S230, a layer of in-situ doped polysilicon material is deposited and fills the trench to form a gate in the primitive cell.
And step S240, removing the surface polysilicon material through an etching process or a grinding process to form mutually independent trench gates.
In step S250, an oxide layer is deposited on the surface of the gate electrode as an insulating passivation layer.
In step S260, holes are opened in the polysilicon trench of the gate region and the polysilicon trench extending to the resistor lead-out region for connection with the metal layer.
In step S270, a layer of metal is deposited on the surface of the gate region in the form of sputtering or vapor deposition, and the polysilicon connected to the gate region through the via hole and the polysilicon of the resistor lead-out region are deposited.
In step S280, metal is etched to form electrical isolation between the gate PAD and the resistor lead-out area, which are connected through a plurality of resistor units, respectively, and the resistor lead-out area is connected to the gate bus bar (polysilicon bus bar is shown in fig. 12, and metal bus bar is shown in fig. 13) and extends to each cell of the active area.
The embodiment of the invention aims to protect a grid integrated resistor of a power device, the power device and a preparation method thereof, and the grid integrated resistor is used for a grid voltage control type power device and comprises the following components: a plurality of resistor units arranged between the grid PAD and the grid bus bar; one end of the resistor unit is connected with the grid PAD, and the other end of the resistor unit is connected with the grid bus bar or suspended through the resistor lead-out electrode; at least one resistor lead-out electrode is connected with the grid bus bar; the resistor lead-out poles are electrically isolated and can be connected through external leads. The technical scheme has the following effects:
1. a power device chip can be used for realizing a wide-range built-in adjustable integrated resistor Rgint, and the adjustment setting from 0 to thousands of ohms can be easily realized;
2. the grid integrated resistor adjusting mode is simple and easy to implement, and can be completed only by adding a plurality of metal binding wires in the packaging and routing process of the chip;
3. the power device can be applied to a wide frequency range from low frequency to high frequency;
4. narrow applicability of a single integrated resistor chip is avoided, great complexity of a development process and a long development period are avoided, and development efficiency of the power device chip is greatly improved;
5. the method is suitable for various parallel situations (such as multi-chip parallel connection and multi-module parallel connection), and the value of Rgint can be set according to the size of parasitic inductance, so that the influence of the parasitic inductance di/dt is negligible when the IGBT is switched, and a very good parallel current sharing effect is realized;
6. the current equalizing effect is good, and the reliability is high in the parallel application working condition;
7. in the chip test link, the Rgint can be flexibly regulated to enable the chip to exert the maximum effect.
It is to be understood that the above-described embodiments of the present invention are merely illustrative of or explanation of the principles of the present invention and are in no way limiting of the invention. Accordingly, any modification, equivalent replacement, improvement, etc. made without departing from the spirit and scope of the present invention should be included in the scope of the present invention. Furthermore, the appended claims are intended to cover all such changes and modifications that fall within the scope and boundary of the appended claims, or equivalents of such scope and boundary.
Claims (9)
1. A gate integrated resistor for a power device, the gate integrated resistor comprising: a plurality of resistor units arranged between the grid PAD and the grid bus bar; one end of the resistor unit is connected with the grid PAD, and the other end of the resistor unit is connected with the grid bus bar or suspended by a resistor lead-out electrode; at least one of the resistor extraction electrodes is connected with the grid bus bar; the resistor lead-out poles are electrically isolated and can be connected through external leads;
the resistor unit is a polysilicon resistor which is obtained by etching a polysilicon layer under the metal layers of the resistor leading-out electrode and the grid electrode;
an oxide layer for isolation is arranged between the polysilicon resistor and the resistor lead-out electrode metal layer;
and two ends of the polysilicon resistor are respectively connected with the grid electrode and the resistor leading-out electrode through holes.
2. The power device gate integrated resistor of claim 1,
the resistor lead-out electrode is correspondingly connected with at least one resistor unit; at least one resistance leading-out electrode is connected with the grid bus bar, and the rest resistance leading-out electrodes are arranged in a suspending manner and can be connected with each other through external leads.
3. The power device gate integrated resistor of claim 1,
the resistor lead-out poles are correspondingly connected with the resistor units; the other resistance lead-out electrode is only connected with the grid bus bar, and the resistance lead-out electrode only connected with the grid bus bar can be connected with the other resistance lead-out electrodes through an external lead.
4. A power device gate integrated resistor according to any of claims 1-3, wherein the power device gate resistor has a resistance value of a parallel connection of the resistor unit directly connected to the gate bus bar and/or indirectly connected to the gate bus bar via the external lead:
1/Rgint＝(1/R1)+……+(1/Rn)；
wherein Rgint is the resistance of the grid resistor, and R1-Rn are the resistances of n resistor units directly or indirectly connected with the grid.
5. A power device gate integrated resistor according to any of claims 1-3, wherein the resistor unit and the corresponding resistor lead-out electrode are arranged on at least one side of the gate.
6. The power device gate integrated resistor of any of claims 1-3, wherein the external wire is one of an aluminum wire, a copper wire, a silver wire, a gold wire, or an alloy wire.
7. A power device comprising a power device gate integrated resistor as claimed in any one of claims 1 to 6.
8. A method of manufacturing a power device according to claim 7, comprising the steps of:
forming an oxide layer in the gate region on the surface of the silicon to isolate the substrate and serve as a gate oxide layer;
depositing a layer of in-situ doped polysilicon material, and tiling on the surface of the substrate; etching the surface polysilicon material through an etching process to form electrical isolation between the grid polysilicon and the bus bar polysilicon;
depositing an oxide layer on the polysilicon layer to serve as an insulating passivation layer;
opening holes in the polysilicon of the gate region and the polysilicon extending to the resistor region for connection with the metal layer;
depositing a layer of metal on the surface of the gate region in a sputtering or vapor deposition mode, and connecting the polysilicon of the gate region and the polysilicon of the resistor electrode region through the through hole;
etching metal to form electric isolation of a grid PAD and a resistor lead-out electrode, wherein the grid PAD is connected with the resistor lead-out electrode through a resistor Rn, and at least one resistor lead-out electrode is connected with a grid bus bar and extends to each cell of an active region.
9. A method of manufacturing a power device according to claim 7, comprising the steps of:
etching a groove distribution in a grid region on the surface of silicon;
forming a compact oxide layer serving as gate oxide on the surfaces of the groove and the silicon through an oxidation process;
depositing a layer of in-situ doped polysilicon material, and filling the trench to form a grid in a primitive cell; removing the surface polysilicon material through an etching process or a grinding process to form mutually independent trench gates;
depositing an oxide layer on the surface of the grid electrode to serve as an insulating passivation layer;
opening holes in the polysilicon trench of the gate region and the polysilicon trench extending to the resistor lead-out region for connection with the metal layer;
depositing a layer of metal on the surface of the gate region in a sputtering or vapor plating mode, and connecting the polysilicon of the gate region and the polysilicon of the resistor lead-out region through the through hole;
etching metal to form electric isolation of a grid PAD and a resistor leading-out area, wherein the grid PAD and the resistor leading-out area are respectively connected through a plurality of resistor units, the resistor leading-out area is connected with a grid bus bar, and the resistor leading-out area extends to each cell of an active area.
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|---|---|---|---|---|
| CN102842606A (en) * | 2012-08-24 | 2012-12-26 | 中国电力科学研究院 | Variable grid internal resistance for IGBT (Insulated Gate Bipolar Transistor) chip and design method thereof |
| CN112701158A (en) * | 2019-10-22 | 2021-04-23 | 珠海格力电器股份有限公司 | Power device and electronic equipment |
| CN113035701A (en) * | 2021-03-12 | 2021-06-25 | 重庆万国半导体科技有限公司 | Grid resistance adjustable super junction power device and manufacturing method thereof |
| CN115639406A (en) * | 2022-09-30 | 2023-01-24 | 华中科技大学 | Multi-gear resistor load cabinet switching circuit design method and system based on list method |
| CN116053260A (en) * | 2022-12-19 | 2023-05-02 | 深圳市创芯微微电子有限公司 | Power device integrated with grid resistor and manufacturing method thereof |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102842606A (en) * | 2012-08-24 | 2012-12-26 | 中国电力科学研究院 | Variable grid internal resistance for IGBT (Insulated Gate Bipolar Transistor) chip and design method thereof |
| CN112701158A (en) * | 2019-10-22 | 2021-04-23 | 珠海格力电器股份有限公司 | Power device and electronic equipment |
| CN113035701A (en) * | 2021-03-12 | 2021-06-25 | 重庆万国半导体科技有限公司 | Grid resistance adjustable super junction power device and manufacturing method thereof |
| CN115639406A (en) * | 2022-09-30 | 2023-01-24 | 华中科技大学 | Multi-gear resistor load cabinet switching circuit design method and system based on list method |
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