WO1999003046A1 - Plate-forme polyvalente de calcul, de commutation et de commande - Google Patents

Plate-forme polyvalente de calcul, de commutation et de commande Download PDF

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Publication number
WO1999003046A1
WO1999003046A1 PCT/CN1998/000116 CN9800116W WO9903046A1 WO 1999003046 A1 WO1999003046 A1 WO 1999003046A1 CN 9800116 W CN9800116 W CN 9800116W WO 9903046 A1 WO9903046 A1 WO 9903046A1
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WO
WIPO (PCT)
Prior art keywords
port
dual
computing
control
port ram
Prior art date
Application number
PCT/CN1998/000116
Other languages
English (en)
Chinese (zh)
Inventor
Dixing Wang
Original Assignee
Dixing Wang
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dixing Wang filed Critical Dixing Wang
Priority to AU81007/98A priority Critical patent/AU8100798A/en
Publication of WO1999003046A1 publication Critical patent/WO1999003046A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)

Definitions

  • the present invention belongs to the technical field of data processing, and specifically relates to a multi-purpose intelligent platform that can be widely used in the fields of control, data processing, communication exchange, and computer network. Background of the invention
  • the computer representing the cutting-edge technology of data processing has followed the architecture of the von Neumann machine since its advent in the 1940s. Its main features are: first, program memory and serial processing; second, storage address and storage content are separated ; Third, only passive execution of certain procedures. Over the past 50 years, despite the rapid development of computer technology, people are more and more deeply aware of the limitations brought by traditional computer architecture.
  • Feng-type computer works according to the address mode, and there is no internal connection between computers, that is, there is no self-organization. Between computers, whether it is task assignment or real-time communication, it is a difficult problem to solve, and it only faces one information source in essence. Therefore, it is necessary to create a mechanism to allow as many peripherals as there are to directly face the environment and receive and process information synchronously.
  • the purpose of the present invention is to break through the framework of serial work, address operation and programmed operation mode, and provide a method based on the principle of self-organization, which realizes the synchronization of reading and writing calculations, can be open to parallel reading and writing calculations, and has transparent subsystems.
  • a multi-purpose intelligent platform that is functionally coupled and capable of serial-parallel adaptive interaction.
  • a further object of the present invention is to provide a multi-purpose intelligent platform with multi-valued states, unified modulus, scalable system structure and functions in combination with the logic reversible arithmetic unit with multi-valued states.
  • the present invention is a computing, switching, and controlling multi-purpose platform, which is composed of data, address, command bus and bus control, command register, six peripheral interfaces and dual-port RAM, wherein the command register, peripheral interface and bus control are linked to On the said bus, there are two-way input and output data ports and read-write control connections between these peripheral interfaces and a port of the dual-port RAM; a logical reversible arithmetic unit with three ports, each of which has an input ports and output ports, the three input ports of the logic reversible arithmetic unit are respectively connected with the output of the other port of the dual-port RAM through a one-to-two selector circuit, and the three output ports are respectively connected with the output port of the other port through a one-to-two divider.
  • the input of the other port of the dual-port RAM is connected in pairs;
  • the registers have read and write control respectively to the dual-port RAM, and direction selection control respectively to the two-choice circuit and the one-two distributor.
  • one logical reversible arithmetic unit, six peripheral interfaces and dual-port RAM can be expanded correspondingly, and the command register can correspondingly expand the word length or increase the number of control stages.
  • the logic reversible operator can be composed of one adder and two subtractors.
  • the above-mentioned adder and subtractor can be adder and subtractor bit slices with multi-valued states, which can be cascaded with multiple bits or expand the value range of a bit slice by splicing.
  • the present invention is a computing, switching, and controlling multi-purpose platform, which is composed of data, address, command bus and bus control, command register, three peripheral interfaces and dual-port RAM, wherein the command register, peripheral interface and bus control are linked to On the said bus, there are two-way input and output data ports and read-write control between these peripheral interfaces and one port of the dual-port RAM.
  • the ports are respectively connected to the other port of the dual-port RAM, and the command register has read and write control respectively to the dual-port RAM.
  • the logic reversible operator can be composed of one adder and two subtractors.
  • the above-mentioned adder and subtractor can be adder and subtractor bit slices with multi-value states, and can be multi-bit cascaded or spliced to expand the value range of a bit slice.
  • Fig. 1 is the schematic diagram of circuit principle of the present invention
  • Fig. 2 is a schematic diagram of the parallel processing principle of the present invention.
  • Fig. 3 is a schematic connection diagram of an embodiment of the logical reversible operator of the present invention. Modes of Carrying Out the Invention
  • the present invention is based on a logic reversible arithmetic unit 1 as the core, and is composed of a two-select-one circuit 2, a one-two distributor 3, a dual-port RAM 4, a command register 6, a bus control 10, and a peripheral interface 5. .
  • the command register 6, the peripheral interface 5 and the bus control 10 are all hung on the three buses 11 composed of data, address and control lines.
  • the peripheral interface 5 and one port of the dual-port RAM 4 are connected to the read-write control 9 through a two-way input and output data port, and the outputs of the other port of the dual-port RAM 4 are respectively connected in pairs to the input terminals of the two-select-one circuit 2 , and its input is connected to the output end of the one-two divider 3 respectively.
  • the three input ports of the logical reversible operator 1 are respectively connected to the output terminals of the one-two selecting one circuit 2, and the three output ports are respectively connected to the input terminals of the one-one-two distributor 3.
  • the command register 6 is connected with the read-write control 8 and the dual-port RAM 4 to realize the read-write control for the arithmetic unit, and the direction selection control 7 is connected with the two-to-one circuit 2 and the one-to-two distributor 3 to realize the two-to-one circuit 2 1.
  • the logic control of the one-two distributor 3 changes the one-way input and output facing the logical reversible operator 1 into the two-way input and output facing the dual-port RAM 4, so that the multi-purpose intelligent platform of the present invention can realize serial parallel reading and writing, reading and writing, Serial-parallel switching, serial-parallel computing, serial-parallel control, and real-time bidirectional reading and writing, real-time bidirectional switching, real-time parallel computing, and real-time bidirectional control.
  • A1(A3) and A2 are port A
  • B1(B2) and B3 are port B
  • C2(C3) and C1 are port C
  • three ports can enter at the same time, and three ports can exit at the same time, which can reverse logical reasoning and operation.
  • the logical reversible arithmetic unit 1, the peripheral interface 5 and the dual-port RAM 4 can be extended in a corresponding relationship, and the command register can correspondingly expand the word length or increase the number of control stages, so that the present invention can be used in the command register Under the control of read-write control 8, parallel operation, exchange and control can be completed.
  • the parallel reading and writing of the dual-port RAM 4 of each port is the same signal as the address strobe, and the parallel reading and writing signals, It reads and writes the corresponding dual-port RAM 4 in units of bits through the command register 6 (this correspondence is programmable, and can also be fixed, of course). Because parallel reading and writing can only operate on address 0 of each dual-port RAM, each dual-port RAM is equipped with an address generator, which pushes out data when reading and pushes data in when writing. The data exchange between host computer and terminal computer, terminal computer and terminal computer determines its communication protocol through dual-port RAM, and this protocol has parallelism.
  • each dual-port RAM has another meaning, that is, when the dual-port RAM of each port reads and writes at the same time, the process of exchange and operation is implied, that is, while completing two-way reading and writing, it also completes two-way Exchange and operation, that is, read, write and calculate are completed synchronously.
  • Each terminal machine of the multi-purpose intelligent platform of the present invention can share the command register 6 through the bus, and read and write the dual-port RAM 4 of each port in parallel.
  • the bus control 10 decides according to the principle of priority application.
  • the command word in the command register 6 determines which dual-port RAMs are to be read or written, and the reading and writing of each dual-port RAM and the corresponding calculation, exchange, and control functions are all completed in one clock cycle by one command.
  • each peripheral interface is connected to group-in and group-out equipment or calling and called users; in the case of control, each peripheral interface is connected to sensors or actuators.
  • ports A and C can switch or control bidirectionally
  • ports A and B can switch or control bidirectionally.
  • the multi-purpose intelligent platform of the present invention can select two functional modes of calculation and exchange through mode switching; through serial and parallel read and write control, two modes of exchange and calculation can be selected in serial and parallel mode; through mode switching, there are two modes of fixed host and multi-host Mode is optional.
  • the host serial read-write mode and parallel read-write mode are optional, and the host participates in exchange and calculation, and does not participate but only performs setting control. Two modes are optional.
  • the key point is that the host computer and the terminal computer can share the command register, and read and write the dual-port RAM of each port in parallel. As for which terminal function can be read and written in parallel, it is allocated by the bus control 10.
  • the above-mentioned multi-purpose intelligent platform has functions such as multi-value calculation, exchange, selection and setting of multiple base codes, mutual causality control, and the like. It has a multi-valued state, which is suitable for operation, processing and exchange of various base codes, such as 8, 16 to 32, 64 ... base codes. It is open, and can be cascaded and spliced on the basis of arithmetic unit bit slices at will. Specifically, it can be cascaded at the slice level in units of bits, and can be cascaded in units of slices at the board level as needed. And no matter how cascaded, there is no problem of carry-borrow accumulation delay time.
  • the above-mentioned multi-purpose intelligent platform has the characteristics of unified module and integrated storage and calculation, and can perform non-programmed data processing and control in real time. It has the characteristics of unified address and data ports, and integrated operation and exchange functions, which can realize mutual causality control.
  • the parameters of each port of the system can be dynamically defined interactively and complementarily defined, thus reflecting the self-organization and mutual causality of the system.
  • Fengji and its arithmetic unit it solves the problem of multi-value state and multi-ary system code operation, solves the problem of system self-organization and transparency, and non-programmed function coupling, and solves the problems caused by the expansion of word length.
  • the problem of borrowing and accumulating delay time solves the problem of self-organization and openness of the system, and solves the problem of unification of time and space, modulus, logic reversibility, and irreversibility of the information processing system.
  • Multi-bit chip combination 16 values or 32 to 64, 128 value states... optional, and parallel control between multiple ports and multiple pins.
  • the biggest features of the above-mentioned multi-purpose intelligent platform First, it is open, and both the chip level and the board level According to actual needs, the number of large ports can be increased at will, and the number of pins of each port or the multi-valued state can be increased.
  • the main board can also be made into a form that can be cascaded and expanded at will. After the expansion, the relationship between each port and each pin can also be (1 +N) XN / 2 as mentioned above to realize fully interconnected two-way switching and control.
  • the second is that it has parallelism, which can realize full parallel computing by reading and writing the dual-port RAM of each port in parallel, and can also realize parallel bidirectional exchange or parallel bidirectional control by setting a certain port.
  • the third is that each end machine can be used as a host to implement global control.
  • the advantages of the above-mentioned multi-purpose intelligent platform for computing are parallelism, adapting to the computing exchange of various binary codes; adapting to continuous analog calculation; having real-time performance and reversible logic operations; the advantage of being used for switching is parallel, high-speed, real-time two-way , Self-selected routing;
  • the advantages of control are mutual causality, real-time two-way, unified modulus, and any terminal machine can be used as a host to implement global control.
  • the above-mentioned multi-purpose intelligent platform can be used for random function coupling of multiple subsystems, multi-memory interactive access and associative reading and writing, and can reflect its versatility and multi-functionality in the fields of computing, switching, and control, so it has a wide range of applications and has extremely Strong self-development.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

L'invention concerne une plate-forme polyvalente de calcul, de commutation et de commande qui comprend des bus de données, d'adresses, de commande, une unité de commande de bus, des registres de commande, des interfaces de périphériques et des RAM à double accès. Les registres de commande, les interfaces de périphériques et l'unité de commande de bus sont connectés auxdits bus. Des doubles ports de données et un contrôleur en écriture/lecture sont placés entre les interfaces de périphériques et un port des RAM à double accès. Une UAL à logique réversible comporte trois ports doubles qui sont respectivement connectés à l'autre port desdites RAM à double accès. Lesdits registres de commande sont connectés auxdites RAM à double accès via le contrôleur en écriture/lecture. La plate-forme peut fonctionner parallèlement et est apte à opérer et à commuter un code multiniveaux et est adaptée pour effectuer des opérations analogiques successives. Ladite commutation peut être parallèle, à haute vitesse, bidirectionnelle et peut s'adapter aux fonctions d'acheminement. L'invention permet d'effectuer la commande d'opérations hybrides analogiques/numériques, en temps réel et bidirectionnelles.
PCT/CN1998/000116 1997-07-09 1998-07-02 Plate-forme polyvalente de calcul, de commutation et de commande WO1999003046A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU81007/98A AU8100798A (en) 1997-07-09 1998-07-02 A multipurpose platform for arithmetic and exchange and control

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN97112524.4 1997-07-09
CN 97112524 CN1204809A (zh) 1997-07-09 1997-07-09 运算、交换、控制、多用平台

Publications (1)

Publication Number Publication Date
WO1999003046A1 true WO1999003046A1 (fr) 1999-01-21

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CN (2) CN1204809A (fr)
AU (1) AU8100798A (fr)
WO (1) WO1999003046A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104636308A (zh) * 2015-03-10 2015-05-20 王迪兴 可外挂可扩展立交总线架构

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104506505A (zh) * 2014-12-17 2015-04-08 王迪兴 双向信息交互互联网架构系统及其实现方法
CN104504351A (zh) * 2014-12-17 2015-04-08 王迪兴 双向并行多端口安全服务器及其实现方法

Citations (5)

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Publication number Priority date Publication date Assignee Title
US5109524A (en) * 1985-07-02 1992-04-28 Vlsi Technology, Inc. Digital processor with a four part data register for storing data before and after data conversion and data calculations
WO1992007335A1 (fr) * 1990-10-19 1992-04-30 Cray Research, Inc. Systeme d'ordinateur vectoriel en parallele de type evolutif a nombre de processeurs variable
WO1993001563A1 (fr) * 1991-07-08 1993-01-21 Seiko Epson Corporation Architecture risc de microprocesseur avec dependances architecturales isolees
EP0606674A1 (fr) * 1992-12-04 1994-07-20 Koninklijke Philips Electronics N.V. Processeur réalisant des opérations uniformes sur des suites de données successives dans des flux de données parallèles
EP0620533A2 (fr) * 1993-04-13 1994-10-19 Nec Corporation Processeur vectoriel

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5109524A (en) * 1985-07-02 1992-04-28 Vlsi Technology, Inc. Digital processor with a four part data register for storing data before and after data conversion and data calculations
WO1992007335A1 (fr) * 1990-10-19 1992-04-30 Cray Research, Inc. Systeme d'ordinateur vectoriel en parallele de type evolutif a nombre de processeurs variable
WO1993001563A1 (fr) * 1991-07-08 1993-01-21 Seiko Epson Corporation Architecture risc de microprocesseur avec dependances architecturales isolees
EP0606674A1 (fr) * 1992-12-04 1994-07-20 Koninklijke Philips Electronics N.V. Processeur réalisant des opérations uniformes sur des suites de données successives dans des flux de données parallèles
EP0620533A2 (fr) * 1993-04-13 1994-10-19 Nec Corporation Processeur vectoriel

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104636308A (zh) * 2015-03-10 2015-05-20 王迪兴 可外挂可扩展立交总线架构

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Publication number Publication date
CN1204809A (zh) 1999-01-13
AU8100798A (en) 1999-02-08
CN1265755A (zh) 2000-09-06
CN1126048C (zh) 2003-10-29

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