WO1998049622A1 - Carte a puce avec maximisation des acces a la memoire et enregistrement - Google Patents

Carte a puce avec maximisation des acces a la memoire et enregistrement Download PDF

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Publication number
WO1998049622A1
WO1998049622A1 PCT/DE1998/001085 DE9801085W WO9849622A1 WO 1998049622 A1 WO1998049622 A1 WO 1998049622A1 DE 9801085 W DE9801085 W DE 9801085W WO 9849622 A1 WO9849622 A1 WO 9849622A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory
characteristic
accesses
value
write
Prior art date
Application number
PCT/DE1998/001085
Other languages
German (de)
English (en)
Inventor
Markus Weinländer
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO1998049622A1 publication Critical patent/WO1998049622A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
    • G11C16/3495—Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Definitions

  • Chip cards often have a non-volatile memory, the memory cells of which only allow a maximum possible number of write memory accesses.
  • Such memories are, for example, non-volatile EEPROM memory elements. These currently allow about a hundred thousand storing, i.e. content-changing accesses per memory address. At a
  • Figure 1 shows an example of a known, so-called 'ring buffer-like memory area' PS '.
  • This has similarly structured data fields F1 'to Fn', each of which allows a maximum possible number of write memory accesses.
  • a data record to be written is first stored in the first data field F1 'during a first write memory access.
  • the data record is stored in the second and in the case of further write memory accesses in the following data fields F2 'to Fn'.
  • the first, the second and the subsequent data fields Fl '.. Fn' are described one after the other.
  • a memory element X ' serves as a pointer zl' ..
  • the memory element X ' which serves as a pointer element to indicate the data field to be described next, is generally a non-volatile memory element with a maximum permissible number of write memory accesses. If the 'service life' of the memory element X 'is exceeded, it is no longer ensured that the stored pointer value zl' .. zn 'is safely retained by the memory cell.
  • FIG. 2 Another known memory PS '' is shown by way of example in FIG. 2, which is in the form of a so-called 'multi-write memory area'.
  • a memory element X '' serves as a pointer or index for the data fields Fl '' ..Fn ''. This is shown in FIG. 2 by way of example by the arrows provided with the reference numerals zl ′′ to zn ′′.
  • write memory accesses access a certain data field until the maximum number of accesses has been reached. Only then is the pointer value zl '' .. zn '' of the memory element X '' set to the following data field F2 '' .. Fn ''. Is the last
  • the memory PS '' can thus be executed n times the maximum number of write memory accesses with respect to a single data field Fl '' .. Fn ''.
  • the object of the invention is to provide a chip card with a memory which allows only a limited, maximum number of memory accesses which change the memory content and which allows the maximum number of write memory accesses to the memory to be used and the previous memory accesses to be logged.
  • Memory area are executable. According to the invention, the logging depth n-1 of previous write memory accesses is logged at the same time.
  • the invention is therefore advantageously suitable for chip card applications which have a large number of writing memory Accesses and a log of previous, write memory access should have.
  • FIG. 3 shows a schematic illustration of a chip card constructed according to the invention
  • FIG. 4a shows a structure of the memory designed according to an embodiment of the invention with memory areas and characteristic maps and characteristic values assigned to them,
  • FIG. 4b shows the structure of the memory shown in FIG. 4a, the change in the characteristic values being shown which are caused by a write memory access
  • FIG. 3 shows a chip card CK constructed according to the invention with a main memory S.
  • the main memory S has at least one non-volatile memory PS, the memory cells FlL.Fnm of which allow a maximum number of write memory accesses. Memory accesses are closed under write memory accesses understand which change the data content of memory cells FlL.Fnm, such as write and delete access.
  • So-called EEPROM memory modules serve as non-volatile memory PS.
  • the chip card CK has a program execution unit P. This includes, for example, a microprocessor, input / output interfaces, an address register and a program counter, and possibly other volatile and / or non-volatile memories, in particular so-called RAM and / or ROM memory modules.
  • FIGS. 4a and 4b each show an example of a structure of the non-volatile memory PS designed according to the invention.
  • This has at least memory areas FL.Fn, to which a map zL.zn is assigned according to the invention.
  • the memory areas FL.Fn are composed in particular of memory cells FlL.Fnm of the non-volatile memory PS.
  • the memory areas FL.Fn each have m memory cells FlL.Flm to FnL.Fnm.
  • the memory areas FL.Fn preferably have the same arbitrary size.
  • the non-volatile memory PS can be present on the chip card CK in the form of a single memory module or else distributed over several memory modules.
  • the characteristic diagrams zl .. zn shown in FIGS. 4a and 4b each have a characteristic value i..i + (nl) ⁇ or i + l ⁇ ..i + n ⁇ .
  • the size of the characteristic values i..i + (nl) ⁇ or i + l ⁇ ..i + n ⁇ is a measure of the time sequence F with which write memory accesses to the respectively assigned memory areas Fl .. Fn have been made.
  • the program execution unit P of the chip card CK accesses the memory area F2 or F3 which has been described as the oldest in the event of a write memory access to the memory PS.
  • the oldest described memory area F2 or F3 is determined by evaluating the characteristic values i..i + (nl) ⁇ or i + l ⁇ .. i + n ⁇ . Because of According to the invention, the program execution unit P changes the characteristic value i or i + i ⁇ of the map z2 or z3 assigned to it such that the assigned memory area F2 or F3 is recognized by the program execution unit P as the most recent one described.
  • the characteristic values i .. i + (nl) ⁇ or i + l ⁇ ..i + n ⁇ of the characteristic diagrams zL.zn form an ascending or descending sequence X.
  • a write memory access to the memory PS is changed by the program execution unit P according to the invention, the corresponding characteristic value i by increasing or decreasing such that it increases or decreases in the ascending or descending sequence X of the characteristic values i..i + n ⁇ has the lowest value.
  • the characteristic value is preferably set to a minimum value. This can be the case, for example, if a memory byte is used as the map zl .. zn and its maximum value of 255 decimal is exceeded. Then there is, for example, a reset to a minimum value of decimal 0.
  • the characteristic value can be set to a maximum value when the characteristic values are lowered when the value falls below a minimum value.
  • the number n of memory areas FL.Fn of chip card CK can in particular be matched to the maximum possible number of accesses to a memory area FL.Fn that change the memory content or to the length of the necessary logging steps.
  • the number of logging steps corresponds to the number n of memory rich FL.Fn.
  • the maximum total number of possible write memory accesses to the memory PS of the chip card CK corresponds to the product of the number n of the memory areas FL.Fn and the maximum number of write memory accesses, which each allow a memory area FL.Fn of the memory PS.
  • FIGS. 4a and 4b describes how memory accesses writing to the chip card CK according to the invention are directed by rotation to the corresponding memory areas FL.Fn of the memory PS.
  • the memory PS thus forms in particular a ring buffer-like memory, which is also referred to as a so-called 'cyclic file'.
  • FIGS. 4a and 4b by the arrows s.
  • the characteristic fields z1 in FIG. 4a or z2 in FIG. 4b with the largest characteristic value i + (n-1) ⁇ or i + n ⁇ are recognized here by the program execution unit P as the most recently described ones.
  • the characteristic diagram zl has the largest characteristic value i + (nl) ⁇ , the characteristic diagram z2 the smallest characteristic value i.
  • the memory area F1 assigned to the characteristic map z1 and colored gray in the example in FIG. 4a thus contains the most current, ie most recent, data contents, while the memory area F2 assigned to the characteristic map z2 contains the oldest data contents.
  • the characteristic diagrams z3..zn or the memory areas F3..Fn which are located between them with respect to the sequence X or the temporal sequence F contain data contents which are stored in the chronological sequence between the most recent and oldest write memory access in the memory PS were. This causes logging according to the invention.
  • the program execution unit P of the chip card CK determines the chronological sequence F of the write memory accesses to the memory areas FL .Fn by evaluating the characteristic maps zL.zn.
  • a write memory access for example a write access, to the memory PS of the chip card CK takes place according to the invention to the memory area which was described as the oldest. In the example in FIG. 4a, this is the memory area F2, since the characteristic map z2 assigned to it has the smallest characteristic value i compared to the other characteristic values.
  • the characteristic value i of the characteristic diagram z2 is now increased according to the invention, as shown in FIG. 4b. While in the example of FIG. 4a the largest characteristic value was present in the map zl in the amount of i + (n-l) ⁇ , in FIG. 4b the largest characteristic value in the amount of i + n ⁇ was now available in the map z2. In the example of FIG.
  • the program execution unit P thus recognizes the gray-colored memory area F2 assigned to the map z2 as the most recent one described. In the event of a further write access to the memory, the map z3 having the smallest characteristic value i + l ⁇ and the memory area F3 assigned to it would be accessed.

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  • Techniques For Improving Reliability Of Storages (AREA)
  • Credit Cards Or The Like (AREA)
  • Storage Device Security (AREA)

Abstract

L'invention concerne une carte à puce (CK) qui présente une unité d'exécution de programme (P) et une mémoire permanente (PS) dont les cellules (F11..Fnm) permettent un nombre maximum d'accès pour écriture. A cet effet, la mémoire (PS) possède au moins des zones de mémoire (F1..Fn) à chacune desquelles est affecté un champ caractéristique (zl..zn). Les champs caractéristiques comportent chacun une valeur caractéristique (X, i..i+(n-1)Δ), la grandeur des valeurs caractéristiques constituant une mesure pour la séquence dans le temps (F) selon laquelle des accès à la mémoire pour écriture se sont effectués dans les zones de mémoire (Fl..Fn) respectivement associées. En outre, lors d'un accès pour écriture à la mémoire (PS), est d'abord définie, par évaluation des valeurs caractéristiques, la zone de mémoire (F2) dans laquelle il a été écrit il y a le plus longtemps, puis l'accès à cette mémoire est effectué. La valeur caractéristique (i) du champ caractéristique (z2) associé est alors modifiée de sorte que la zone de mémoire (F2) associée soit reconnue comme celle dans laquelle il a été écrit le plus récemment. De façon avantageuse, conformément au nombre n des zones de mémoire utilisées, un nombre correspondant à n x le nombre maximum d'accès pour écriture à la mémoire concernant une zone de mémoire individuelle peut être exécuté. L'invention offre simultanément la possibilité d'avoir un enregistrement des accès pour écriture à la mémoire exécutés dans le passé.
PCT/DE1998/001085 1997-04-30 1998-04-17 Carte a puce avec maximisation des acces a la memoire et enregistrement WO1998049622A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19718479.0 1997-04-30
DE1997118479 DE19718479C1 (de) 1997-04-30 1997-04-30 Chipkarte mit Speicherzugriffsmaximierung und Protokollierung

Publications (1)

Publication Number Publication Date
WO1998049622A1 true WO1998049622A1 (fr) 1998-11-05

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PCT/DE1998/001085 WO1998049622A1 (fr) 1997-04-30 1998-04-17 Carte a puce avec maximisation des acces a la memoire et enregistrement

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WO (1) WO1998049622A1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10129417A1 (de) * 2001-06-19 2003-01-09 Infineon Technologies Ag Verfahren zum Bearbeiten eines Speicherplatzes in einem Speicher einer Chipkarte
US20030204857A1 (en) * 2002-04-29 2003-10-30 Dinwiddie Aaron Hal Pre-power -failure storage of television parameters in nonvolatile memory
EP1713085A1 (fr) * 2002-10-28 2006-10-18 SanDisk Corporation Usage automatisé nivelant les systèmes de stockage non volatiles
DE60316171T2 (de) 2002-10-28 2008-05-29 SanDisk Corp., Milpitas Automatischer abnutzungsausgleich in einem nicht-flüchtigen speichersystem
DE102004037785A1 (de) * 2004-08-03 2006-03-16 Endress + Hauser Gmbh + Co. Kg Feldgerät für die Automatisierungstechnik
DE102009004291A1 (de) * 2009-01-10 2010-07-15 Austria Card Gmbh Chipkarte mit Austauschindikation

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0340981A2 (fr) * 1988-04-28 1989-11-08 Sony Corporation Méthode et appareil d'emmagasinage d'informations
GB2243230A (en) * 1990-02-27 1991-10-23 Nec Corp Method and system for storing data in a memory
FR2665791A1 (fr) * 1990-08-13 1992-02-14 Mazingue Didier Procede de mise a jour d'une memoire eeprom.

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05151097A (ja) * 1991-11-28 1993-06-18 Fujitsu Ltd 書換回数制限型メモリのデータ管理方式
FR2689263A1 (fr) * 1992-03-25 1993-10-01 Trt Telecom Radio Electr Dispositif comportant des moyens pour valider des données inscrites dans une mémoire.

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0340981A2 (fr) * 1988-04-28 1989-11-08 Sony Corporation Méthode et appareil d'emmagasinage d'informations
GB2243230A (en) * 1990-02-27 1991-10-23 Nec Corp Method and system for storing data in a memory
FR2665791A1 (fr) * 1990-08-13 1992-02-14 Mazingue Didier Procede de mise a jour d'une memoire eeprom.

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DE19718479C1 (de) 1998-09-24

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