WO1998042074A1 - Evaluation of a pulse-width modulation signal - Google Patents
Evaluation of a pulse-width modulation signal Download PDFInfo
- Publication number
- WO1998042074A1 WO1998042074A1 PCT/DE1998/000712 DE9800712W WO9842074A1 WO 1998042074 A1 WO1998042074 A1 WO 1998042074A1 DE 9800712 W DE9800712 W DE 9800712W WO 9842074 A1 WO9842074 A1 WO 9842074A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- signal
- counter
- level
- feedback signal
- counting
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/02—Measuring effective values, i.e. root-mean-square values
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
- G01P15/00—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration
- G01P15/02—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses
- G01P15/08—Measuring acceleration; Measuring deceleration; Measuring shock, i.e. sudden change of acceleration by making use of inertia forces using solid seismic masses with conversion into electric or magnetic values
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
- H03M1/504—Analogue/digital converters with intermediate conversion to time interval using pulse width modulation
Definitions
- the invention relates to a method and a circuit arrangement for evaluating a pulse-width modulation signal (PWM signal) having a first level and a second level according to the preamble of claim 1 or according to the preamble of claim 4, respectively which is counted up at least temporarily at a predetermined frequency during the period of the first level, or which has a first counter which has a first activation input to which a first activation signal is present, which is formed from the PWM signal, the first counter only counts during the time that the first activation signal activates the first counter.
- PWM signal pulse-width modulation signal
- the counting frequency In order to count a PWM signal with an accuracy of 8 bits, for example, the counting frequency must be 256 times the frequency of the PWM signal. If the frequency of the PWM signal is, for example, one kilohertz (KH), the counting frequency is 256 kilohertz. Such a counting frequency can be processed by most systems without problems.
- KH one kilohertz
- the frequency of the PWM signal is approximately 250 kilohertz, as is the case, for example, with an output signal from a sensor for a position control loop of a micromechanical accelerometer, a counting frequency of at least 64 megahertz would be necessary for an 8-bit resolution.
- the processing of such a high counting frequency is, however, quite complex.
- the useful signal on which the PWM signal is based also contains frequency components with a higher frequency and only the frequency components with a lower frequency are required for further processing, as is the case, for example, when accelerating, as occurs when a motor vehicle hits a wall the high frequency components to meet Shannon's sampling theorem are filtered out of the sensor signal using a filter become.
- the low-pass filtering of the sensor signal ensures that the sensor signal can be digitized with reasonable effort.
- the PWM signal emitted by an accelerometer to trigger an air cushion used in the motor vehicle contains high frequency components, a very high counting frequency must be used to evaluate the PWM signal using the known methods. This is very disadvantageous.
- the sensor signal is regularly filtered using a low-pass filter before the analog-digital conversion.
- At least intermittent counting down takes place during the period of the second level, that is to say the first counter has a first counting direction input, to which a first counting direction signal taking on two levels is present, the first counter counting up when the first counting direction signal has the first level and the first counter counts down when the first count direction signal is at the second level.
- the PWM signal determines whether the counter is counting up or down, the counter reading changes only to the extent that the pulse duty factor of the PWM signal is different by 50%. If the pulse duty factor of the PWM signal is 50%, the counter counts up and down as much. The count would fluctuate around an average. With a duty cycle of greater than 50%, the count value moves upwards on average, with a duty cycle of less than 50% downwards.
- the first counter is not only activated by the PWM signal, but the counting direction is also specified by the PWM signal. That is, the PWM signal also forms the first counting direction signal.
- the PWM signal is particularly easy to evaluate if the first counter counts up and down at a constant frequency. If the counter reading is read out at certain intervals, the difference between the counter readings corresponds to the pulse duty factor of the PWM signal.
- the evaluation principle is ultimately based on averaging.
- the resolution when the PWM signal and the counting frequency signal run synchronously, will not be better than in a conventional evaluation, since the counter registers the PWM signal only on its own clock edges, that is, at discrete times. However, if there is no synchronization between the PWM signal and the counting frequency signal, the counter is not read out several times in succession at the same point in the PWM signal. With a If the distance of the meter reading is selected long enough, each point is scanned once within a PWM interval, which increases the resolution.
- the evaluation of a PWM signal according to the invention has the advantage that it is integrated over the entire sampling period.
- the counter acts like an integrator. The resolution can be adjusted by changing the sampling period.
- An embodiment of the invention has proven to be particularly advantageous in which a first logic element is provided which, depending on the respective counter reading and the counting frequency, forms a first feedback signal having a first level and a second level in such a way that the first feedback signal is composed of a proportionality factor and corresponds to the current counter reading formed part of the counting frequency, wherein the first feedback signal is used to form the first activation signal and the first counting direction signal.
- the feedback signal thus has a pulse density that is dependent on the proportionality factor and the current counter reading.
- the function of the counter can advantageously be set so that the counting speed with which the first counter counts up decreases with increasing counter reading.
- the counter output signal shows low-pass behavior.
- the cut-off frequency can be set using the proportionality factor.
- the feedback signal can be used to set the function of the counter so that the counter output signal behaves like a first-order low-pass filter. Due to the low-pass behavior of the according to the circuit arrangement, an additional filter to limit the bandwidth of the PWM signal can be dispensed with in a particularly advantageous manner.
- a second logic element which forms the first activation signal and the first counter direction signal from the PWM signal and the first feedback signal in such a way that the first counter is activated when the PWM signal has the first level and the first feedback signal is at the second level or the PWM signal is at the second level and the first feedback signal is at the first level, and the first counter is deactivated when the PWM signal is at the first level and the first feedback signal is at the first Has level or the PWM signal has the second level and the first feedback signal has the second level, and the first counter direction signal has the first level if the PWM signal has its first level and the first feedback signal has the second level and that first counter direction signal has the second level, or whom n the PWM signal has its second level and the first feedback signal has the first level.
- the formation of the first activation signal described above is a logical combination of the PWM signal with the first feedback signal known as an exclusive OR.
- the first counter direction signal is formed by directly taking over the PWM signal. Since standard components are used to form the first activation signal and the first counter direction signal. can be used, the implementation of the latter embodiment is very inexpensive.
- the first logic element can advantageously be designed in such a way that it has an up-counter, which is operated synchronously with the first counter and whose multi-bit wide output is connected to the multi-bit wide input of an edge detector.
- the edge detector emits a pulse at its bit-wide output at one bit position only if there is an edge change of the corresponding input bit, for example in the positive direction, for the duration of, for example, the entire or only the positive clock of the counting frequency.
- the output of the edge detector is connected to an evaluation circuit in which the bit positions of the output of the edge detector and the bit positions of the output of the first counter are each connected via an AND operation.
- the linkage is such that the least significant bit position of the output of the edge detector is linked to one another with the most significant bit position of the output of the first counter.
- the outputs of the AND operations are connected to one another via an OR operation, which emits the first feedback signal at its output. With such a circuit arrangement, the first feedback signal can be generated with very simple means.
- the proportionality factor can be generated very easily by means of such a circuit arrangement.
- the proportionality factor can be adjusted by shifting the bit positions of the output of the edge detector in relation to the bit positions of the output of the first counter. The change takes place in powers of two.
- the circuit arrangement according to the invention cannot only be used for evaluating a PWM signal. It can be used in a particularly advantageous manner for any signal whose information lies in the pulse density, in particular for output signals from sigma-delta converters.
- the circuit arrangement according to the invention already includes a filter, so that further components can be omitted for filtering. This has a particularly favorable effect on costs.
- the filtering acts like a quasi-continuous digital filter. The discretization on the time axis that is regularly present in normal digital filters, for example a 250 ⁇ -second raster with a measurement signal bandwidth of 1000 Hertz, is no longer important, since the effective sampling rate now corresponds to the counter clock, which results in a discretionary raster of 1000 to 500 ns , practically no longer seen.
- a second counter which has a second activation input to which a second activation signal is present, which is formed from the first feedback signal and a second feedback signal having a first level and a second level.
- the second counter only counts while the second activation signal activates the second counter.
- the second counter also has a second counting direction input, to which a second counting direction signal having two levels is present. The second counter counts up when the second count direction signal is at the first level and the second counter counts down when the second count direction signal is at the second level.
- a third logic element is provided which, depending on the respective counter reading of the second counter and the counting frequency, forms the second feedback signal in such a way that the second feedback signal is a part of the second feedback signal which is formed from a second proportionality factor and the respective current counter reading Counter frequency corresponds.
- a fourth logic element which forms the second activation signal and the second counter direction signal from the first feedback signal and the second feedback signal.
- the second activation signal is formed such that the second counter is activated if the first feedback signal has the first level and the second feedback signal has the second level or the first feedback signal has the second level and the second feedback signal has the first level, and the second counter is deactivated when the first feedback signal has the first level and the second feedback signal has the first level or the first feedback signal has the second level and the second feedback signal has the second level.
- the counter direction signal is formed in such a way that the second counter direction signal has the first level when the first feedback signal reaches its first level. and the second feedback signal has the second level, and the second counter direction signal has the second level if the first feedback signal has its second level and the second feedback signal has the first level.
- the circuit arrangement formed from the second counter and the third and fourth logic element corresponds to the circuit arrangement formed from the first counter and the first and second logic element. It therefore also shows low eating behavior.
- the overall circuit arrangement acts like two low-pass filters of the first order connected in series.
- circuit arrangement formed from the second counter and the third and fourth logic element connects to the circuit arrangement formed from the first counter and the first and second logic element, further corresponding circuit arrangements can follow. It is possible to borrow a large number of such circuit arrangements in series so that very different filter behavior can be set.
- FIG. 1 is a block diagram of a circuit arrangement according to the invention in a schematic representation
- Fig. 2 shows an embodiment of a first logic element in a schematic representation.
- a PWM signal emitted, for example, by a micromechanical accelerometer is carried out for synchronization via a D / Q flip-flop 9.
- a signal FI forming the system clock or the counting frequency is applied to the D / Q flip-flop 9.
- the counting frequency signal FI is also applied to a first counter 1.
- the first counter 1 has a first activation input E and a first counting direction input U / D.
- the first activation input E and the first counting direction input U / D are connected to a second logic element 4.
- the second logic element 4 generates an activation signal SE applied to the first activation input E of the first counter 1 and a first counter direction signal applied to the first counting direction input U / D of the first counter 1.
- the two signals are formed from the PWM signal synchronized by the D / Q flip-flop 9 and a first feedback signal R.
- the first activation signal SE is formed by an exclusive OR operation of the synchronized PWM signal with the first feedback signal R.
- the first counter direction signal is a through-connection of the PWM signal.
- the output of the first counter 1 is connected to a standard multiplexer 10, by means of which the output bits of the output of the counter 1 can be shifted in the direction of the least significant bit.
- the output of the multiplexer 10 is connected to a first input of an edge detector 3.
- a data word ZB which is smaller than the counter reading Z of the first counter 1, reaches the first input of the edge detector 3 through the multiplexer 10.
- a two input of the edge detector 3 is connected to the output of an edge evaluation 7.
- the edge detector 3 forms the first feedback signal R from the counter reading Z of the first counter 1 or the output data word ZP of the multiplex 10 and the output signal F of the edge detector 7.
- the first feedback signal R consists of a sequence of pulses which are associated with the counting frequency signal FI are synchronous.
- the average number of pulses per unit time of the first feedback signal R depends on the count Z of the first counter 1. If the counter reading is low, the average pulse number is small and thus a low pulse density. As a result, the first counter 1 is predominantly set so that it counts up. When the count is high, the pulse density of the first feedback signal R is high, that is to say the first counter 1 is only briefly set so that it counts up.
- the input of the edge detector 7 is connected to the output of a dual counter 8, which continuously counts up in time with the counting frequency FI and which starts counting again at zero in the event of an overflow.
- the edge detector 7 is so switches that it outputs a pulse at its output F at a bit position fdo to fdn only at a predetermined edge change of the corresponding input bit, that is to say the corresponding bit position azo to azn of the dual counter 8.
- the duration of the pulse corresponds to the duration of a cycle of the counting frequency FI.
- a second evaluation stage consisting of a second counter 2, a second edge evaluation 5 and a fourth logic element 6 is connected, which in conjunction with the dual counter 8 and the edge detector 7 has the same function as the first stage.
- the input signal for the second stage does not form the PWM signal, but the first feedback signal R.
- the output signal Z of the first counter 1 or the output signal Z 'of the second counter 2 or the first feedback signal R or the second feedback signal R' can be used. Because the information contained in the PWM signal is not only in the output signal of the first counter 1 or the second counter 2, but also in the first feedback signal R or in the second feedback signal R ', since the pulse density of the feedback signal R, R' is also from the PWM Signal depends.
- the output bits of the dual counter 8, apart from the first output bit azo, are connected to inputs of AND gates, which the edge detector 7 has.
- the first output bit azo is directly with connected to the corresponding output fdo of the edge detector 7.
- the second output bit fdl of the edge detector 7 is an AND operation of the two first output bits azo, azl of the dual counter 8.
- the third output bit fd2 of the edge detector 7 is an AND operation of the first three output bits azo, azl and az2 of the dual counter 8. The arrangement is continued until finally the last output bit fdn of the edge detector 7 is formed by means of an AND operation of all output bits azo to azn of the dual counter 8.
- a pulse occurs at the output of the edge detector 7 at a bit location fdo to fdn only for the duration of a clock of the counting frequency FI if azo to azn of the output of the dual counter 8 occurs at the relevant bit location Edge change has taken place in a positive direction, for example.
- the bit positions fdo to fdn of the edge detector 7 each lead to the input of an associated AND gate.
- the second input of the respective AND gate is connected to a bit position zn-1 to zo of the output of the first counter 1.
- bit positions fdo to fdn of the output of the edge detector 7 are linked to the bit positions zn-1 to zo of the output of the first counter 1 in such a way that the least significant bit position fdo of the output bits fdo to fdn of the edge detector 7 are linked with the most significant bit position zn of the output bits zo to zn of the first counter 1. This means that with increasing the count of the first counter 1 increasingly at one of the outputs of the AND gates a pulse.
- the outputs of the AND gates are linked to one another via an OR gate.
- the first feedback signal R is generated at the output of the OR gate.
- the first feedback signal R thus occurs more frequently with increasing counter reading of the first counter 1. That is, the higher the counter reading of the first counter 1, the greater the pulse density of the feedback signal R.
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP98921354A EP0966791A1 (en) | 1997-03-14 | 1998-03-11 | Evaluation of a pulse-width modulation signal |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19710558.0 | 1997-03-14 | ||
DE1997110558 DE19710558A1 (en) | 1997-03-14 | 1997-03-14 | Evaluation of a pulse width modulation signal |
Publications (1)
Publication Number | Publication Date |
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WO1998042074A1 true WO1998042074A1 (en) | 1998-09-24 |
Family
ID=7823347
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE1998/000712 WO1998042074A1 (en) | 1997-03-14 | 1998-03-11 | Evaluation of a pulse-width modulation signal |
Country Status (3)
Country | Link |
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EP (1) | EP0966791A1 (en) |
DE (1) | DE19710558A1 (en) |
WO (1) | WO1998042074A1 (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4485347A (en) * | 1980-09-04 | 1984-11-27 | Mitsubishi Denki Kabushiki Kaisha | Digital FSK demodulator |
JPH05315910A (en) * | 1992-05-07 | 1993-11-26 | Nec Corp | Duty ratio judging circuit |
JPH0746275A (en) * | 1993-07-26 | 1995-02-14 | Idec Izumi Corp | Data discrimination method by pulse width |
-
1997
- 1997-03-14 DE DE1997110558 patent/DE19710558A1/en not_active Withdrawn
-
1998
- 1998-03-11 WO PCT/DE1998/000712 patent/WO1998042074A1/en not_active Application Discontinuation
- 1998-03-11 EP EP98921354A patent/EP0966791A1/en not_active Withdrawn
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4485347A (en) * | 1980-09-04 | 1984-11-27 | Mitsubishi Denki Kabushiki Kaisha | Digital FSK demodulator |
JPH05315910A (en) * | 1992-05-07 | 1993-11-26 | Nec Corp | Duty ratio judging circuit |
JPH0746275A (en) * | 1993-07-26 | 1995-02-14 | Idec Izumi Corp | Data discrimination method by pulse width |
Non-Patent Citations (2)
Title |
---|
PATENT ABSTRACTS OF JAPAN vol. 018, no. 124 (E - 1517) 28 February 1994 (1994-02-28) * |
PATENT ABSTRACTS OF JAPAN vol. 095, no. 005 30 June 1995 (1995-06-30) * |
Also Published As
Publication number | Publication date |
---|---|
EP0966791A1 (en) | 1999-12-29 |
DE19710558A1 (en) | 1998-09-17 |
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