WO1998006129A1 - Espaceur de parois laterales pour lignes de grille verticales au chrome - Google Patents

Espaceur de parois laterales pour lignes de grille verticales au chrome Download PDF

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Publication number
WO1998006129A1
WO1998006129A1 PCT/CA1996/000519 CA9600519W WO9806129A1 WO 1998006129 A1 WO1998006129 A1 WO 1998006129A1 CA 9600519 W CA9600519 W CA 9600519W WO 9806129 A1 WO9806129 A1 WO 9806129A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
insulator material
gate line
depositing
wall spacers
Prior art date
Application number
PCT/CA1996/000519
Other languages
English (en)
Inventor
Chengbin Qiu
Michael Hall
Original Assignee
Litton Systems Canada Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Litton Systems Canada Limited filed Critical Litton Systems Canada Limited
Priority to PCT/CA1996/000519 priority Critical patent/WO1998006129A1/fr
Publication of WO1998006129A1 publication Critical patent/WO1998006129A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes

Definitions

  • This invention relates in general to thin film transistors, and more particularly to a method of depositing a thin metallization layer with improved step coverage during fabrication of thin film transistors.
  • AMLCDs Active matrix liquid crystal displays
  • TFTs thin film transistors
  • CRT displays cathode ray tube
  • TFT driven AMLCDs are characterized by low power consumption, light weight, fliclcerless image, thin profile, low-voltage operation, large dynamic range of screen luminance, high contrast ratio and integrated circuit process compatibility.
  • the TFT arrays used in AMLCDs function as switches to charge individual pixel storage capacitors and to control leakage between refresh cycles.
  • a layer of chromium film is deposited and patterned onto a glass substrate.
  • a gate insulator layer is deposited over the patterned gate line.
  • a thin conductive layer is deposited and patterned so as to form a transparent output pad.
  • a further oxide layer is then deposited followed by semiconductor deposition and patterning, oxide passivation, opening of contact vias, source/drain metal deposition and patterning.
  • the initial patterning of the gate line is typically implemented by wet etching
  • a method for depositing a thin conductive layer with improved step coverage during fabrication of thin film transistors.
  • a side- wall spacer is introduced between the gate patterning step and subsequent gate insulator layer deposition in order to improve the step coverage of the conductive film over the gate line.
  • the side- wall spacer abuts the side walls of the gate lines forming a desired width and slope for later conformal deposition of the thin metallization layer
  • Figure 1 shows a partially fabricated thin film transistor according to the prior art
  • Figures 2A-2E show successive steps in the process according to the present invention for introducing a side-wail spacer between gate patterning and subsequent gate insulator layer deposition steps during fabrication of a thin film transistor.
  • FIG. 1 a partially fabricated thin film transistor is shown according to prior art methodology.
  • a 2400 Angstrom chromium film is deposited on polished Corning 7059TM borosilicate glass substrate 1.
  • the chromium layer is patterned and etched to form gate line 3, using a wet etching process, as discussed above.
  • a layer of SiO 2 is deposited via plasma enhanced chemical vapour deposition (PECVD) to form gate insulator 5.
  • PECVD plasma enhanced chemical vapour deposition
  • ITO Indium Tin Oxide
  • An ITO cover oxide 9 is then deposited. Additional steps
  • CdSe semiconductor deposition and patterning include CdSe semiconductor deposition and patterning, PECVD oxide passivation, opening of contact vias and source/drain metal deposition and patterning.
  • the patterning of the chromium to form gate line 3 is accomplished via wet etching (e.g. using Cr - 4TM Chrome Etchant manufactured by Cyantek Corp.).
  • wet etching e.g. using Cr - 4TM Chrome Etchant manufactured by Cyantek Corp.
  • Cr - 4TM Chrome Etchant manufactured by Cyantek Corp.
  • the Cr gate line 3 has either a vertical or negative slope, resulting in a mushroom shape to the subsequently deposited layers.
  • the thin ITO layer 7 can become discontinuous on top of the gate line 3 and beside the gate line, especially at the regions denoted by reference numeral 1 1.
  • FIGS. 2A-2E the process flow according to the present invention is shown for introducing side-wall spacers on either side of the gate line 3 for improving the step coverage of the ITO film 7 over the Cr gate line 3.
  • a 2400 Angstrom silicon dioxide (SiO 2 ) layer 5 A is deposited ( Figure 2B).
  • Reactive ion etching (RIE) is then used to remove the planar portions of the oxide layer 5A.
  • oxide side wall spacers 5A remain on either side of the gate line 3 where the deposited film is thicker in the vertical direction ( Figure 2C).
  • the desired width and slope of the side-wall spacers 5 A can be controlled in a single RIE step by adjusting a set of process parameters and the thickness of the CVD oxide 5 A.
  • the sides of the spacers 5 A are further eroded, resulting in steeper slope, whereas a decrease in pressure results in a more conformal bulbous shape to the side-wall spacers 5A.
  • the slope of the side-wall spacers 5 A can be further steepened.
  • RIE operating parameters used for the fabrication of side- wall spacers 5 A are as follows:
  • the usual gate oxide layer 5B is deposited, followed by ITO layer 7, and the usual subsequent steps.
  • the fabrication of side- wall spacers 5 A according to the present invention results in conformal deposition of the ITO layer 7, with improved step coverage and an absence of discontinuities in the film.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention porte sur une technique permettant de déposer une mince couche conductrice possédant un pouvoir couvrant graduel amélioré durant la fabrication d'un transistor à couche mince. Cette technique comporte les phases suivantes: dépôt d'une première couche d'un matériau isolant sur une ligne de grille ayant été plaquée et mise en forme sur un substrat de verre, enlèvement des parties planes de cette première couche de matériau isolant par attaque aux ions réactifs de manière à découvrir des parties du substrat de verre et de la ligne de porte tout en intercalant des espaceurs de parois latérales de matériau isolant venant porter sur les parois opposées de la ligne de grille, dépôt d'une seconde couche de matériau isolant sur les espaceurs de parois latérales ainsi que sur les parties à découvert du substrat de verre et de la ligne de porte, ce qui permet de constituer une couche isolante de grille à parties inclinées positivement sus-jacentes aux espaceurs de parois latérales et dépôt enfin de la mince couche conductrice au-dessus de la couche isolante de grille. De ce fait, les parties à inclinaison positive de la couche isolante de grille formée par les espaceurs de parois latérales donnent lieu à un dépôt de la mince couche conductrice à même d'épouser les formes de son support.
PCT/CA1996/000519 1996-07-31 1996-07-31 Espaceur de parois laterales pour lignes de grille verticales au chrome WO1998006129A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/CA1996/000519 WO1998006129A1 (fr) 1996-07-31 1996-07-31 Espaceur de parois laterales pour lignes de grille verticales au chrome

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CA1996/000519 WO1998006129A1 (fr) 1996-07-31 1996-07-31 Espaceur de parois laterales pour lignes de grille verticales au chrome

Publications (1)

Publication Number Publication Date
WO1998006129A1 true WO1998006129A1 (fr) 1998-02-12

Family

ID=4173164

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CA1996/000519 WO1998006129A1 (fr) 1996-07-31 1996-07-31 Espaceur de parois laterales pour lignes de grille verticales au chrome

Country Status (1)

Country Link
WO (1) WO1998006129A1 (fr)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0506427A1 (fr) * 1991-03-27 1992-09-30 STMicroelectronics, Inc. Transistor integré ayant l'effet d'un champ de grille avec imbrication grille-drain et méthode pour sa préparation

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0506427A1 (fr) * 1991-03-27 1992-09-30 STMicroelectronics, Inc. Transistor integré ayant l'effet d'un champ de grille avec imbrication grille-drain et méthode pour sa préparation

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
JEON D Y: "GATE TECHNOLOGY FOR 89 GHZ VERTICAL DOPING ENGINEERED SI METAL- OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR", JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY: PART B, vol. 10, no. 6, 1 November 1992 (1992-11-01), pages 2922 - 2926, XP000332499 *
RUSSEL MARTIN: "SPACER FOR IMPROVED LOCAL OXIDATION PROFILE", XEROX DISCLOSURE JOURNAL, vol. 12, no. 5, 1 September 1987 (1987-09-01), pages 251 - 253, XP000110800 *
YAO W W ET AL: "METAL STEP COVERAGE IMPROVEMENT IN DOUBLE LEVEL METAL WITH OXIDE SPACERS", IEEE VLSI MULTILEVEL INTERCONNECTION CONFERENCE, SANTA CLARA, JUNE 25 - 26, 1985, no. 1985, 25 June 1985 (1985-06-25), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 38 - 44, XP000010240 *

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