WO1998003978A1 - Dispositif de reference, procede de fixation d'un niveau de reference, procede d'autodiagnostic et memoire semi-conductrice non volatile - Google Patents

Dispositif de reference, procede de fixation d'un niveau de reference, procede d'autodiagnostic et memoire semi-conductrice non volatile Download PDF

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Publication number
WO1998003978A1
WO1998003978A1 PCT/JP1997/002269 JP9702269W WO9803978A1 WO 1998003978 A1 WO1998003978 A1 WO 1998003978A1 JP 9702269 W JP9702269 W JP 9702269W WO 9803978 A1 WO9803978 A1 WO 9803978A1
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WO
WIPO (PCT)
Prior art keywords
gate
cell
memory cell
reference cell
main surface
Prior art date
Application number
PCT/JP1997/002269
Other languages
English (en)
Japanese (ja)
Inventor
Nobuyoshi Takeuchi
Original Assignee
Nkk Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nkk Corporation filed Critical Nkk Corporation
Publication of WO1998003978A1 publication Critical patent/WO1998003978A1/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563—Multilevel memory reading aspects
    • G11C2211/5634—Reference cells

Definitions

  • Reference mounting method reference level setting method, self-diagnosis method, and nonvolatile semiconductor memory device
  • the present invention relates to a semiconductor device, in particular EP ROM, E '2 P ROM , reference device and its's Reference level setting for data references in the nonvolatile memory device such as a hula Sshumemo Li.
  • the present invention relates to a self-diagnosis method using the reference device, and further relates to a nonvolatile semiconductor memory device including the reference device.
  • non-volatile memory devices such as EP ROM, E 2 P ROM, flash memory, etc.
  • Such a reference cell is generally made of the same type as the memory cell in order to represent the characteristics of the memory cell.
  • U.S. Pat. Nos. 4,223,394 describe an isomorphic reference cell in an EPROM.
  • n 1
  • the voltage applied to the reference cell is multi-staged, the output is multi-valued, or a plurality of sense amplifiers having different sense ratios are prepared, and the sense amplifier is operated according to the output.
  • a method has been proposed to support multi-leveling by using different methods.
  • the circuit itself becomes complicated and the circuit area increases.
  • the setting of multi-leveling is not a reference cell itself, but a so-called reference. The problem is that the correlation with the memory cell becomes difficult because the external environment of the reference cell is changed.
  • the present invention provides a reference cell set including a reference cell having a gate power ripple ratio smaller than that of a memory cell and a reference cell having a gate coupling ratio larger than that of the memory cell.
  • two reference cells constituting each reference cell set may have a gate power ratio of ⁇ 0.5 to 7.0 with respect to a gate power ratio of a memory cell.
  • the present invention includes a memory cell, a reference cell having a smaller gate power ruffle ratio than the memory cell, and a reference cell having a larger gate power ruffle ratio than the memory cell. 2 to provide a non-volatile semi-conductor memory device characterized by comprising a's Reference device having a plurality of re files Rensuseruse' DOO
  • a multi-valued reference cell set including a reference cell having a gate couple ratio smaller than that of a memory cell and a reference cell having a gate couple ratio larger than the memory cell is used.
  • the three reference cell sets prepared for each level are programmed according to the number of multi-levels, using pulses that are an integral multiple of the number of voltage pulses used to program the memory cells.
  • each reference cell set is set so as to maintain the margin of each level according to the number of pulses and also have a margin corresponding to the multilevel level.
  • the specified level will always be at the point where the memory cell was pulsed. Therefore, without increasing the circuit area, it is possible to cope with multi-leveling while sufficiently correlating with the memory cell.
  • FIG. 1 is a diagram showing a nonvolatile memory circuit including a cell array and a reference device according to an embodiment of the present invention.
  • Figure 2 shows the program characteristics of the memory cell and each reference cell.
  • FIG. 3 is a diagram showing program characteristics of a memory cell and each reference cell when a multi-level level setting reverse to that of FIG. 2 is performed.
  • c Figure 5 A and 5 B is a cross-sectional view showing an example of Jozo memory cell used in the present invention is a diagram showing an example in which occupies different Getokatsupuru ratio of the reference cell.
  • FIG. 6 is a plan view showing another example of the structure of the memory cell and the reference cell used in the present invention.
  • FIG. 7 is a cross-sectional view taken along the line XX ′ of FIG.
  • FIG. 8 is a sectional view taken along line YY ′ of FIG.
  • FIG. 9 is a schematic diagram showing another example of the structure of the reference cell used in the present invention.
  • FIGS. 10A and 10B are plan views showing the reference cell shown in FIG. 9, respectively.
  • FIGS. 11A and 11B are plan views each showing another example of the reference cell.
  • FIG. 12 is a diagram showing an example of a specific nonvolatile memory circuit using the reference device of the present invention.
  • FIG. 13 is a diagram showing another example of a specific nonvolatile memory circuit using the reference device of the present invention.
  • FIG. 1 is a diagram showing a nonvolatile memory circuit including a cell array and a reference device according to an embodiment of the present invention.
  • the cell array 1 has a plurality of memory cells 2, each of which is connected to a reference selection circuit 4 via a sense amplifier 3.
  • the reference selection / selection circuit 4 has a plurality of reference cell sets 5 2 , 5, 5, 5 2 , 5, and 5, according to the levels R, R 2 , R, of multi-level quantization.
  • the reference cell set is composed of a reference cell having a smaller gate coupling ratio than a memory cell and a reference cell having a larger gate coupling ratio than the memory cell.
  • Figure 2 shows the program characteristics of memory cells and each reference cell, with the number of pulses (logarithm) on the horizontal axis and the threshold value on the vertical axis.
  • This shows the program characteristics of EPROM.
  • the threshold value of notes Riseru is between Li off Arensuseruse' bets 5, the threshold value of each re fa Rensuseru of ⁇ 5 n. Then, if the difference between the number of program pulses or the total program time is sufficiently large, the reference levels at each pulse number can be made not to overlap:
  • the characteristics are not limited to the flash EPROM by the Fauula-Nordheim tunnel electron injection, and other programming methods such as hot carrier injection have similar characteristics.
  • the multi-value determination can be performed by the following procedure.
  • Fig. 3 it is also possible to set a multi-level level opposite to that of Fig. 2 by extracting electrons from the high threshold voltage through the Fowler-Nordheim tunneling electron.
  • the memory cell and reference cell set explain the relationship with the program and the program time.
  • the gate coupling ratio (hereinafter abbreviated as the “kapple ratio”) of the reference cell set is too different from that of the memory cell. If it is small, the threshold change will be slow. For this reason, the memory cell must have a threshold between each reference cell in the reference cell set; an overlap with other multi-levels; and a reference level. It is necessary to consider the margin of the bezel, that is, the threshold width that can absorb the program variation of the memory array. In addition, the number of multilevel levels ( 2n ) also becomes a problem.
  • the difference between the two reference cells that make up each reference cell set is within ⁇ 0.5 to ⁇ 7.0% of the memory cell couple ratio. It is desirable that the magnitude ratio of the reference ratio of the reference cells in each set is not necessarily symmetric. In other words, if one of the reference cells is + 3%, the force ripple ratio of the other reference cell does not have to be 1: 1 :.
  • the reference device of the present invention may be configured as follows.
  • the memory cell and the reference set of the present invention are programmed or erased at the same time, and the threshold value of the memory cell is changed by an arbitrary number of pulses, and then the verify operation is performed. Can be.
  • the characteristics of the memory cell are found to be abnormal. This is because the threshold value of the memory cell must be within the threshold width of the reference cell set.
  • the threshold value after programming or erasing is compared with the threshold value of the reference cell to confirm that the cell has been programmed or erased. More specifically,
  • a voltage V1 is applied to the gate of the reference cell, and the output of the memory cell should be lower than the output of the reference cell at that time;
  • the threshold of the memory cell is checked. Therefore, the output component when a voltage V such that VI ⁇ V ⁇ V2 is applied is a margin. Thus, in the conventional method, the level at which the change in the threshold value of the memory cell is confirmed is determined. And it is difficult to set it to any value.
  • the present invention there are two cells in the reference cell set, one of which has a smaller gate cut ratio than the memory cell, the other has a larger size than the memory cell.
  • the transistor characteristics of the and reference cells are similar except for the gate couple ratio. Therefore, if a memory cell and the reference cell set have the same initial state, and if they are programmed or erased simultaneously, the threshold value of the memory cell will always fall between the threshold values of the cells in the reference cell set. This means that the programming and erasing speed depends only on the gate-cable ratio if other parameters are common, and the gate voltage of the programming and erasing on the memory device to avoid complexity. Are commonly used for memory cells and reference cells. Or
  • the memory cell and the reference cell set are programmed or erased only at an arbitrary time, and the threshold value of the memory cell is compared with the threshold value of the reference cell set. It can be confirmed that the threshold value is between the threshold values of the cells in the reference cell set. In other words, it is possible to confirm whether the memory cell is really programmed or erased. That is, according to the present invention, an arbitrary threshold value can be set and confirmed, that is, self-diagnosis can be performed.
  • the state of the memory cell and the reference cell set before programming or erasing are the same if the programming or erasing time exceeds several tens of milliseconds, even if the initial threshold is different. If so, for example, after programming to a certain value, the memory cell threshold can be clamped by the reference cell set threshold in subsequent programming or erasing. This is because the program or erase after enough time for the initial state of the memory cell and the reference cell to be different regardless of the initial threshold value, for example, several tens ⁇ sec to several msec. This is because the characteristic curve becomes common depending on the value of the gate force ripple ratio.In other words, the characteristic curve is applied only depending on the gate couple ratio, and the characteristic curve is different if the gate couple ratio is different. It is possible to beat.
  • the memory cell and the reference cell are simultaneously programmed or erased for a period of time sufficient for the initial state of the memory cell and the reference cell to be different, and the threshold and reset of the memory cell are performed.
  • Self-diagnosis is performed by comparing the threshold value of the reference cell set with the threshold value of the reference cell and confirming that the threshold value of the memory cell is within the threshold value of the reference cell.
  • the initial state of the memory cell differs from that of the reference cell.
  • the sufficient time to become fully assumes that voltage is applied when the memory cell and the reference cell program or erase, obtained is several tens mu ec order one r
  • the threshold value of a memory cell can be arbitrarily set using a reference cell set.
  • the memory cell is an abnormal cell :
  • the programming or erasing speed shows an abnormal value independent of the clickable ratio. Therefore, even though programming or erasing is started at the same time as the reference cell set, after a certain time, the threshold value of the memory cell is compared with the threshold value of the reference cell set. This means that the memory cell can be self-diagnosed as being abnormal. If there is a memory cell exhibiting the bit characteristics, the memory cell can be diagnosed by using this reference cell / reset. It can be estimated that the characteristics have deteriorated.
  • a force for forming a reference cell set by a reference cell having a smaller power ratio than a memory cell and a reference cell having a larger coupling ratio than the memory cell For example, the reference cell needs to have similar characteristics to the memory cell, so the basic structure of the memory cell and the reference cell is the same.
  • Change the power rubble ratio by changing the area of the part facing the control port c
  • a P o 1 y—S i cap type floating gate cell is disclosed in US Pat. This is shown in No. 14 and has a structure as shown in FIG. 4, for example. That is, the n-type source 22 and the drain 23 are formed on the main surface of the p-type substrate 2 ⁇ , and the P o is formed on the channel region 24 therebetween through the gate insulating film 25. 1 Floating gate 26 of y-Si is formed, and Poly-Si cap 27 is formed on it. Poly-Si cap 27 is formed.
  • a via hole 29 made of Po 1 y—S i is formed on the substrate through an interlayer insulating layer 28 made of, for example, ONO (oxide-nitride-oxide). Note that an insulating layer 30 is formed on the side of the floating gate 26.
  • the cell shown in FIG. 4 be a memory cell, and as shown in FIG. 5A, use a Po 1 y-Si cap 27 ′ with a shorter length (that is, a smaller area) than the cap 27.
  • the cell having a small coupling ratio corresponds to the reference cell, and as shown in FIG. 5B, a cell having a Poly-Si cap 27 "longer (that is, larger in area) than the cap 27.
  • FIGS. 7 and 8 show cells with such a structure.
  • FIG. 6 is a plan view showing a part of the cell array of such a cell
  • FIG. 7 is a sectional view taken along line X--X '
  • FIG. 8 is a sectional view taken along line Y--Y'.
  • the floating gate 37 is designed to cover a part of the source 32 and the drain 33 and a part of the element isolation region 36. The specific structure of this cell is shown in FIGS. 7 and 8.
  • the n-type source 32 and the drain 33 are formed on the main surface of the ⁇ -type substrate 31.
  • a gate insulating film 35 is formed on the channel region 34.
  • a floating gate 37 of P o 1 y—Si is formed on the gate insulating film 35, and an interlayer made of, for example, ONO (oxide mononitride monoxide) is further formed thereon.
  • a control / legate 39 made of Po 1 y—Si is formed via an insulating layer 38, and these cells are formed. Are separated by an element isolation region;
  • the area of the floating gate 37 is changed to change the area of the portion where the floating gate 37 and the control port 39 overlap.
  • the capacitance between the floating gate and the control gate can be changed, thereby changing the gate couple ratio.
  • the floating gate may be provided so as to extend in the arrangement direction of the source and the drain. Nor.
  • the following example is an example, and there is a method in which the opening gate is not stacked. In any case, it is simple and effective to adjust the cell characteristics by adjusting the floating gate length.
  • FIG. 9 shows an example in which a 1-poly EPROM according to the 1993 VLSI Symposium 52-A is used as a reference cell.
  • a source 45 and a drain 46 are respectively formed in the portion 2 and a common floating gate 49 is formed on the channel regions 47 and 48 therebetween through a gate oxide film (not shown). Is provided. That is, it has a CMOS structure in which NMOS and PMQS are combined.
  • the voltage Ve is applied to the source 43 and the drain 44 from the power supply 51, the source 4 and the drain 46 are grounded, and the NMOS part is read.
  • the transistor functions as a transistor, and the PMOS portion functions as a control gate portion.
  • Reference numeral 52 denotes a high-concentration region for improving grounding characteristics.
  • the gate couple ratio depends on the amount of threshold ion implantation, the thickness of the gate oxide film, and the floating in the control gate portion (PMOS). It depends on the area of the portion where the gate and the active region overlap, and the area ratio of the portion where the floating gate and the active region overlap in the readout transistor section (NMOS) (hereinafter referred to as the area ratio of the active region).
  • the gate cut ratio can be changed, and thus the threshold can be made different.

Abstract

Cette invention concerne un dispositif de référence capable de traiter des données de niveaux multiples et d'établir simultanément une corrélation suffisante avec les cellules de mémoire, sans pour autant nécessiter un accroissement de surface des circuits. Ledit appareil de référence est doté d'une pluralité d'ensembles de cellules de référence comportant chacun une cellule de référence ayant un taux de couplage entre grilles plus important que celui des cellules de mémoire. Ces ensembles de cellules de référence sont programmés en fonction du nombre d'impulsions qui est un multiple entier du nombre d'impulsions de programme alimentant les cellules de mémoire ou en fonction du temps correspondant au nombre d'impulsions, ce qui permet de fixer un niveau de référence.
PCT/JP1997/002269 1996-07-18 1997-07-01 Dispositif de reference, procede de fixation d'un niveau de reference, procede d'autodiagnostic et memoire semi-conductrice non volatile WO1998003978A1 (fr)

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JP8/189193 1996-07-18
JP18919396 1996-07-18

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6538922B1 (en) 2000-09-27 2003-03-25 Sandisk Corporation Writable tracking cells
US7237074B2 (en) 2003-06-13 2007-06-26 Sandisk Corporation Tracking cells for a memory system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4833514A (en) * 1985-05-01 1989-05-23 Texas Instruments Incorporated Planar FAMOS transistor with sealed floating gate and DCS+N2 O oxide
JPH03134896A (ja) * 1989-10-20 1991-06-07 Fujitsu Ltd 不揮発性半導体記憶装置
JPH08213572A (ja) * 1994-11-30 1996-08-20 Nkk Corp 不揮発性半導体装置およびその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4833514A (en) * 1985-05-01 1989-05-23 Texas Instruments Incorporated Planar FAMOS transistor with sealed floating gate and DCS+N2 O oxide
JPH03134896A (ja) * 1989-10-20 1991-06-07 Fujitsu Ltd 不揮発性半導体記憶装置
JPH08213572A (ja) * 1994-11-30 1996-08-20 Nkk Corp 不揮発性半導体装置およびその製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6538922B1 (en) 2000-09-27 2003-03-25 Sandisk Corporation Writable tracking cells
US6714449B2 (en) 2000-09-27 2004-03-30 Sandisk Corporation Sense amplifier suitable for analogue voltage levels
US6873549B2 (en) 2000-09-27 2005-03-29 Sandisk Corporation Writable tracking cells
US7237074B2 (en) 2003-06-13 2007-06-26 Sandisk Corporation Tracking cells for a memory system

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