WO1998001895A1

WO1998001895A1 - Method of production of semiconductor integrated circuit device

Info

Publication number: WO1998001895A1
Application number: PCT/JP1996/001889
Authority: WO
Inventors: Takashi Yunogami; Takao Kumihashi
Original assignee: Hitachi, Ltd.
Priority date: 1996-07-08
Filing date: 1996-07-08
Publication date: 1998-01-15
Also published as: AU6319796A

Abstract

When the surface of a semiconductor wafer (1) having a predetermined thin film formed thereon is etched by using a plasma etching apparatus equipped with a plasma monitor for monitoring a plasma process in a chamber (10) by detecting the radiation from the plasma, a porous plate (110) having pores having a high aspect ratio is disposed in the optical path of the radiation from the plasma toward the plasma monitor, and the radiation passing through the porous plate (110) is detected by the plasma monitor so as to determine the end point of etching of the thin film.

Description

Method of manufacturing semiconductor integrated circuit device

The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and more particularly to a technology effective when applied to end point detection of a plasma process. Background art

The technology that monitors the progress and end point of etching by measuring the emission spectrum intensity of the reaction product generated by etching is a technology that can accurately detect minute patterns in the deep submicron LSI manufacturing process. This technology is indispensable for dry etching.

For example, in the manufacturing process of 256 Mbit to 1 Gbit DRAM (Dynamic Random Access Memory) manufactured with a design rule of 0.25 or less, when processing the information storage capacitor (capacity) of a miniaturized memory cell. Plasma etching as described above is indispensable. In the process of manufacturing ferroelectric non-volatile memory (Ferro-electric RAM; FRAM), which is being developed in recent years, plasma etching as described above is indispensable when processing information storage capacitors.

256M In bit~ 1 G bit DR AM, as a countermeasure to compensate for the decrease in the accumulated electric load volume due to miniaturization of the memory cell, a capacitor insulating film of the information storage capacitor _{_{T a 2 0 5 B ST (}} (B a , S r) T i 0 ₃ ), it is required to be composed of a high dielectric thin film having a relative dielectric constant of 20 or more and a ferroelectric thin film having a relative dielectric constant of more than 100. Further, F RAIV [case, the capacitor insulating film _{P ZT (P b Z r X} T i,. X 0 3), P b T i ◦ 3, S r T i 0 3, B a T i 0 3 And the like. Therefore, the conductive film for the upper electrode deposited on the capacitive insulating film of DRAM or FRAM is also easy to grow a crystal on the high (strong) dielectric film as described above, and has a high (strong) dielectric film or its structure. It is required to use a conductive material having chemical resistance to the material, such as Pt. When etching a Pt film or a ferroelectric thin film by etching, the etching rate changes every time because the etching characteristics change over time due to the reaction products attached to the inner wall of the chamber of the etching apparatus. And fluctuate. Therefore, when processing these materials by etching, it is necessary to determine the end point of the etching by monitoring the intensity of the plasma emission spectrum each time one wafer is processed.

In the plasma etching process, the end point of the etching is detected by observing the emission of plasma transmitted through a quartz glass window installed on the chamber wall of the etching apparatus by an optical system equipped with a lens and a light sensor. A method is used in which this light is converted into an electric signal and analyzed.

An example of this type of end point detection device is disclosed in Japanese Patent No. 25017164.

The end point detecting device includes a sensor assembly including a plurality of optical sensors responsive to different spectral portions of the optical spectrum generated by the plasma discharge, and a plurality of optical sensors generated from the plurality of optical sensors. A computer system that mathematically combines the digitized data of the optical channels to form a complex function, and changes the R-coefficient of each optical channel so that the etching gas and the etching material are different. It monitors end-point status of multiple processes and other etching conditions.

The sensor assembly includes a probe section extending into the chamber through an opening in the chamber wall of the plasma etching apparatus, and a housing section surrounding the optical sensor and the analog circuit. A cylindrical body with a plurality of holes acting as light guides for transmitting radiation is provided. Each of the plurality of holes has a truncated cone shape having an axis slightly bent at a predetermined angle from the horizontal, and the inner wall thereof reflects electromagnetic radiation of a predetermined frequency.

Japanese Patent Application Laid-Open No. 61-2075853 discloses an apparatus for etching a wafer surface by forming plasma between a lower electrode on which a wafer is mounted and an upper electrode at a ground potential. The reflected light of the light applied to the scribe line on the wafer surface is collected on the image sensor through the mesh of the upper electrode, and the image of the scribe line is formed. A method is disclosed in which an image signal is extracted, and an integrated value thereof is monitored in accordance with an etching process, whereby the end point of the etching is detected with high accuracy and automatically.

Japanese Patent Application Laid-Open No. 59-17072 describes an apparatus for etching a wafer surface by forming plasma between a lower electrode on which a wafer is mounted and an upper electrode at a ground potential. It discloses a technique for preventing reaction products and the like in the chamber from adhering to the surface of a condenser lens installed outside the window of the chamber wall.

The window installed on the chamber wall of this etching device is composed of a pinhole that transmits light, a condensing chamber installed outside the chamber wall, and a lens installed inside the chamber. An inert gas such as nitrogen is introduced into the light chamber to make the inside of the light chamber a positive pressure with respect to the chamber. As a result, the reaction gas generated in the chamber does not flow into the focusing chamber through the pinhole, so that the lens surface can be prevented from being stained, and the end point of the etching can be accurately detected.

Japanese Patent Application Laid-Open No. H5-206076 discloses that an observation window made of quartz glass or the like provided on a chamber wall is provided with an adhering substance for removing reaction products and the like adhering to the inside of the observation window to eliminate fogging. A plasma processing apparatus e provided with a removing means is disclosed. This adhering matter removing means has a heating means such as a ceramic heater formed in the periphery of the observation window along the circumferential direction thereof. If the etching processing is being performed, the adhering matter removing means is driven after the processing. By heating the observation window to a predetermined temperature, reaction products and the like are prevented from adhering to the surface of the observation window.

By the way, in the above-mentioned etching of the Pt film and the ferroelectric thin film, a reaction product having a very large adhesion coefficient and a low vapor pressure is generated in the chamber of the etching apparatus, and the reaction product is formed on the inner wall of the chamber. In addition, since it adheres to the surface of a quartz glass window as well, there is a problem in that the glass window does not transmit the plasma light emission when only a few wafers are processed, and this causes Pt and This has hindered the application of ferroelectric materials to DRAM and FRAM information storage capacitors. If the end point of the etching cannot be detected from the light emission of the plasma, the etching time must be managed and a method of etching for a predetermined time must be adopted. In such a case, the overetching amount has to be set large, that is, the etching time must be set long in order to prevent the etching residue. Ma PT / JP96 / 01889

When the over-etching amount is increased, it is necessary to increase the thickness of the underlying film. For example, when forming an information storage capacitor having a three-layer structure (an upper electrode, a capacitor insulating film, and a lower electrode), the thickness of the capacitor insulating film is increased in order to increase the over-etching amount of the conductive film for the upper electrode. The thickness of the lower electrode conductive film is increased to increase the amount of over-etching of the capacitive insulating film, and the thickness of the base insulating film is increased to increase the over-etching amount of the lower electrode conductive film. Need to be thicker.

When the thickness of each film is increased in this manner, the following adverse effects occur.

(1) The area of the memory cell increases.

(2) The thicker the insulating film, the lower the access speed to the memory cell.

(3) It is technically difficult to make the ferroelectric film thick β.

(4) As the thickness of the underlying insulating crotch increases, connection holes (connection holes) having a high aspect ratio must be formed in this insulating film. Accordingly, it becomes difficult to embed a metal such as A1 or TIN in the connection hole.

(5) When depositing an insulating film on top of an information storage capacitor, the power barrier of the insulating film is reduced due to a large base step. In addition, the coverage of the conductive film for wiring deposited on the insulating film is also reduced.

An object of the present invention is to reliably determine the end point of etching from emission of plasma even in the case of performing etching accompanied by generation of a reaction product even when the adhesion coefficient is large L, the reaction product or the vapor pressure is low, and the reaction product is generated. It is to provide the technology that can do it.

The above and other objects and novel features of the present invention will become apparent from the description of the specification and the accompanying drawings. Disclosure of the invention

A method of manufacturing a semiconductor integrated circuit device according to the present invention includes: a plasma processing unit configured to form a plasma near a semiconductor wafer to perform a plasma processing on a surface of the semiconductor wafer; When etching the surface of a semiconductor wafer on which a predetermined thin film is formed by using an etching apparatus having a plasma monitor for monitoring the state of the thin film, at least a reaction generated in the plasma processing unit by the etching of the thin film. The source side of the product has a high aspect ratio A pore collecting plate formed with a plurality of pores is arranged on an optical path of light emission of the plasma incident on the plasma monitor, and light emission of the plasma transmitted through the hole collecting plate is detected by the plasma monitor. It is something to do. As a result, the plasma emission can reach the plasma monitor without being blocked by the reaction product, so that the adhesion coefficient is large, the reaction product and vapor pressure are low, and etching involving the generation of the reaction product occurs. In this case, the end point of the etching can be reliably determined.

In the present application, a semiconductor integrated circuit device includes a TFT liquid crystal, and a wafer includes a substrate used for manufacturing a TFT liquid crystal. In addition, “about the same” for numerical values, etc., refers to a range of about 1 to 4 times as large as the one to be compared. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a main part configuration diagram of a plasma etching apparatus used in the first embodiment of the present invention, FIG. 2 is an enlarged perspective view of a thin tube assembly attached to the plasma etching apparatus shown in FIG. 1, and FIG. FIG. 4 is an explanatory view showing a method of manufacturing a thin tube aggregate plate, FIG. 4 is a plan view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention, and FIG. FIG. 6 is a sectional view of a principal part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to one embodiment. FIG. 6 is a principal part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 7 is a sectional view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device [B] according to a first embodiment of the present invention. FIG. 9 is a sectional view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device. FIG. 10 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to a first embodiment. FIG. 10 is a sectional view of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 11 is a partial sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 12 is a first embodiment of the present invention. FIG. 13 is a cross-sectional view of a main part of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device as an example. FIG. 13 is a main part of a semiconductor substrate showing a method for manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 14 is a sectional view of a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 15 is a cross-sectional view of a main part of a semiconductor substrate illustrating a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. Sectional view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 17 shows a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 18 is a sectional view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 19 is a sectional view of the first embodiment of the present invention. FIG. 20 is a cross-sectional view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to an embodiment; FIG. 20 is an enlarged cross-sectional view of a main part of a thin tube collecting plate; FIG. FIG. 22 is a graph showing the change over time in the intensity of the plasma. Reference numeral 23 denotes a cross section of a main part of a semiconductor substrate in a method of manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention. 124 denotes a semiconductor integrated circuit according to the first embodiment of the present invention. FIG. 25 is a cross-sectional view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device K according to a first embodiment of the present invention. FIG. 26 is a plan view of a principal part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention. FIG. 27 is a third embodiment of the present invention. FIG. 28 is a fragmentary plan view of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to a third embodiment of the present invention; FIG. 29 is a cross-sectional view of a main part of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device according to a fourth embodiment of the present invention. FIG. 30 is a fifth embodiment of the present invention. Fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a semiconductor integrated circuit device is, 3 1 is a sectional view showing another embodiment of a capillary collection plate. BEST MODE FOR CARRYING OUT THE INVENTION

The present invention will be described in more detail with reference to the accompanying drawings in order to explain it in more detail. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and a repeated description thereof will be omitted.

First embodiment

FIG. 1 is a main part configuration diagram of a plasma etching apparatus used in the present embodiment. Alumite coating which is a plasma processing unit of plasma etching equipment 100 A flat lower electrode 102 and an upper electrode 103 are arranged inside a chamber 101 made of A1 which has been subjected to the brushing. The lower electrode 102 connected to the RF power supply 104 is connected to a part of the upper electrode 103 connected to the ground potential _c, which is the stage on which the semiconductor substrate (wafer) 1 as a sample is mounted. A gas introduction pipe 105 for supplying a reaction gas such as chlorine or a plasma stabilizing gas such as Ar is provided in a chamber 101.

Around the lower electrode 102, a wall plate 106 for preventing a reaction product 118 of the plasma etching from adhering to the inner wall of the channel 101 is provided. A baffle plate 107 is provided below the lower electrode 102. The wall plate 106 has such a structure that it can be easily removed from the chamber 101 in order to periodically remove the reaction product 118 attached to its inner wall. At the -end of the channel 101, a vacuum pump 108 for evacuating the inside of the chamber 101 to a pressure of is provided. A rotating magnet 109 is provided outside the chamber 101, and an upper electrode 100 is formed by a magnetic field generated by the rotating magnet 109 and an RF bias applied by an RF power source 104. A high density plasma 114 is formed between 3 and the lower electrode 102.

On the wall surface of the wall plate 106 provided around the gate electrode 102, a thin disk-shaped thin tube collecting plate 110 is attached by fixing means such as a clamp 111. As will be described in detail later, the thin tube collecting plate 110 is a thin slice of a bundle of fine quartz glass tubes, and the light that hits the surface is mainly transmitted through the inside of each fine glass tube and the back side. It is structured to reach. A transparent quartz glass window 112 is attached to a wall surface of the champer 101 facing the thin tube collecting plate 110 by fixing means such as a clamp 111. An O-ring 113 is fitted in a gap between the quartz glass window 112 and the wall surface of the chamber 101 so that the airtightness inside the chamber 101 is maintained.

Outside the quartz glass window 112, the emission of plasma 114 formed between the lower electrode 102 and the upper electrode 103 during plasma etching is monitored to determine the end point of the etching, etc. A plasma monitor is provided. This plasma monitor section has the intensity of plasma emission transmitted through the thin tube collecting plate 110 and the quartz glass window 112. It consists of a light emission detection monitor 115 that detects the degree of light, a monochromator 116 that selects light of a desired wavelength out of the plasma light emission, and a pen recorder 117 that records the light emission intensity of the plasma.

FIG. 2A is an enlarged view of the thin tube collecting plate 110 attached to the wall plate 106 of the plasma etching apparatus 100. Although not particularly limited, the thin tube collecting plate 110 is made of a quartz glass disk having a diameter of 25 mm and a thickness of 0.24 mm, and has a diameter of 1 mm penetrating to the back surface on the front surface. Many 0 pores are formed. Each of these pores is composed of a quartz glass capillary as shown in Fig. 2 (b). As the thin tube collecting plate 110 having such a structure, for example, "Hamamatsu Photonics Co., Ltd. (HAMAMATSU PHOTONICS KK)" manufactured by "Micro Caviar Replate (registered trademark), Model J5 () 22-n" or the like is used. can do.

In order to manufacture the thin tube collecting plate 110, as an example, a large number of elongated columnar quartz glass thin tubes as shown in FIG. 3 (a) are prepared. Next, as shown in Fig. 3 (b), these quartz glass tubes are bundled and bonded to form a glass tube assembly. For the bonding between the glass tubes, molten glass of the same material as the tubes is used. Next, as shown in FIG. 3 (c), the glass thin tube aggregate is thinly sliced into a thin tube aggregate plate 110.

The thin tube made of glass (see Fig. 2Cb) that constitutes the pores of the thin tube collecting plate 110 has a ratio (aspect ratio) of the length (L) to the diameter (ø) of 1 Should be large, and in practice, the aspect ratio should be at least 5 or more, preferably as high as possible. The higher the aspect ratio of the glass tube, the lower the probability of reaction product particles of plasma etching coming into the tube, so that it is possible to more reliably prevent the light transmittance from lowering. On the other hand, if the aspect ratio is set to about 1 or less, the reaction product accumulates inside the tubule after a short use, and the light does not pass through. The thin tube collecting plate 110 used in the present embodiment is obtained by slicing an aggregate of glass thin tubes having a diameter of 10 m to a thickness of 0.24 mm (= 240 m). The aspect ratio is 24.

The diameter (ø) of the thin tube is also an important factor. If the diameter (ø) force is 1 m or less, the thin tube may be blocked by the reaction product attached near the opening. On the other hand, If the diameter (Φ) is L or a thin tube, the length (L) must be increased in order to ensure a sufficient aspect ratio. Considering that the thin tube collecting plate 110 is attached to the inside of the chamber 101 of 00, the thickness of the thin tube collecting plate 110 is preferably several cm or less. Therefore, the capillary has a diameter (ø) of 1π! It should be within the range of ~ 1 mm.

On the other hand, when specified in relation to the wavelength (λ) of the plasma emission, the diameter (Φ) of the glass capillary is desirably at least as large as this wavelength (λ) (0 ≥). Further, in relation to the Ψ-uniform process (1) of the reaction product particles, it is desirable that the diameter (ø) is equal to or less than the average free process (1) (0≤1).

In addition, the aperture ratio of the narrow tube plywood 110 (the ratio of the area of the holes to the area of the light receiving section) is another factor to be considered. If the aperture ratio is small, the amount of light transmitted through the thin plate decreases. Therefore, a high-numerical-diameter thin-tube assembly plate that ensures an aperture ratio of at least about 10% or more should be used.

The thin tube collecting plate 110 is not limited to the one using the quartz glass tube as described above, and may be configured as a composite plate of fine tubular objects made of various materials. Further, the present invention is not limited to the dense structure of tubular objects. For example, a thin plate made of a metal such as glass, A], or Cu is used to form a large number of fine holes to form a pore aggregate plate. Is also good. At this time, the diameter and the aspect ratio of the pores and the opening ratio of the pore-aggregating plate must satisfy the conditions described above.

Next, a description will be given of a manufacturing method of this embodiment applied to a DRAM which is a kind of semiconductor memory.

FIG. 4 is a plan view showing a layout of a memory cell of the DRAM of the present embodiment. This DRAM memory cell employs a two-intersection cell and a CB (Capacitor Over Bitlinc) structure in which a capacitance element for storing information is arranged above a bit line. The transistor of each memory cell (MISFET for memory cell selection) is connected to the peripheral circuit via the bit line BL. The bit line BL is connected to one of the semiconductor regions 8 (source region, drain region) of the memory cell selection MISFET through the connection hole 14. The operation of the memory cell selection MISFET is controlled by the word line WL (gate electrode 6). This word line WL (gate electrode 6) is connected to peripheral circuits Have been. The information storage capacitive element C disposed above the bit line BL is connected to the other one of the semiconductor regions 8 (source region and drain region) of the MISFET for selecting a memory cell through the connection hole 13. The information storage capacitor C is connected to the peripheral circuit via the plate electrode 26.

The first feature of this planar layout is that one plate electrode 26 is arranged for two word lines WL. With such a layout, the capacity of the plate electrode 26 can be made smaller than that of a normal DRAM, so that the potential of the plate electrode 26 can be easily controlled by a peripheral circuit. The number of plates and poles 26 may be one for one word line WL, or one for three word lines WL. However, if the number of plate electrodes 26 with respect to the word line WL increases, it becomes difficult to increase the degree of integration, and if the number decreases, the capacitance a of the plate electrode 26 increases and control by peripheral circuits becomes difficult. The appropriate number of plate poles 26 varies depending on the use of the DRAM.

The second feature of this planar layout is that the plate electrode 26 extends in the same direction as the word line WL (gate electrode 6). Thus, when the potential of the plate electrode 26 is controlled by the peripheral circuit, the potential can be controlled in synchronization with the potential of the lead line WL.

To manufacture this DRAM memory cell, first, as shown in FIG. 5 (a cross-sectional view taken along the line A—A ′ in FIG. 4), a semiconductor substrate 1 made of ρ · single-crystal silicon is prepared. After a field oxide film 2 is formed on the surface by a selective oxidation (LOCOS) method, a p-type impurity (B) is ion-implanted into the semiconductor substrate 1 to form a p-type well 3. Then, after p-type impurities (B) are ion-implanted into the p-type well 2 to form p-type channel stopper debris 4, the active region of the p-type well 3 surrounded by the field oxide film 2 is formed. A gate oxide film 5 is formed on the surface by a thermal oxidation method.

Next, as shown in FIG. 6, a gate electrode 6 (a common line WL) of the memory cell selecting MISFET is formed. The gate electrode 6 (lead line WL) is formed, for example, by depositing a polycrystalline silicon film on the semiconductor substrate 1 by a CVD method, then depositing a TiN film and a W film by a sputtering method, and further forming a cap insulating film. Silicon nitride film 7 is deposited by plasma CVD, and then these films are etched using a photoresist as a mask. Is formed by patterning. The polycrystalline silicon film that forms part of the gate electrode 6 (word line WL) is doped with an n-type impurity (P) to reduce its resistance.

Next, as shown in FIG. 7, an n-type impurity (P) is ion-implanted into the p-type well 2 and the n-type impurity (P) of the MIS FET for memory cell selection is injected into the p-type well 2 on both sides of the gate electrode 6 (word line WL). Form semiconductor regions 8, 8 (source region, drain region). Next, as shown in FIG. 8, a side wall spacer 9 is formed on the side wall of the gate electrode 6 (word line WL). The sidewall spacer 9 is formed by processing a silicon nitride film deposited on the gate electrode 6 (lead line WL) by a plasma CVD method by anisotropic etching.

Next, as shown in Fig. 9, a silicon oxide film 10 and a BPSG (Boron-doped Phospho Silicate Glass) film 11 are deposited on the top of the MISFET for memory cell selection by the CVD method. The BPS G film 11 is polished by a polishing (Chemical Mechanical Polishing; CMP) method to flatten its surface.

Next, as shown in FIG. 10, after depositing a polycrystalline silicon film 12 on the BP SG film 11 by CVD method, using a photoresist as a mask, the polycrystalline silicon film 12 and the BP film 1 are deposited. 1. By etching the silicon oxide film 10 and the gate oxide film 5, a connection hole 13 is formed above one of the source region and the drain region (n-type semiconductor region 8) of the MISFET for memory cell selection. Then, a connection hole 14 is formed on the other (n-type semiconductor region 8). At this time, the silicon nitride film 7 formed on the gate electrode 6 (word line WL) of the memory cell selection MISFET and the silicon nitride film 9 formed on the sidewalls are slightly etched. Therefore, the connection holes 13 and 14 having a small diameter can be formed by self-alignment (self-alignment) without providing a margin for matching the connection holes 13 and 14 with the gate electrode 6 (word line WL).

Next, as shown in FIG. 11, a plug 15 of polycrystalline silicon is embedded in the connection holes 13 and 14. The plug 15 is formed by depositing a polycrystalline silicon film on the polycrystalline silicon film 12 by the CVD method and removing the polycrystalline silicon film and the polycrystalline silicon film 12 by etch-back. I do. Polycrystalline silicon composing plug 15 The film is doped with an n-type impurity (P). The plug 15 may be formed by embedding, for example, TiN, W, Ti, Ta, or the like, in addition to polycrystalline silicon.

Next, as shown in FIG. 12, a silicon oxide film 16 is deposited on the BPSG film 11 by a CVD method, and then the silicon oxide film 16 on the connection hole 14 is etched by using a photoresist as a mask. After the removal, a bit line BL is formed on the connection hole 14 as shown in FIG. The bit line BL is formed by depositing a TiN film and a W film on the silicon oxide film 16 by a sputtering method, and further depositing a silicon nitride film 17 serving as a cap insulating film by a plasma CVD method. These films are patterned and formed by etching using a photoresist as a mask.

Next, as shown in FIG. 14, a side wall spacer 18 is formed on the side wall of the bit line BL. The side walls 18 are formed by processing a silicon nitride film deposited on the bit line BL by a plasma CVD method by anisotropic etching. Next, as shown in FIG. 15, a BPSG film 19 having a thickness of about 300 nm is deposited on the bit line BL by a CVD method and reflowed. By etching the silicon oxide film 16, a connection hole is formed above the connection hole 13 formed above the other of the source region and the drain region (the n-conducting region 8) of the memory cell selecting MI SFET Qt. Form 20. At this time, since the silicon nitride film 17 on the upper part of the bit line BL and the sidewall spacers 18 on the side walls serve as etching stoppers, the connection holes 20 are self-aligned similarly to the connection holes 13 and 14. (Self-aligned).

When the connection hole 20 is formed by dry etching, a method used in the conventional technology, that is, a method of controlling the etching time and etching for a predetermined time is used as a method of determining the end point of the etching. Alternatively, the light emission of the plasma may be monitored to determine the etching end time. At this time, the plasma etching apparatus 100 shown in FIG. 1 may be used.

Next, as shown in FIG. 16, a plug 21 is embedded in the connection hole 20. The plug 21 is formed by depositing a TiN film and a W film on the 8-30 film 19 by, for example, a sputtering method, and then etching back these films. The plug 21 can also be formed by embedding polycrystalline silicon, TiN, W, Ti, Ta, or the like. Next, an information storage capacitor is formed above the plug 21. To form the information storage capacitor element, first, as shown in FIG. 17, a barrier metal 22 is deposited on the BPSG film 19 using a sputtering method or the like, and then a barrier metal 22 is deposited on the parietal metal 22. A Pt film 23a having a thickness of about 175 nm is deposited by a sputtering method. Although the parity metal 22 is not always necessary, it is effective for suppressing the diffusion of the lower electrode material (Pt) of the information storage capacitor. As the material of the barrier metal 22, TiN, Ti, or the like is used, and the film thickness is about 20 ηιη.

Next, as shown in FIG. 18, after depositing the capacitive insulating film 24 of the information storage capacitive element on the Pt film 23a, the upper electrode material of the information storage capacitive element is deposited on the capacitive insulating film 24. Deposit Pt film 25a. The capacitor insulating film 24 is formed by depositing BST (CBa, Sr) TiO ₃ ) as a strong dielectric material by a sputtering method, and has a film thickness of about 250 nm. The Pt film 25a is deposited by a sputtering method and has a thickness of about 100 nm. Depending on the material of the capacitive insulating film 24, crystallization heat treatment may be performed after film formation, if necessary.

In this embodiment, a case will be described in which Pt is used as an electrode material of an information storage capacitor and BST is used as a capacitor insulating material. However, the present invention is not limited thereto.

Considering also be applied to such F RAM, other P t as the electrode _{material, I r, I r 0 2} , Rh, Rh_〇 _2, O s, O S_〇 _2, Ru, Ru_〇 _2, Re, R E_〇 _3, Pd, can be used a u or a laminated film. By such Ru_〇 ₂ and I 1 "0 ₂ is deposited using 1 ^ 1 MOCVD method, a good film coverage can and forming child. Also, high barrier property against oxygen thereon Ru, It is possible to improve the oxidation resistance of the film by laminating Ir, etc. Furthermore, if oxidation at the interface of the capacitive insulating film can be suppressed, W, A], T i N , Ta, Cu, Ag, or a laminated film of these materials can also be used.

Other BS Ding as a capacitor insulating film material, T a ₂ 0 ₅ is deposited by CVD, or the like may be used oxide silicon or silicon nitride. The various ferroelectric materials, for example, P b Z R_〇 _{_{3, L i Nb0 3, B}} i 4 T i 3 〇 _{_{I2, B aMgF 4, PLZT,}} Y 1 (S r B i, (N b, T a) , O ₉ ) can also be used. These ferroelectric materials are In addition to sputtering, MOCVD, sol-gel, laser ablation, etc. can be used for deposition.

Next, as shown in FIG. 19, a photoresist 27 is formed on the Pt film 25a, which is an upper electrode material, and then the plasma etching apparatus 100 shown in FIG. 1 is used. Then, the Pt film 25a, the capacitive insulating film 24, the Pt film 23a and the barrier metal 22 are dry-etched.

In order to perform this dry etching, first, a semiconductor substrate (wafer) 1 is placed on the lower electrode 102 of the plasma etching apparatus 100, and then chlorine is introduced into the chamber 101 through a gas introduction pipe 105. Introduce 40 scans of gas and 10 scans of Ar gas, and use a vacuum pump 108 to reduce the air / air inside the chamber 101 to 5 mTorr (the mean free path of the reaction product particles is (). ~ Several tens of cm). The temperature of the gate electrode 102 on which the semiconductor substrate 1 is mounted is set to 30 ° C. Then, a magnetic field formed by the rotating magnet 109 rotating 24 times per minute and an RF power supply 104 applied between the upper electrode 103 and the lower electrode 102 via the RF power source 13.56 Plasma 114 is generated by an RF bias of M Hz / 1200 W, and the Pt film 25a is etched by ions and radicals generated in the plasma 114. At this time, of the plasma emission transmitted through the thin tube collecting plate 110 attached to the wall surface of the wall plate 106 and the quartz glass window 112 attached to the ^ surface of the chamber 101, The light of the desired wavelength is selected by the monochromator 1 16, the luminescence intensity is detected by the luminescence detection monitor 1 15 and recorded on the pen recorder 1 17.

As the etching of the Pt film 25a progresses, a large amount of the reaction product 118 having a large adhesion coefficient and a low vapor pressure is deposited on the surface of the upper electrode 103 and the inner wall of the wall plate 106. Adhere to. At this time, as shown in FIG. 20, the reaction product 118 also adheres to the surface of the thin tube collecting plate 110 attached to the wall surface of the wall plate 106, but the Since the reaction product 118 is unlikely to fly inside the glass tube with a high ratio, the plasma emission passes through the inside of the glass tube without being hindered by the reaction product 118, and the quartz glass window The light can pass through 112 and reach the plasma monitoring means. FIG. 21 is a graph showing the temporal change of the light emission intensity of the plasma transmitted through the thin tube collecting plate 110 and the quartz glass window 112. Etch 150 wafers as shown However, the decrease in luminescence intensity was about 40% even after running, and it was possible to maintain the intensity sufficiently higher than the luminescence intensity detection limit of the monitoring means (marked with 〇). If this graph is extrapolated, it can be estimated that about 100,000 wafers (40,000 lots) can be continuously detected for the end point. On the other hand, when etching was performed without attaching the thin tube collecting plate 110 (mark), only three wafers were etched, and a large amount of reaction products adhered to the surface of the quartz glass window 112 to emit light. The intensity attenuated to 1Z100 or less, making it impossible to detect the emission intensity.

The end point of the etching of the Pt film 25a can be determined from the waveform of a wavelength of 406 nm corresponding to the light emission considered to be that of Ti shown in FIG. When the Pt film 25a in the region not masked by the photoresist 27 is etched and gradually disappears, and the BST film, which is the insulating film 24 of the lower debris, begins to be etched, the-component of the film is removed. Since the light beams fly into the plasma and emit light, the intensity of light having a wavelength of 406 nm increases. Then, as the emission area of the BST film increases, the intensity of light having a wavelength of 406 nm increases, and the emission intensity becomes constant when the Pt film 25a completely disappears and the BST film is exposed. Become. Therefore, this point is determined to be the end point of the Pt etching.

Thereafter, the capacitance insulating film 24, the Pt film 23a, and the barrier metal 22 are successively dry-etched in the manner described above to form the information storage capacitance element C as shown in FIG. .

According to the above-described dry etching method, it is possible to accurately determine the etching end point of each thin film constituting the information storage capacitance element C. Therefore, when forming the information storage capacitance element C, the base film (BPSG film) is formed. This eliminates the problem of overcutting 9). Also, since the material of each thin film is different, it is desirable to change the etching conditions for each thin film from the viewpoint of the selectivity with the throughput-to-resist, but the etching conditions may be changed at any time by the above dry etching method. Can be known exactly. Furthermore, even if the number of processed wafers is large, the end point can be determined accurately, so that the maintenance time of the end point determining means is shortened, so that the operation rate of the apparatus is improved, and the throughput can be increased.

Conventionally, the dry etching method described above is used, and in the case of no dry processing, three wafers are processed. The maintenance of the etching equipment was required every time, but it took about 7 hours to shut down the equipment and start up the maintenance equipment by mechanical polishing such as a quartz glass window. The etching time was about 3 minutes for JF-taste, but it took 7 hours to process one wafer. On the other hand, after the introduction of the dry etching method, it is possible to process 40 lots (100 pieces) of wafers in a single maintenance, and to increase throughput by 50 times or more. Improvements have been achieved.

Next, after removing the photoresist 27 at the fin of the information storage capacitor C by asking, as shown in FIG. 24, a lift such as a BPSG film is used to protect the information storage capacitor C. An insulative insulating film 28 is deposited, and its surface is f-supported by chemical mechanical polishing (CMP) to expose the surface of the upper electrode 25. In this case, complete planarization is not indispensable, but it is preferable to planarize the insulating film 28 as much as possible in order to increase the reliability of the wiring formed in the h portion in a later step. In order to enhance the protection effect of the information storage capacitor, a thin film made of an oxide such as Ti, Sr, or Ba compatible with the constituent material of the information storage capacitor C is deposited, and then the insulating film 28 May be deposited. Further, a CVD / silicon oxide film using an organic Si gas may be used instead of the insulating film 28 having a riff opening, or an organic insulating material such as polyimide resin may be used. The planarization of the insulating film may be performed by an etch / etch method instead of the CMP method, and may not be particularly performed when the step due to the information storage capacitor C is small.

Next, as shown in FIG. 25, a plate electrode 26 common to a plurality of memory cells is formed on the insulating film 28. As the plate electrode material, various conductive materials used in the conventional silicon LSI process, such as a polycrystalline silicon film and a W film, can be used. If the base is sufficiently flat, use a conductive material that can be formed by sputtering. If the base has a step, use a conductive material that can be formed by CVD. When the deposited conductive film is dry-etched to form a plate electrode 26, plasma emission is monitored by using the plasma etching apparatus 100 shown in FIG. 1 to obtain an etching end time. You may do it. At this time, there is no danger that a large amount of reaction products will adhere to the surface of the quartz glass window 112 due to a small adhesion coefficient of the reaction products of the etching or a high vapor pressure. In such a case, it is not always necessary to use the capillary tube plywood 110.

Through the above steps, the DRAM memory cell of this embodiment is substantially completed. In an actual DRAM, it is necessary to form about two more layers of wiring above the plate electrode 26 to connect the memory cell and peripheral circuits, and to package the semiconductor substrate 1 with resin or the like. Needless to say, it is necessary.

Second example

FIG. 26 is a plan view showing the layout of the memory cell of the DRAM of this embodiment. C The memory cell of this DRAM is composed of two intersection cells and a C〇B in which an information storage capacitor is arranged above the bit line. Structure and adopted. The transistor of each memory cell (MISFET for selecting a memory cell) is connected to the peripheral circuit via a bit line BL. The bit line BL is connected to one of the semiconductor regions 8 (source region and drain region) of the MISFET for memory cell selection through the connection hole 14. Operation of the memory cell selecting MIS FET is controlled by a word line WL (gate electrode 6) _c The word line WL (gate electrode 6) is connected to the peripheral circuit. The information storage capacitor C arranged above the bit line BL is connected to the other of the semiconductor regions 8 (source region and drain region) of the memory cell selection MISFET through the connection hole 13. The information storage capacitor C is connected to the peripheral circuit via the plate electrode 26.

The first feature of this planar layout is that one plate electrode 26 is arranged for one bit line BL. With such a layout, the capacitance of the plate electrode 26 can be made smaller than that of a normal DRAM, so that the potential of the plate electrode 26 can be easily controlled by a peripheral circuit. The number of plate electrodes 26 may be one for two or more bit lines BL. However, when the number of the plate electrodes 26 with respect to the bit line BL is reduced, the capacitance of the plate electrode 26 is increased, so that control by the peripheral circuit becomes difficult. The optimal number of plate ^ poles 26 depends on the application of DRAM.

The second feature of this planar layout is that the plate electrode 26 extends in the same direction as the bit line BL. This makes it possible to control the potential of the plate electrode 26 in synchronism with the potential of the bit line BL when controlling the potential of the peripheral circuit. Becomes

The memory cell of the DRAM of this embodiment can also be manufactured by the same method as in the first embodiment.

Third embodiment

27, _c characterized in this plane Reiau Bok is a plan view showing a layout of a memory cell of the DRAM of the present embodiment controls the information storing capacitor C in one play Bok electrode 26 with a larger area That is. With such a layout, it becomes easy to apply the reference potential required for the DRAM operation to the information storage capacitor C. In addition, if the driving capability of the peripheral PI path is made sufficiently large, operation as a nonvolatile memory is also possible. The number of the information storage capacitance elements C controlled by the plate name 26 may be adjusted according to the use of the memory.

FIG. 28 is a cross section taken along line AA ′ of FIG. 27! The structure and manufacturing capability of the DRAM memory cell of the present embodiment are basically the same as those of the DRAM memory cell of the first embodiment except for the plate electrode 26. The processing of the plate ¾ electrode 26 is performed in the same manner as in the first embodiment, and may be adjusted to a required size.

Fourth embodiment

The structure of the memory cell of this embodiment will be described with reference to FIG. This figure is a cross-sectional view showing a stage of creating one transistor and one capacity memory until the capacity is completed. PZT, a ferroelectric material, is used for the capacitive insulating film of the capacitor, and Pt is used for the capacitive electrode.

In this memory, transistors are electrically separated by a field oxide film 2 on a semiconductor substrate 1. The transistor is an MISTFET composed of a semiconductor region 8 (source region and drain region), a gate electrode 6 of polycrystalline silicon, and a gate oxide film 5 thereunder. After the upper part of the MISFET is flattened using the BP30 film 11, a capacity is formed. The capacitor and the MISFET are electrically connected by a polycrystalline silicon plug 15 embedded in the-part of the BPSG film 11. The capacitor is a three-dimensional capacitor formed on the lower electrode 23 of Pt. The capacitor insulating film 24 of PZT is formed on the lower electrode 23, and the upper electrode of Pt is formed on the capacitor insulating film 24. 23 is formed to form a three-dimensional capacity. Also at the bottom In order to suppress the diffusion of Pt from the electrode 23 into the plug 15, a TiN parametal 22 is provided between the lower electrode 23 and the plug 15.

In order to actually operate as a memory, in addition to those shown in this figure, wiring (usually two layers of wiring are required above the upper electrode 25) and memory operation are controlled to Peripheral circuits for exchanging signals are required, but these are well-known structures and are not directly related to the present embodiment, so description thereof will be omitted.

Even in the case of a memory using such a three-dimensional capacitor, accurate end point determination can be performed when the lower electrode 23 and the barrier metal 22 are etched by using the plasma etching apparatus of the first embodiment. Can be.

The lower electrode 23, the capacitive insulating film 24, and the fin electrode 25 can be formed using the various materials described in the first embodiment.

Fifth embodiment

The method for manufacturing the memory cell of this embodiment will be described with reference to FIG.

In this embodiment, after the gate electrode 23 is formed, a planarization process is performed using the insulating film 28, and thereafter, the capacitive insulating film 24 of PZT and the upper electrode 25 of Pt are formed. Except for this, the manufacturing method is the same as that of the fourth embodiment. Even in the case of a memory using such a three-dimensional capacity, by using the plasma etching apparatus of the first embodiment, an accurate end point can be determined when etching the gate electrode 23 and the barrier metal 22. be able to.

Sixth embodiment

FIG. 31 is a sectional view showing another embodiment of the thin tube collecting plate. This thin tube collecting plate is formed by collecting tapered thin tubes 1 19 having a taper such that the diameter of the light receiving section is larger than the diameter of the other end and bundling them with quartz 120 to form a thin tube collecting plate. It is structured to be attached to the quartz glass window 1 1 2. The light emission of the plasma enters from the large diameter side of the thin tube 119, passes through the quartz window 112, and is guided to the plasma monitor. In this way, by adopting a structure in which the thin tube 119 has a taper angle, the light emission of the plasma is collected while being reflected on the inner wall surface of the thin tube 119, so that the light receiving efficiency can be improved. . In addition, even when a reaction product adheres to the inner wall of the thin tube 119 during dry etching of Pt, the variation in the light receiving efficiency is small because the adhered substance acts as a light reflection layer. No.

The thin tubes 1 19 can be made, for example, by stretching a quartz glass tube. The thin tube 119 may be made of only quartz glass, but the inner wall of the thin tube 119 may be previously thinly coated with a substance having a high reflectance (for example, gold). Further, the thin tube 119 may be formed of metal. In this case, too, it can be created by stretching the metal tube. At that time, metal may be used instead of quartz 120 as a support as a support for binding the metal tubes.

As described above, the invention made by the inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and it can be said that various modifications can be made without departing from the gist of the invention. Not even.

The present invention is not limited to the etching using the magnetron RIE type plasma etching apparatus as shown in the above-described embodiment, but is applicable to various types of plasma etching apparatuses such as ECR, helicon, ICP, TCP, etc. It can be applied to etching. Industrial applicability

As described above, according to the method for manufacturing a semiconductor integrated circuit device of the present invention, since the emission of plasma can reach the plasma monitor of the etching apparatus without being interrupted by the reaction products, the adhesion coefficient is large, This method is suitable for use in processes where it is necessary to accurately determine the end point of etching involving the generation of a reaction product with low L on a substance or vapor I.

Claims

The scope of the claims

1. A plasma processing unit that forms a plasma near the semiconductor wafer and performs a plasma process on the surface of the semiconductor wafer, and a plasma monitor unit that detects light emission of the plasma and monitors the state of the plasma process. When etching the surface of a semiconductor wafer on which a predetermined thin film has been formed using an etching apparatus, at least a source hole of a source of a reaction product generated in the plasma processing section by the etching of the thin film is opened. A method for manufacturing a semiconductor integrated circuit device, comprising: arranging a pore collecting plate formed with a plurality of pores having a power ratio on an optical path of emission of the plasma incident on the plasma monitor.

2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the porous plywood is a tubular assembly plate formed by joining a plurality of tubular materials having a fine diameter. Of manufacturing a semiconductor integrated circuit device.

3. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein the self-tubular assembly is a thin glass tube assembly formed by joining a plurality of thin glass tubes. A method for manufacturing a circuit device.

4. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein an aspect ratio of the pores formed in the pore aggregation plate is 5 or more. Device manufacturing method.

5. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the ratio of the area of the pores to the area of the light receiving portion of the pore collecting plate is 10% or more. Of manufacturing a semiconductor integrated circuit device.

6. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the pores formed in the pore aggregation plate have a diameter of a source-side opening end of the reaction product at the other end. A method for manufacturing a semiconductor integrated circuit device, characterized in that the size is large.

7. A method for manufacturing a semiconductor integrated circuit device, comprising the following steps:

(a) depositing a predetermined thin film on the surface of a semiconductor wafer,

(b) a plasma processing section for forming a plasma near the semiconductor wafer and performing a plasma processing on the surface of the semiconductor wafer; and detecting the light emission of the plasma and performing the plasma processing. A plasma monitor for monitoring the state of processing, a plasma monitor disposed on the optical path of light emission of plasma before entering the plasma monitor, and a source side of at least a reaction product generated in the plasma processing unit having a high opening on a source side. Using an etching apparatus provided with a high-numerical-aperture aggregate plate in which a plurality of pores having an aspect ratio are formed, the plasma monitor monitors the end point of the semiconductor wafer while monitoring the end point thereof. Etching the deposited thin film.

8. The method for manufacturing a semiconductor integrated circuit device according to claim 7, wherein the step of etching the thin film is performed by stacking a lower electrode, a capacitor insulating film, and an upper electrode.

—¾A method of manufacturing a semiconductor integrated circuit device, which is a step of forming an element. 9. The method for manufacturing a semiconductor integrated circuit device according to claim 8, wherein the capacitance element is an S element of a DRAM memory cell.

10. The method for manufacturing a semiconductor integrated circuit device according to claim 9, wherein the thin film is a Pt film constituting an upper electrode of the element. Manufacturing method.

11. The method for manufacturing a semiconductor integrated circuit device according to claim 10, wherein the capacitor insulating film below the upper electrode made of the Pt film has a relative dielectric constant of 20 or more. A method for manufacturing a semiconductor integrated circuit device, comprising: a film.

12. A method of manufacturing a semiconductor integrated circuit device, comprising the following steps: (a) depositing a first thin film on a surface of a semiconductor wafer;

(b) a plasma processing unit that forms a plasma near the semiconductor wafer and performs a plasma process on the surface of the semiconductor wafer; a plasma monitor unit that detects light emission of the plasma and monitors a state of the plasma processing; Pre ^ A high-aspect-ratio pore that is located on the optical path of the plasma emission incident on the plasma monitor and at least the source side of the reaction product generated in the plasma processing section is opened. Using a first etching apparatus provided with a high numerical aperture aggregate plate in which a plurality of holes are formed, while monitoring the end point thereof by using a plasma monitor, the above-described process is performed on the surface of the semiconductor wafer. Etching the first thin film,

(c) depositing a second thin film on the surface of the semiconductor wafer; (d) before or after the step (a), by using the first etching apparatus or a second etching apparatus different from the first etching apparatus, by determining the end point by etching for a predetermined time. Etching the second thin film.

13. A method for manufacturing a semiconductor integrated circuit device comprising the following steps:

(a) forming a first thin film directly or indirectly on a main surface of a wafer for manufacturing a semiconductor integrated circuit device;

(b) etching the first thin film into a predetermined shape by etching the wafer on which the first thin film is formed in a gas phase reaction processing vessel by using a gas phase reaction. Turning process,

(c) When monitoring optical information from a reaction gas phase in the vicinity of the wafer involved in self-etching or transmitted through at least a portion thereof, the gas phase reaction between the reaction gas phase and a light detection unit is performed. The processing vessel has an inner diameter large enough to allow at least the observation light to pass through, and an aspect ratio large enough to substantially prevent or suppress the passage of particles that cause undesired deposition. By placing a microtube collecting plate in which a very large number of microtubes are densely arranged, at least the reaction gas phase side is opened, and observing light transmitted through the microtube collecting plate, the end point of the etching is determined. The process of detecting.

14. The method for manufacturing a semiconductor integrated circuit device according to claim 13, wherein the inside diameter of the microtube is a mean free path of the particles causing the undesired deposition in the gas-phase reaction processing container. A method for manufacturing a semiconductor integrated circuit device, which is sufficiently smaller than the above.

15. The method for manufacturing a semiconductor integrated circuit device according to claim 14, wherein the length of the fine tube is such that the particles causing the undesired deposition are mean free in the gas phase reaction processing container. A method for manufacturing a semiconductor integrated circuit device, wherein the method is equal to or shorter than a process.

16. The method for manufacturing a semiconductor integrated circuit device according to claim 15, wherein an inner diameter of the microtube is sufficiently larger than a wavelength of the observation light. Method.

17. The method for manufacturing a semiconductor integrated circuit device according to claim 16, wherein the area of the inner diameter portion of the fine tube is substantially the same as the area of the entire other portion between the tube wall and the tube. production method _c Kamata semiconductor integrated circuit device, characterized in that greater than

18. The method for manufacturing a semiconductor integrated circuit device according to claim 17, wherein a main part of the gas phase reaction is an average of particles that cause the undesired deposition in the gas phase reaction processing container. A method for manufacturing a semiconductor integrated circuit device, wherein the process is performed under a vacuum such that a free process is from 0.1 mm to several 10 cm.

1 9. A method for manufacturing a semiconductor integrated circuit device comprising the following steps:

(a) Directly or indirectly on a first insulating film on a first main surface of a wafer for manufacturing a semiconductor integrated circuit device, a memory data storage unit or a ferroelectric film using a high dielectric film. Forming a high-dielectric film or a ferroelectric dielectric film constituting at least a part of an electrode of the capacitor or a first metal layer having a chemical reaction resistance to a constituent material thereof;

(b) forming, directly or indirectly, on the first metal layer, a highly insulating or ferroelectric second insulating film constituting a part of a capacitor;

(c) directly or in contact with the second insulating film, the high dielectric material constituting at least a part of an electrode of a memory data storage unit or a capacitor using the high dielectric film or the ferroelectric film. The formation of the second metal layer having chemical reaction resistance to the film or the strong dielectric film or its constituent material

(d) etching the wafer, on which the second metal layer is formed, by using a gas phase reaction in a gas phase reaction processing vessel, so that the wafer has a predetermined shape;

(e) When monitoring optical information from or at least transmitted through a reaction gas phase near the wafer involved in the etching, the gas phase reaction between the reaction gas phase and a light detection unit is monitored. The inside diameter of the processing vessel is large enough to allow at least the observation light to pass, and the large aspect ratio is large enough to substantially prevent or suppress the passage of particles that cause undesired deposition. By arranging a fine tube collecting plate in which a very large number of fine tubes with at least the reaction gas phase side being opened are densely arranged, and observing light transmitted through the fine tube collecting plate, the end point of the etching Detect Process.

20. A method for manufacturing a semiconductor integrated circuit device comprising the following steps:

(a) Directly or indirectly on a first insulating film on a first main surface of a wafer for manufacturing a semiconductor integrated circuit device, a memory data storage unit or a ferroelectric film using a high dielectric film or a ferroelectric film. Forming a first metal layer having resistance to a chemical reaction with respect to the high dielectric film or the ferroelectric film constituting the at least a part of the electrode of the capacitor or a constituent material thereof;

(b) forming, directly or indirectly, on the first metal layer, a second insulating film having a high dielectric property or a ferroelectric property which constitutes a part of a capacity;

(c) directly or indirectly on the second insulating film, the high dielectric substance constituting at least a part of a memory data storage unit or a capacitor electrode using the high dielectric film or the ferroelectric film. Forming a second metal layer having chemical reaction resistance to the film or the ferroelectric film or its constituent materials;

(d) a step of notching into a predetermined shape by etching the wafer on which the second metal chips are formed by using a gas phase reaction in a gas phase reaction processing vessel;

(e) when monitoring optical information from or at least transmitted through a reaction gas phase near the wafer involved in the etching, the gas phase reaction between the reaction gas phase and a light detection unit; The inside diameter of the processing vessel is at least large enough to allow observation light to pass through, and 5 or more large enough to substantially prevent or suppress the passage of particles that cause undesired deposition. A step of arranging a tubular portion having a stroke ratio and opening at least the reaction gas phase side, and observing light transmitted through the tubular portion to detect the end point of the etching.