JP2007181190A - Semiconductor device and method for fabricating same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of forming a compact hollow capacitor with simple configuration. <P>SOLUTION: On a single substrate 10, a hollow capacitor portion including a pair of counter electrodes 14 and 24 and a hollow part 23 located between the counter electrodes and semiconductor circuit portions 11a, 11b and 12 are formed. The hollow part 23 of the hollow capacitor portion is surrounded by insulating layers 16, 17 and 18, and a through hole 22 is formed in the insulating layer 17, 18 to communicate with the hollow part 23. The top surface of the insulating layer 17 covering the hollow part 23 is planarized. Part of the insulating layer 17 located to the lateral sides of the hollow part 23 supports the other part of the insulating layer 17 located on the hollow part 23 and the upper counter electrode 24. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device comprising a semiconductor circuit portion, a pair of counter electrodes, and a hollow capacitor portion formed of a hollow portion between the counter electrodes on the same substrate.

  Ultrasonic sensors with a frequency of several tens of kHz to several tens of megahertz have strong directivity, so the ultrasonic sensor can detect even if the object is transparent in the visible light range. It is applied to a wide range of fields, taking advantage of its characteristic that it is not easily affected by For example, distance detectors such as fish detectors, diagnostic devices capable of non-destructive inspection, flaw detectors, etc. have been put to practical use as ultrasonic sensors, and washing machines and welders are also used as ultrasonic devices. Etc. have been put into practical use (see, for example, Non-Patent Document 1). Note that the ultrasonic sensor is usually divided into a transmission unit that transmits ultrasonic waves and a reception unit that receives the transmitted ultrasonic waves.

  However, since the receiving part of the conventional ultrasonic sensor usually uses a piezoelectric ceramic vibrator, there is a problem that the price of the apparatus becomes high and the size cannot be reduced so much. In addition, in order to improve the detection sensitivity, the substrate side of the vibrator must be etched and thinned, resulting in a complicated manufacturing process. Therefore, the use application was limited.

  FIG. 10 is a cross-sectional view showing a structure of a receiving unit of a conventional ultrasonic sensor.

  On the substrate, lead zirconate titanate (PZT), which is a ferroelectric ceramic material, is formed as a material of the piezoelectric ceramic vibrator 100. Usually, in order to form PZT, it is necessary to fire at a high temperature of 550 ° C. or higher in an oxygen atmosphere. Therefore, in order to prevent the material of the electrode 101 from becoming an insulator due to oxidation during the firing process, A platinum group material such as platinum or iridium, which is difficult to finely process and is expensive, is used. In order to ensure sensitivity, it is necessary to thinly etch the back surface of the substrate on which the piezoelectric ceramic vibrator is formed to form the opening 102. For example, an 8-inch Si wafer has a thickness of about 750 μm, The etching technique of about 1 to 2 μm that is normally performed in the process of forming a semiconductor element cannot be applied, and a special process must be used to form the opening 102.

On the other hand, Patent Documents 1 to 3 disclose an ultrasonic sensor including a semiconductor circuit portion and a hollow capacitor on a semiconductor substrate. Here, the hollow portion provided between the pair of electrodes is formed by removing the sacrificial layer by wet etching with hydrofluoric acid or the like.
Yoshiro Tomikawa, “Ultrasonic Electronics Vibration Theory-Fundamentals and Applications”, Asakura Shoten, February 20, 1998 Japanese Patent No. 2545713 Special Table 2002-518913 JP-A-2002-250665

  However, a liquid etchant such as hydrofluoric acid is introduced into the sacrificial layer when forming a fine hollow portion necessary for an ultrasonic sensor and having a width of about several μm to several mm and a gap of about several hundred nm to several μm. It is very difficult. Even if it can be introduced, when the liquid etchant is removed from the hollow portion, there is a problem that the formed hollow portion is crushed by the surface tension of the liquid etchant.

  The present invention has been made to solve the above problems, and a main object thereof is to provide a semiconductor device capable of forming a small hollow capacitor with a simple configuration.

  In order to achieve the above object, a semiconductor device according to the present invention includes a hollow capacitor unit including a pair of counter electrodes and a hollow part between the counter electrodes. It is characterized by being wrapped with an insulating film.

  With such a configuration, a small hollow capacitor (ultrasonic sensor) with a simple structure can be easily realized. In addition, the upper electrode of the hollow capacitor portion vibrates due to the incidence of ultrasonic waves, and thereby the distance between the upper electrode and the lower electrode changes to change the capacitance of the hollow capacitor portion. The capacitance change of the hollow capacitor portion can be amplified and detected by a signal processing circuit mounted on the semiconductor circuit portion to operate as an ultrasonic sensor.

  In a preferred embodiment, the insulating film includes a first insulating film that covers the lower electrode of the hollow capacitor portion, and a second insulating film that covers the hollow portion of the hollow capacitor portion formed on the first insulating film. And a third insulating film covering the upper electrode of the hollow capacitor portion formed on the film and the second insulating film.

  With this configuration, in order to form the hollow portion, when the sacrificial layer previously provided in the region where the hollow portion is to be formed is removed by etching, portions other than the sacrificial layer such as the upper electrode and the lower electrode are etched. Can be prevented.

  In a preferred embodiment, a first hole connected to the hollow portion of the hollow capacitor portion is provided, and the first hole penetrates the third insulating film and the second insulating film. Thereby, the etchant at the time of forming a hollow part can be easily introduce | transduced into a sacrificial layer.

  In a preferred embodiment, the semiconductor device further includes a second hole connected to the hollow portion of the hollow capacitor portion, and the second hole penetrates at least the third insulating film and the upper electrode of the hollow capacitor portion. Thereby, more etchants can be introduced into the sacrificial layer, and the hollow portion can be easily formed.

  Here, the wall surface of the second hole is preferably covered with a protective film. Thereby, when the sacrificial layer is removed by etching to form the hollow portion, it is possible to prevent the upper electrode and the like from being etched.

  Preferably, the insulating film and the protective film are made of a silicon oxide film, the upper electrode and the lower electrode of the hollow capacitor portion are made of polycrystalline silicon, and the upper electrode is sandwiched between silicon nitride films. Thereby, the ceiling part of a hollow part can be made independent, irrespective of the kind and shape of an upper electrode.

  Furthermore, it is preferable that a charge retention layer is provided between the upper electrode and the hollow portion of the hollow capacitor portion, and the charge retention layer is wrapped with the insulating film. Thereby, when an ultrasonic wave is received, a voltage change between the upper electrode and the lower electrode of the hollow capacitor can be increased, and reception sensitivity can be increased.

  Another semiconductor device according to the present invention includes a fixed electrode formed on a substrate, a first insulating film formed on the substrate so as to cover the fixed electrode, and the first insulating film. A hollow portion formed above the fixed electrode, a first insulating film, a second insulating film formed to cover the hollow portion, and a second insulating film, A movable electrode formed above the hollow portion, and the fixed electrode, the hollow portion, and the movable electrode constitute a hollow capacitor, and the surface of the second insulating film is flattened And

  With such a configuration, the second insulating film and the movable electrode located above the hollow part can be held by the thick second insulating film located on the side of the hollow part. It is possible to prevent the second insulating film and the movable electrode located above the hollow portion from being bent and closing the hollow portion.

  In a preferred embodiment, a third insulating film is further formed on the second insulating film so as to cover the movable electrode.

  In a preferred embodiment, an introduction hole connected to the hollow portion is formed in the second insulating film and the third insulating film.

  In a preferred embodiment, the hollow portion has a communication hole extending from the periphery of the hollow portion toward the second insulating film, and the introduction hole is connected to the communication hole. With such a configuration, it is possible to increase the thickness of the second insulating film located on the side of the hollow portion, thereby strengthening the second insulating film and the movable electrode located above the hollow portion. Can be held in.

  Preferably, the hollow portion has a rectangular shape, and the communication hole extends from the periphery of the hollow portion to the second insulating film side in a cross shape.

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming a fixed electrode on a substrate, a step of forming a first insulating film on the substrate so as to cover the fixed electrode, and a step of forming the first insulating film on the first insulating film. A step of forming a sacrificial layer above the fixed electrode; a step of forming a second insulating film on the first insulating film so as to cover the sacrificial layer; and a surface of the second insulating film Planarizing the second insulating film having a predetermined thickness on the sacrificial layer, forming a movable electrode on the second insulating film and above the sacrificial layer; Forming a third insulating film on the second insulating film so as to cover the movable electrode; and forming an introduction hole reaching the sacrificial layer in the second insulating film and the third insulating film. And a step of forming a hollow portion in the second insulating film by etching away the sacrificial layer through the introduction hole, and fixing. Poles constitute a hollow capacitor hollow portion, and the movable electrode.

  In a preferred embodiment, the sacrificial layer has a part extending from the periphery of the sacrificial layer to the second insulating film side, and the introduction hole is connected to a part where the sacrificial layer extends.

  According to the semiconductor device of the present invention, a small hollow capacitor (ultrasonic sensor) with a simple structure can be easily realized. Further, according to the method for manufacturing a semiconductor device according to the present invention, a hollow capacitor (ultrasonic sensor) having a hollow portion having a stable shape can be manufactured by a simple manufacturing method.

  The best mode for carrying out the present invention will be described below with reference to the drawings. In addition, embodiment described below is an example used in order to explain the structure in this invention and its effect | action easily, Comprising: This invention is not limited to the following forms.

(First embodiment)
The semiconductor device (ultrasonic sensor) according to the first embodiment will be described with reference to FIGS.

[Configuration of ultrasonic sensor]
FIG. 1A is a cross-sectional view schematically showing the configuration of the ultrasonic sensor according to this embodiment, and FIG. 1B is a plan view showing the hollow capacitor portion of the ultrasonic sensor according to this embodiment. FIG. FIG. 5 is a cross-sectional view showing the configuration of an ultrasonic sensor according to a modification of the present embodiment.

  As shown in FIG. 1A, the ultrasonic sensor according to this embodiment includes a hollow capacitor portion in which an upper electrode (movable electrode) 24 and a lower electrode (fixed electrode) 14 face each other, a field effect transistor element, and the like. It has a configuration in which a semiconductor circuit unit including an amplifier circuit, a noise removal circuit, an output circuit, and the like is integrated. In FIG. 1A, one hollow capacitor portion and one transistor in one semiconductor circuit portion are illustrated, but a plurality of hollow capacitor portions may be arranged in an array. In this case, a selection transistor that can arbitrarily select each hollow capacitor is connected to the plurality of hollow capacitor portions. Here, FIG. 1A is a cross-sectional view through the main part (A-A ′ line) of the hollow capacitor part illustrated in FIG.

  As shown in FIG. 1A, a source region 11 a and a drain region 11 b in which n-type impurities are diffused are formed on the surface of a p-type silicon substrate 10. Thick oxide film element isolation regions 13 are formed on both sides of the source region 11a and the drain region 11b. On the surface of the silicon substrate 10, a first interlayer insulating layer (first insulating film) 16, A second interlayer insulating layer (second insulating film) 17, a third interlayer insulating layer (third insulating film) 18, and a surface protective film 26 are stacked. Note that the surface of the second interlayer insulating layer 17 is flattened so that the second interlayer insulating layer 17 a having a predetermined thickness remains on the hollow portion 23. Here, the first interlayer insulating layer 16, the second interlayer insulating layer 17, and the third interlayer insulating layer 18 are formed of a silicon oxide film.

  A gate electrode 12 is formed between the source region 11 a and the drain region 11 b, and a lower electrode 14 is formed on the element isolation region 13. Further, a hollow portion 23 and an introduction hole (first hole) 22 connected to the hollow portion 23 are formed on the lower electrode 14 via the first interlayer insulating layer 16.

  As shown in FIG. 1B, the hollow portion 23 has a communication hole 23a extending horizontally from the peripheral edge of the hollow portion 23 toward the second interlayer insulating layer 17, and each introduction hole 22 has a communication hole 23a. Are connected to the end of each. For example, in the example shown in FIG. 1B, the hollow portion 23 has a rectangular shape, and each communication hole 23 a extends from each side of the hollow portion 23 to the second interlayer insulating layer 17 side in a cross shape. Further, the end portion of the upper electrode 24 is located above the communication hole 23 a extending from each side of the hollow portion 23.

  With such a configuration, the second interlayer insulating layer 17 a and the upper electrode 24 positioned above the hollow portion 23 can be held by the thick second interlayer insulating layer 17 b positioned on the side of the hollow portion 23. Thus, it is possible to prevent the second interlayer insulating layer 17a and the upper electrode 24 located above the hollow portion 23 from being bent and closing the hollow portion 23.

  In addition, the hollow portion 23 is provided with the communication holes 23a extending from the respective sides of the hollow portion 23, so that the second interlayer insulating layer 17b having a large film thickness is formed in a portion located on the side of the communication holes 23a. A column that supports the upper electrode 24 can be provided, whereby the second interlayer insulating layer 17a and the upper electrode 24 positioned above the hollow portion 23 can be held more firmly.

  Here, the area of the lower electrode 14 is larger than the upper electrode 24. The hollow portion 23 is covered with a silicon oxide film. Here, the hollow portion 23 has a height of approximately 300 nm to 1 μm and an area of approximately 90 nm × 90 nm to 1000 μm × 1000 μm. In addition, the opening area of the introduction hole 22 is approximately 100 nm long side × 70 nm short side to 800 μm long side × 10 μm short side.

  Above the hollow portion 23 is an upper electrode film 24b sandwiched between tension films 24a and 24c, and the upper electrode 24 is formed by the tension films 24a and 24c and the upper electrode film 24b. Here, the tension films 24a and 24c are made of, for example, a silicon nitride film, and the film thickness is thinner than that of the upper electrode film 24b, and is about 30 nm to 250 nm. The upper electrode film 24b is made of, for example, a polysilicon film and has a thickness of about 200 nm to 450 nm. The area of the upper electrode 24 is approximately 100 nm × 100 nm to 1100 μm × 1100 μm, and the area of the lower electrode 14 is approximately 110 nm × 110 nm to 1200 μm × 1200 μm.

  Here, the hollow portion 23 is rectangular and the introduction hole 22 is connected to the hollow portion 23 in a cross shape. However, the hollow portion 23 has a circular shape or a gear shape, and the introduction hole 22 is an arbitrary portion of the hollow portion 23. It may be connected to the point.

  Above the source region 11a, the drain region 11b, and the gate electrode 12, a contact hole 19 embedded with tungsten (W) or a polysilicon film connected to the wiring 25 is formed. Sidewalls 15 are formed on the side surfaces of the gate electrode 12 and the lower electrode 14.

  The lower electrode 14 and the gate electrode 12 are preferably made of the same material and have the same film thickness. As a result, the lower electrode 14 and the gate electrode 12 can be simultaneously formed by film formation and processing, and a small semiconductor device with a simpler structure can be realized. Here, the gate electrode 12 and the lower electrode 14 are made of, for example, a polysilicon film, and the film thickness is about 200 nm to 450 nm.

  The lower electrode 14 is also formed with a contact hole 20 embedded in, for example, tungsten (W) or a polysilicon film, connected to the wiring 25 at a portion not covered with the hollow portion 23. The contact holes 19 and 20 may have different hole diameters.

  The upper electrode 24 is also formed with a contact hole 21 embedded in, for example, tungsten (W) or a polysilicon film, which is connected to the wiring 25 at a location where the hollow portion 23 does not exist below. The diameter of the contact hole 21 may be different from the diameter of the contact holes 19 and 20. For example, the hole diameter of the contact hole 19 is approximately 0.6 μm to 2.5 μm, the hole diameter of the contact hole 20 is approximately 0.6 μm to 2.0 μm, and the hole diameter of the contact hole 21 is approximately 0. It is about 4 μm to 1.0 μm.

  Further, as shown in FIG. 5, another introduction hole 27 (second hole) that penetrates the upper electrode 24 and reaches the hollow portion 23 may be formed. In this case, it is necessary to install a wall protective film 28 made of, for example, a silicon oxide film and having a thickness of about 50 nm to 150 nm so that the upper electrode 24 is not exposed where the introduction hole 27 penetrates the upper electrode 24. . Here, the hole diameter of the introduction hole 27 is about 1 μm to 10 μm, and the opening area of one introduction hole 27 is 1% or less of the area of the upper electrode 24.

[Method of manufacturing ultrasonic sensor]
Next, a method for manufacturing the ultrasonic sensor according to the present embodiment will be described. 2 to 4 are cross-sectional views illustrating the manufacturing process of the ultrasonic sensor according to the present embodiment, and FIG. 4B is a plan view illustrating the hollow capacitor portion in FIG.

  First, as shown in FIG. 2A, a thick oxide film 13 is selectively formed on the surface of the p-type silicon substrate 10 as element isolation. Subsequently, a gate insulating film and a polysilicon film are deposited, and a lower electrode 14 is formed on the gate electrode 12 and the thick film oxide film 13 from the polysilicon film by using a lithography method and a dry etching method.

  Subsequently, using the gate electrode 12 as a mask, impurities are implanted into the surface of the p-type silicon substrate 10 to form a source region 11a and a drain region 11b made of an n-type impurity diffusion layer. Thereafter, sidewalls 15 are formed on the gate electrode 12 and the lower electrode 14, and then the first effect so that the field effect transistor element portion and the lower electrode 14 are covered over the entire surface of the p-type silicon substrate 10 using the CVD method. A silicon oxide film to be the interlayer insulating layer 16 and a polysilicon film to be the sacrificial layer 29 are deposited. Note that salicide may be formed in the transistor of the semiconductor circuit portion in order to manufacture a finer transistor element.

  Subsequently, as shown in FIG. 2B, the sacrificial layer 29 is processed into a predetermined shape corresponding to the hollow portion 23 by using a lithography method and a dry etching method. For example, as shown in FIG. 4B, a pattern region such as a cross, a quadrangle, a circle, or a gear is formed from a polysilicon film. Next, a silicon oxide film that becomes the second interlayer insulating layer 17 using the CVD method is formed on the surface of the sacrificial layer 29 and the first interlayer insulating layer 16 formed in the shape of the hollow portion 23 using the CVD method. To deposit. Subsequently, the surface of the deposited second interlayer insulating layer 17 is planarized by using etch back or chemical mechanical polishing (CMP). The deposited thickness of the second interlayer insulating layer 17 is set so that a predetermined thickness remains on the sacrificial layer 29 after planarization.

  Next, a silicon nitride film, a polysilicon film, and a silicon nitride film are sequentially deposited by using a CVD method, and an upper portion composed of a tension film 24a, an upper electrode film 24b, and a tension film 24c by using a lithography method and a dry etching method. The electrode 24 is formed.

  Subsequently, as shown in FIG. 2C, a third interlayer insulating layer 18 is deposited on the upper electrode 24 and the second interlayer insulating layer 17 by a CVD method. Subsequently, the upper surface of the third interlayer insulating layer 18 is planarized using an etch back or chemical mechanical polishing (CMP) method or the like, and then contacted with the upper electrode film 24b using a lithography method or a dry etching method. Hole 21 is formed.

  Further, contact holes 19 and 20 connected to the source region 11a, the drain region 11b, the gate electrode 12, and the lower electrode 14 of the transistor are formed by lithography and dry etching. Thereafter, a conductor film made of tungsten or a polysilicon film is deposited by CVD so as to fill each contact hole 19, 20, 21. Subsequently, the deposited conductor film is etched back or chemical mechanical polished to remove the conductor film on the surface of the third interlayer insulating layer 18, thereby forming a plurality of contact plugs.

  Next, as shown in FIG. 3A, for example, titanium, titanium nitride, aluminum, and titanium nitride are deposited using, for example, a sputtering method, and a wiring 25 is formed using a lithography method and a dry etching method. .

  Further, after depositing a silicon nitride film by a CVD method, the silicon nitride film on the upper surface of a pad (not shown) for electrical connection with an external device is removed using a lithography method and a dry etching method, and a surface protective film 26 is formed.

  Subsequently, as shown in FIG. 3B, the surface protection film 26, the third interlayer insulating layer 18 and the second interlayer insulating layer 17 are penetrated using the lithography method and the dry etching method, and the shape of the hollow portion 23 is formed. The introduction hole 22 connected to the sacrificial layer 29 formed in (1) is formed.

  Thereafter, as shown in FIG. 4A, the polysilicon film of the sacrificial layer 29 is completely removed using a gas material capable of etching the polysilicon film, for example, fluorine trichloride, to form the hollow portion 23. Here, as an etchant for hollow etching, a gas material such as xenon fluoride may be used. Further, an etchant having a surface tension reduced by adding a surfactant such as ethanol to a liquid material such as hydrofluoric acid may be used.

  Here, before hollow etching, the following steps may be added to form another introduction hole 27 and then hollow etching may be performed.

  As shown in FIG. 5, an introduction hole that penetrates the upper electrode 24 and reaches the sacrificial layer 29 is formed by using a lithography method and a dry etching method, and then silicon oxide that becomes a wall protective film 28 by a CVD method on the entire surface. Deposit film. Next, the introduction hole 27 is formed simultaneously with the formation of the introduction hole 22 by using the lithography method and the dry etching method. At this time, the wall surface protective film 28 remains on the side surface of the introduction hole 27. At this time, the silicon oxide film on the upper surface of a pad (not shown) for electrical connection with an external device is also removed.

  Note that when the upper electrode 24 is formed, an opening may be formed in the upper electrode 24. Then, since the third interlayer insulating layer 18 is buried also in this opening, the introduction hole 27 can be formed at the opening portion simultaneously with the formation of the introduction hole 22 without adding a process. .

[Advantages of ultrasonic sensors]
The ultrasonic sensor according to the present embodiment having the above structure has a semiconductor circuit part, a pair of counter electrodes, and a hollow capacitor part composed of a hollow part between the counter electrodes on the same substrate. A structure and a small ultrasonic sensor can be realized.

  When the ultrasonic wave is incident, the upper electrode of the hollow capacitor portion vibrates and the distance between the upper electrode and the lower electrode changes to change the capacitance of the hollow capacitor. The capacitance change of the hollow capacitor portion is amplified and detected by a signal processing circuit mounted on the semiconductor circuit portion, and operates as an ultrasonic sensor.

  Further, the introduction hole 22 connected to the sacrificial layer 29 of the hollow capacitor part and the introduction hole 27 connected to the sacrificial layer 29 through the upper electrode 24 of the hollow capacitor part are formed, so that an etchant at the time of hollow etching is formed. Can be introduced into the sacrificial layer 29, and the hollow portion 23 can be easily formed.

  Further, by covering the periphery of the hollow portion 23 with a silicon oxide film, it is possible to prevent the upper electrode 24 and the lower electrode 14 from being etched when the sacrificial layer 29 is hollow etched.

  Further, the upper electrode 24 is configured such that the upper electrode film 24b is sandwiched vertically in the substrate direction by tension films 24a and 24c made of, for example, a silicon nitride film, which has a strong tensile stress. Regardless, the ceiling portion of the hollow portion can be formed independently. Furthermore, since the contact hole 21 to the upper electrode 24 is not formed on the hollow portion 23, the vibration of the upper electrode 24 can be facilitated and the sensitivity can be improved.

  Further, by making the size of the counter electrode of the hollow capacitor portion larger in the lower electrode 14 than in the upper electrode 24, the contact hole 20 connecting the lower electrode 14 and the wiring 25 can be easily formed.

  In addition, since the lower electrode 14 is made of the same material as the gate electrode 12 and has the same film thickness, the lower electrode 14 and the gate electrode 12 can be simultaneously formed and processed simultaneously. A small-sized semiconductor device with a simple structure can be realized.

  In addition, element isolation can be facilitated by forming the lower electrode 14 on the thick oxide film 13.

  Further, the contact hole 19 to the semiconductor circuit part, the contact hole 20 to the lower electrode 14 of the hollow capacitor part, and the diameter of the contact hole 21 to the upper electrode film 24b of the hollow capacitor part, each having a different contact hole depth, are defined. By changing it, it is possible to obtain an optimum aspect ratio for making contact with each other.

(Second Embodiment)
A semiconductor device (ultrasonic sensor) according to the second embodiment will be described with reference to FIGS.

[Configuration of ultrasonic sensor]
The configuration of the ultrasonic sensor will be described with reference to FIGS. FIG. 6 is a cross-sectional view showing the configuration of the ultrasonic sensor according to the present embodiment, and FIG. 9 is a cross-sectional view showing the configuration of the ultrasonic sensor according to a modification of the present embodiment.

  As shown in FIG. 6, the ultrasonic sensor according to the present embodiment includes a semiconductor circuit unit including a charge holding material in a hollow capacitor unit in which an upper electrode and a lower electrode are opposed to each other, and further configured by a field effect transistor element or the like. Are integrated. In FIG. 6, one hollow capacitor portion and one transistor in one semiconductor circuit portion are illustrated, but a plurality of the hollow capacitor portions are arranged in an array, and each of the hollow capacitor portions is arranged in each of the plurality of hollow capacitor portions. A configuration may be adopted in which a plurality of hollow capacitors are integrated by connecting to a selection transistor so that a hollow capacitor can be arbitrarily selected.

  As shown in FIG. 6, a source region 11 a and a drain region 11 b in which n-type impurities are diffused are formed on the surface of a p-type silicon substrate 10. Thick oxide film element isolation regions 13 are formed on both sides of the source region 11a and the drain region 11b. On the surface of the substrate 10, a first interlayer insulating layer 31 and a second interlayer insulating layer 32 are formed. The third interlayer insulating layer 33 and the surface protective film 26 are laminated. Here, the first interlayer insulating layer 31, the second interlayer insulating layer 32, and the third interlayer insulating layer 33 are formed of a silicon oxide film.

  The element isolation region 13 is formed between the semiconductor circuit portion and the hollow capacitor portion, and a lower electrode sandwiched between tension films 14 a and 14 c on the silicon substrate 10 surrounded by the element isolation region 13. There is a film 14b, and the lower electrode 14 is composed of each film 14a, 14b, 14c.

  A through hole 34 is formed in the silicon substrate 10 below the lower electrode 14. The hollow portion 23 and the introduction hole 22 connected to the hollow portion 23 are formed via the first interlayer insulating layer 31. Here, the introduction hole 22 is connected to each side of the rectangular hollow portion 23 in a cross shape. Here, the tension films 14a and 14c are made of, for example, a silicon nitride film, and the film thickness is thinner than the lower electrode film 14b, and is about 30 nm to 250 nm. The lower electrode film 14b is made of, for example, a polysilicon film and has a thickness of about 200 nm to 450 nm. The area of the upper electrode 24 is approximately 100 nm × 100 nm to 1100 μm × 1100 μm, and the area of the lower electrode 14 is approximately 110 nm × 110 nm to 1200 μm × 1200 μm. Further, the opening area of the semiconductor element surface portion of the introduction hole 22 is approximately 100 nm long side × 70 nm short side to 800 μm long side × 10 μm short side.

  Here, the area of the lower electrode 14 is larger than the upper electrode 24. The hollow portion 23 is covered with a silicon oxide film. The charge holding material 35 is formed between the hollow portion 23 and the upper electrode 24 and is covered with the second interlayer insulating layer 32 and the third interlayer insulating layer. Here, the hollow portion has a height of approximately 300 nm to 1 μm and an area of approximately 90 nm × 90 nm to 1000 μm × 1000 μm.

  Here, the hollow portion 23 is rectangular and the introduction hole 22 is connected to the hollow portion 23 in a cross shape. However, the hollow portion 23 has a circular shape or a gear shape, and the introduction hole 22 is an arbitrary portion of the hollow portion 23. It may be connected to the point.

  Above the source region 11a, the drain region 11b, and the gate electrode 12, a contact hole 19 embedded with tungsten (W) or a polysilicon film connected to the wiring 25 is formed. Sidewalls 15 are formed on the side surfaces of the gate electrode 12 and the lower electrode 14.

  Since the lower electrode 14 and the gate electrode 12 are made of the same material and have substantially the same film thickness, a more compact structure and a smaller semiconductor device can be realized. Here, the gate electrode 12 and the lower electrode film 14b are made of, for example, a polysilicon film, and the film thickness is about 200 nm to 450 nm.

  The lower electrode 14 is also formed with a contact hole 20 embedded in, for example, tungsten (W) or a polysilicon film, connected to the wiring 25 at a portion not covered with the hollow portion 23. The contact holes 19 and 20 may have different hole diameters.

  As shown in FIG. 9, another introduction hole 27 that penetrates the upper electrode 24 and reaches the hollow portion 23 may be formed. In this case, it is necessary to install a wall protective film 28 made of, for example, a silicon oxide film and having a thickness of about 50 nm to 150 nm so that the upper electrode 24 is not exposed where the introduction hole 27 penetrates the upper electrode 24. . Here, the hole diameter of the introduction hole 27 is about 1 μm to 10 μm, and the opening area of one introduction hole 27 is 1% or less of the area of the upper electrode 24.

[Method of manufacturing ultrasonic sensor]
Next, a method for manufacturing the ultrasonic sensor according to the present embodiment will be described. 7-8 is sectional drawing which shows the manufacturing process of the ultrasonic sensor which concerns on this embodiment.

  First, as shown in FIG. 7A, a thick oxide film 13 is selectively formed on the surface of the p-type silicon substrate 10 as element isolation. Subsequently, a gate insulating film and a polysilicon film are deposited, and a gate electrode 12 is formed from the polysilicon film using a lithography method and a dry etching method. Subsequently, using the gate electrode 12 as a mask, impurity implantation is performed on the surface of the p-type silicon substrate 10 to form a source region 11a and a drain region 11b made of an n-type impurity diffusion layer.

  Subsequently, a silicon nitride film of the tension film 14a is deposited by CVD. Next, a polysilicon film is deposited, and a polysilicon film 14b as a lower electrode is formed using a lithography method and a dry etching method. Subsequently, a silicon nitride film of the tension film 14c and a silicon oxide film of the first interlayer insulating layer 31 are deposited.

  Next, as shown in FIG. 7B, a polysilicon film to be the sacrificial layer 29 is deposited on the surface of the first interlayer insulating layer 31 by the CVD method. Subsequently, the sacrificial layer 29 is processed into a predetermined shape corresponding to the hollow portion 23 by using a lithography method and a dry etching method. Here, as in the first embodiment, the polysilicon film is processed into a pattern shape such as a cross shape. Next, a silicon oxide film of the second interlayer insulating layer 32 is deposited on the surfaces of the sacrificial layer 29 and the first interlayer insulating layer 31 formed in the shape of the hollow portion 23 using the CVD method, using the CVD method. . Subsequently, the upper surface of the deposited second interlayer insulating layer 32 is planarized using an etch back or chemical mechanical polishing (CMP) method or the like. The deposited thickness of the second interlayer insulating layer 32 is set so that a predetermined thickness remains on the sacrificial layer 29 after planarization.

  Next, as shown in FIG. 8A, the charge holding material 35 is formed using a CVD method, a lithography method, and a dry etching method. As the charge holding material 35, for example, a Teflon (registered trademark) film or the like is used. Thereafter, a charge is applied to the charge holding material 35 using corona discharge, and then a silicon oxide film of the third interlayer insulating layer 33 is deposited to cover the charge holding material 35. Subsequently, the upper surface of the third interlayer insulating layer 33 is planarized by using etch back or chemical mechanical polishing (CMP). The deposited thickness of the third interlayer insulating layer 33 is set so that a predetermined thickness remains on the charge retention material 35 after planarization.

  Subsequently, contact holes 19 and 20 connected to the source region 11a, the drain region 11b, the gate electrode 12, and the lower electrode film 14b of the transistor are formed by lithography and dry etching. Thereafter, a conductor film made of tungsten or a polysilicon film is deposited by CVD so as to fill the contact holes 19 and 20. Subsequently, the deposited conductor film is etched back or subjected to chemical mechanical polishing to remove the conductor film on the surface of the third interlayer insulating layer 33, thereby forming a plurality of contact plugs.

  Subsequently, for example, titanium, titanium nitride, aluminum, and titanium nitride are deposited using a sputtering method, for example, and the upper electrode 24 and the wiring 25 are formed using a lithography method and a dry etching method.

  Further, after depositing a silicon nitride film by a CVD method, the silicon nitride film on the upper surface of a pad (not shown) for electrical connection with an external device is removed using a lithography method and a dry etching method, and a surface protective film 26 is formed.

  Next, as shown in FIG. 8B, the surface protection film 26, the third interlayer insulating layer 33, and the second interlayer insulating layer 32 are penetrated using the lithography method and the dry etching method, and the shape of the hollow portion 23 is formed. The introduction hole 22 connected to the sacrificial layer 29 formed in (1) is formed. Subsequently, a resist film (not shown) having an opening under the lower electrode 14 is formed on the back surface of the wafer by lithography, and the back surface other than the opening is masked.

  Subsequently, the polysilicon film of the sacrificial layer 29 is completely removed using a gas material as an etchant for hollow etching, such as fluorine trichloride or xenon fluoride, to form the hollow portion 23. At this time, the silicon substrate 10 in the opening is simultaneously etched to form a through hole 34 in the silicon substrate 10 below the lower electrode 14.

  Here, before hollow etching, the following steps may be added to form another introduction hole 27 and then hollow etching may be performed.

  As shown in FIG. 9, an introduction hole that penetrates the upper electrode 24 and the charge holding material 35 and reaches the sacrificial layer 29 is formed by using a lithography method and a dry etching method. A silicon oxide film to be 28 is deposited. Next, when the introduction hole 27 is formed in the through hole simultaneously with the introduction hole 22 using the lithography method and the dry etching method, the wall surface protective film 28 remains on the side surface of the introduction hole 27. At this time, the silicon oxide film on the upper surface of a pad (not shown) for electrical connection with an external device is also removed.

[Advantages of ultrasonic sensors]
The ultrasonic sensor according to the present embodiment having the above structure has a semiconductor circuit part, a pair of counter electrodes, and a hollow capacitor part composed of a hollow part between the counter electrodes on the same semiconductor substrate. Structure and a small ultrasonic sensor can be realized.

  When the ultrasonic wave is incident, the upper electrode of the hollow capacitor portion vibrates and the distance between the upper electrode and the lower electrode changes to change the capacitance of the hollow capacitor. The capacitance change of the hollow capacitor portion is amplified and detected by a signal processing circuit mounted on the semiconductor circuit portion, and operates as an ultrasonic sensor.

  Also, the introduction hole 22 connected to the sacrificial layer 29 of the hollow capacitor portion is formed, and further, the introduction hole 27 penetrating the upper electrode 24 and the charge holding material 35 of the hollow capacitor portion and connected to the sacrificial layer 29 is formed. Thus, the etchant at the time of hollow etching can be further introduced into the sacrificial layer 29, and the hollow portion 23 can be easily formed.

  In addition, by covering the hollow portion 23 and the charge holding material 35 with a silicon oxide film, it is possible to prevent the charge holding material 35 and the lower electrode 14 from being etched during the hollow etching of the sacrificial layer 29.

  Further, by providing the charge holding material 35 wrapped with an insulating film between the upper electrode 24 and the hollow portion 23 of the hollow capacitor portion, the upper electrode 24 and the lower portion of the hollow capacitor due to a change in the interelectrode distance during ultrasonic reception The voltage change between the electrodes 14 can be increased, and the receiving sensitivity can be increased. Further, by forming the charge holding material 35 between the hollow portion 23 and the upper electrode 24, it is possible to greatly reduce process damage to the charge holding material 35 due to heat treatment such as annealing at the time of forming the ultrasonic sensor element. .

  Further, by disposing the charge holding material 35 between the counter electrodes, a charge supply circuit is not required for the capacitor portion, and the circuit area can be reduced and the size can be reduced.

  In addition, since the silicon substrate 10 below the lower electrode 14 of the hollow capacitor portion is opened by the through hole 34, it is possible to receive ultrasonic waves with high sensitivity.

  As mentioned above, although this invention was demonstrated by suitable embodiment, such description is not a limitation matter and of course, various modifications are possible. For example, in the present embodiment, an ultrasonic sensor has been described as an example of a semiconductor device including a hollow capacitor, but the present invention can also be applied to other acoustic devices such as a condenser microphone.

  As described above, the present invention is useful for an ultrasonic sensor or the like in which a semiconductor circuit is integrated, is suitable for mounting on various electronic devices as well as a single unit, and has high industrial utility value.

(A) is sectional drawing which showed the structure of the semiconductor device based on the 1st Embodiment of this invention, (b) is the top view. (A)-(c) is process sectional drawing which showed the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. (A)-(b) is process sectional drawing which showed the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. (A) is process sectional drawing which showed the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention, (b) is a top view which shows the hollow capacitor part in FIG.2 (b). It is sectional drawing which showed the modification of the semiconductor device in 1st Embodiment. It is sectional drawing which showed the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention. (A)-(b) is process sectional drawing which showed the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. (A)-(b) is process sectional drawing which showed the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing which showed the modification of the semiconductor device in the 2nd Embodiment of this invention. It is sectional drawing which showed the structure of the conventional ultrasonic sensor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Silicon substrate 11a Source region 11b Drain region 12 Gate electrode 13 Thick film oxide film (element isolation region)
14 Lower electrode 14a, 14c Tension film 14b Polysilicon film 15 Side wall 16, 31 First interlayer insulating layer 17, 17a, 17b, 32 Second interlayer insulating layer 18, 33 Third interlayer insulating layer 19, 20, 21 Contact hole 22, 27 Introduction hole 23 Hollow part 23a Communication hole 24, 24b Upper electrode 24a, 24c Tension film 25 Wiring 26 Surface protection film 28 Wall surface protection film 29 Sacrificial layer 34 Through-hole 35 Charge holding material

Claims (17)

A semiconductor device having a semiconductor circuit portion, a pair of counter electrodes, and a hollow capacitor portion formed of a hollow portion between the counter electrodes on the same substrate,
The semiconductor device according to claim 1, wherein the hollow portion of the hollow capacitor portion is wrapped with an insulating film. The insulating film is
A first insulating film covering a lower electrode of the hollow capacitor portion;
A second insulating film covering a hollow portion of the hollow capacitor portion formed on the first insulating film;
2. The semiconductor device according to claim 1, comprising: a third insulating film that covers the upper electrode of the hollow capacitor portion formed on the second insulating film. 3. A first hole connected to the hollow portion of the hollow capacitor portion;
The semiconductor device according to claim 2, wherein the first hole penetrates the third insulating film and the second insulating film. A second hole connected to the hollow portion of the hollow capacitor portion;
3. The semiconductor device according to claim 2, wherein the second hole penetrates at least the third insulating film and the upper electrode of the hollow capacitor portion.   The semiconductor device according to claim 4, wherein a wall surface of the second hole is covered with a protective film. The insulating film and the protective film are made of silicon oxide,
The upper electrode and the lower electrode of the hollow capacitor portion are made of polycrystalline silicon,
6. The semiconductor device according to claim 5, wherein the upper electrode is sandwiched between upper and lower silicon nitride films. A charge retention layer is provided between the upper electrode of the hollow capacitor portion and the hollow portion,
The semiconductor device according to claim 1, wherein the charge retention layer is enclosed by the insulating film. The insulating film is
A first insulating film covering a lower electrode of the hollow capacitor portion;
A second insulating film covering a hollow portion of the hollow capacitor portion formed on the first insulating film;
A fourth insulating film covering the charge retention layer of the hollow capacitor portion formed on the second insulating film,
The semiconductor device according to claim 7, wherein an upper electrode of the hollow capacitor portion is formed on the fourth insulating film. A first hole connected to the hollow portion of the hollow capacitor portion;
The semiconductor device according to claim 8, wherein the first hole penetrates at least the second insulating film. A fixed electrode formed on the substrate;
A first insulating film formed on the substrate so as to cover the fixed electrode;
A hollow portion formed on the first insulating film and above the fixed electrode;
A second insulating film formed on the first insulating film so as to cover the hollow portion;
A semiconductor device comprising: a movable electrode formed on the second insulating film and above the hollow portion;
The fixed electrode, the hollow portion, and the movable electrode constitute a hollow capacitor,
The semiconductor device, wherein the second insulating film has a flat surface.   The semiconductor device according to claim 10, wherein a third insulating film is further formed on the second insulating film so as to cover the movable electrode.   The semiconductor device according to claim 11, wherein an introduction hole connected to the hollow portion is formed in the second insulating film and the third insulating film. The hollow portion has a communication hole extending from the periphery of the hollow portion toward the second insulating film,
The semiconductor device according to claim 12, wherein the introduction hole is connected to the communication hole. The hollow portion has a rectangular shape,
The semiconductor device according to claim 13, wherein the communication hole extends from the periphery of the hollow portion to the second insulating film side in a cross shape.   The semiconductor device according to claim 13, wherein an end portion of the movable electrode is located in an upper portion of the communication hole. Forming a first insulating film on the substrate so as to cover the fixed electrode;
Forming a sacrificial layer on the first insulating film and above the fixed electrode;
Forming a second insulating film on the first insulating film so as to cover the sacrificial layer;
Planarizing the surface of the second insulating film such that a second insulating film having a predetermined thickness remains on the sacrificial layer;
Forming a movable electrode on the second insulating film and above the sacrificial layer; forming a third insulating film on the second insulating film so as to cover the movable electrode; ,
Forming an introduction hole reaching the sacrificial layer in the second insulating film and the third insulating film;
A step of forming a hollow portion in the second insulating film by etching away the sacrificial layer through the introduction hole, and a method of manufacturing a semiconductor device,
A method of manufacturing a semiconductor device, wherein the fixed electrode, the hollow portion, and the movable electrode constitute a hollow capacitor. The sacrificial layer has a portion extending from the periphery of the sacrificial layer to the second insulating film side,
The method of manufacturing a semiconductor device according to claim 16, wherein the introduction hole is connected to a portion where the sacrificial layer extends.

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