JP2002299572A - Semiconductor device and its fabricating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To satisfy both large capacitance and fine patterning (high integration) of capacitors in a ferroelectric memory. SOLUTION: A first capacitor electrode 121 and a second capacitor electrode 122 sandwiching a ferroelectric film (capacitor dielectric film) 13 have faces (sandwiching faces) perpendicular to the major surface of an Si substrate 1. After a gate part 2, an insulation film 3 on the gate, source and drain 4 and 5, an interlayer insulation film 6, and a plug 8 are formed on the Si substrate 1, a sacrificial insulation film is deposited on the entire surface and trenches for burying the capacitor electrodes 121 and 122 are made therein. A conductive film 12 is then deposited on the entire surface and eventually removed by CMP except that in the trenches. Subsequently, the trench frame of sacrificial insulation film is removed by etching, ferroelectric 13 is deposited and then the upper surface is polished thus completing a semiconductor device. Since the faces of the electrodes sandwiching the ferroelectric are perpendicular to the substrate 1 and the direction of polarization is parallel with the plane of the substrate, element area is not increased even if the sandwiching face is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device including a ferroelectric memory and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, ferroelectric memories, which are one type of nonvolatile memories, have been developed. FIG. 15 is a sectional view showing the basic structure of the ferroelectric memory. In the figure, 80
Is a Si substrate, 81 is a gate portion (gate insulating film / gate electrode), 82 is a gate upper insulating film, 83 and 84 are source / drain regions, 85 is a first interlayer insulating film, 86 and 87 are plugs, 88 is A lower capacitor electrode made of a noble metal such as Pt, 89 is a capacitor dielectric film made of a ferroelectric, 90 is an upper capacitor electrode made of a noble metal such as Pt, 91 is a second interlayer insulating film, and 92 is a plug / wiring. Is shown.

The surfaces of the lower capacitor electrode 88 and the upper capacitor electrode 90 sandwiching the capacitor dielectric film 89 (hereinafter referred to as sandwiching surfaces) are parallel to the surface of the Si substrate 1. In order to secure the capacitance of the capacitor, it is necessary to increase the capacitor area. For that purpose, it is necessary to enlarge the holding surface.

[0004] When the holding surface is enlarged, the area of the element region required for manufacturing the capacitor increases. Therefore, it is difficult to achieve both the large capacity of the capacitor and the miniaturization (high integration) of the ferroelectric memory.

[0005] Further, respective films to be a lower capacitor electrode 88, a capacitor dielectric film 89, and an upper capacitor electrode 90 are laminated, and the laminated film is subjected to RIE (Reactive Ion Etch).
ng), the material of the lower capacitor electrode 88 and the upper capacitor electrode 90 is P
In order to prevent a noble metal such as t from adhering to the side wall as a deposit, the processed shape is tapered.

As a result, the areas of the lower capacitor electrode 88 and the upper capacitor electrode 90 become asymmetric, the hysteresis curve shifts, and the device characteristics deteriorate. Further, at the time of the RIE processing, a ferroelectric film used as a capacitor dielectric film is damaged, which also deteriorates element characteristics (ferroelectric characteristics).

Further, when a connection hole and a wiring groove are formed in the second interlayer insulating film and the plug and wiring 92 are buried and formed,
Since the aspect ratio of the connection hole is high, the plug / wiring 92
It becomes difficult to embed the plug portion.

[0008]

As described above, in the conventional ferroelectric memory, in order to increase the capacitance of the capacitor,
When the area of the capacitor is increased, the area of the memory cell is increased, and the lower capacitor electrode and the upper capacitor electrode of the capacitor are formed parallel to the substrate surface.
There is a problem that high integration is difficult.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a ferroelectric memory capable of achieving both a large capacity capacitor and a fine ferroelectric memory (high integration). And a method for manufacturing the same.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones are briefly described as follows.

That is, a first semiconductor device according to the present invention comprises: a semiconductor substrate having a main surface; and a ferroelectric memory formed on the main surface of the semiconductor substrate. A capacitor having a ferroelectric film inserted between the first capacitor electrode and the second capacitor electrode;
One of the source / drain includes an MIS transistor electrically connected to the first capacitor electrode, and the direction of polarization induced in the ferroelectric film is relative to the main surface of the semiconductor substrate. It is characterized by being parallel.

Further, a second semiconductor device according to the present invention comprises:
A semiconductor substrate having a main surface; and a ferroelectric memory formed on the main surface of the semiconductor substrate, wherein the ferroelectric memory has a ferroelectric memory between a first capacitor electrode and a second capacitor electrode. A capacitor having a dielectric film inserted therein, and a MIS transistor having one source / drain electrically connected to the first capacitor electrode; and the first capacitor electrode and the ferroelectric film And a direction in which the second capacitor electrodes are arranged in parallel with the main surface of the semiconductor substrate.

In the case of the first and second semiconductor devices,
The surfaces (sandwich surfaces) of the first capacitor electrode and the second capacitor electrode sandwiching the capacitor dielectric film are perpendicular to the main surface of the semiconductor substrate. Therefore, even if the holding surface is increased to increase the capacitance of the capacitor, the area of the element region required for manufacturing the capacitor does not increase. Therefore, it is possible to achieve both the large capacity of the capacitor and the miniaturization (high integration) of the ferroelectric memory.

In the first and second semiconductor devices, when the ferroelectric memory has a chain structure, the other source / drain is connected to the second capacitor electrode.

Further, a first method of manufacturing a semiconductor device according to the present invention provides a semiconductor device comprising: a semiconductor substrate having a main surface; and a ferroelectric memory formed on the main surface of the semiconductor substrate. The manufacturing method of the ferroelectric memory includes a step of forming an MIS transistor on the main surface of the semiconductor substrate and a step of forming an interlayer insulating film covering the MIS transistor on the semiconductor substrate. Forming first and second capacitor electrodes in the same plane on the interlayer insulating film; and forming a capacitor dielectric film between the first capacitor electrode and the second capacitor electrode. It is characterized by having a process.

A second method of manufacturing a semiconductor device according to the present invention provides a semiconductor device comprising: a semiconductor substrate having a main surface; and a ferroelectric memory formed on the main surface of the semiconductor substrate. The manufacturing method of the ferroelectric memory includes a step of forming an MIS transistor on the main surface of the semiconductor substrate and a step of forming an interlayer insulating film covering the MIS transistor on the semiconductor substrate. Forming a capacitor dielectric film on a part of the interlayer insulating film; and forming a first capacitor electrode and a second capacitor electrode in the same plane on the interlayer insulating film. And a step of sandwiching between them.

In the first and second methods for manufacturing a semiconductor device, the first and second capacitor electrodes may be formed of the same conductive film or different conductive films. When formed of the same film, the first and second capacitor electrodes are formed simultaneously, and when formed of different conductive films, the first and second capacitor electrodes are formed in separate steps.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIGS. 1 to 3 are process sectional views showing a method of manufacturing a ferroelectric memory according to a first embodiment of the present invention. In the following embodiments, chai
Although an n-structure ferroelectric memory will be described, the present invention can also be applied to a one-transistor / one-capacitor ferroelectric memory.

First, as shown in FIG. 1A, a gate portion (gate insulating film / gate electrode) 2, a gate upper insulating film 3, a source / drain region 4, 5, a first interlayer insulating film 6, and plugs 7 and 8 are formed. Next, as shown in FIG. 3A, an insulating film 9 having a flat surface as a sacrificial film is formed on the entire surface. The insulating film 9 is removed in the future and does not remain.

Next, as shown in FIG. 1B, trenches 10 ₁ and 10 ₂ reaching the source / drain regions 4 and 5 are formed in the insulating film 6 by using photolithography and RIE. The positions and shapes of the grooves 10 ₁ and 10 ₂ are the same as the positions and shapes of the capacitor electrodes to be formed later.

In general, in the case of RIE processing of an insulating film, since a compound having a low vapor pressure (a compound of a material of an insulating film and a material of an etching gas) exists, the RIE processing of a noble metal film such as a Pt film is performed. Unlike the case described above, a vertical etching shape can be obtained. Therefore, the grooves 10 ₁ , 10
_{The two} side surfaces can be made perpendicular to the base (the surface of the first interlayer insulating film 6).

Next, as shown in FIG. 1C, the grooves 10 ₁ ,
A conductive film 12 serving as first and second capacitor electrodes is deposited on the entire surface so as to embed 10 ₂ .

The material of the conductive film 12 is, for example, Ir, Ir
A metal such as O, Ru, RuO, or SRO or a metal oxide having conductivity, or a non-oxidized metal such as Pt or Au is used.

When the material is Ru, the method of forming the conductive film 12 is, for example, thermal CVD. Film forming conditions, the source used is Ru (CP) ₂ and O _2, the film formation temperature is 250 to 300
° C. The film formation method may be a plating method or a sputtering method.

Next, as shown in FIG.
grooves 10 ₁ , 1 using emical mechanical polishing
0 ₂ to remove the external conductive film 12, the first capacitor electrode 12 ₁ by flattening the surface, forming a second capacitor electrode 12 _2.

Here, the groove 10₁, 10_TwoVertical wall
Therefore, the capacitor electrode 12₁, 12 _TwoVertical side walls
You.

Next, as shown in FIG. 2E, the insulating film 9 is selectively removed. The material of the insulating film 9 is TEOS or SOG
In this case, the insulating film 9 can be selectively removed by wet etching using HF.

[0030] Next, as shown in FIG. 2 (f), so as to fill the first capacitor electrode 12 ₁ and the gap between the second capacitor electrode 12 _2, the ferroelectric film serving as the capacitor dielectric film 13 is deposited on the entire surface. Thereafter, annealing is performed to harden the ferroelectric film 13.

The material of the ferroelectric film 13 is, for example, PZT
(Pb (Zr _x Ti _1-x O ₃ ) or (Ba, Sr) Ti
O ₃ (BST). The method of forming the ferroelectric film 13 is as follows.
For example, a sol / gel method, a sputtering method, or a CVD method.

[0032] Thereafter, as shown in FIG. 3 (g), the first capacitor electrode 12 ₁ and the second capacitor electrode 12
_The ferroelectric film 13 is polished by CMP until the surface of the ferroelectric film ₂ is exposed to form a capacitor dielectric film composed of the ferroelectric film 13, thereby completing a ferroelectric memory. FIG. 3H is a plan view at this stage.

According to the present embodiment, the first capacitor electrode 12 _1, the ferroelectric film (capacitor dielectric film) 13 and a second direction in which the capacitor electrode 12 ₂ is lined, S
A first capacitor electrode 12 which is parallel to the main surface of i-substrate 1 and sandwiches ferroelectric film (capacitor dielectric film) 13
₁ and the second capacitor electrode 12 ₂ of the surface (holding surface)
Are perpendicular to the main surface of the Si substrate 1. In other words, the direction of polarization induced in the ferroelectric film (capacitor dielectric film) 13 is parallel to the main surface of the Si substrate 1. Therefore, even if the holding surface is increased to increase the capacitance of the capacitor, the area of the element region required for manufacturing the capacitor does not increase. Therefore, it is possible to achieve both the large capacity of the capacitor and the miniaturization (high integration) of the ferroelectric memory.

Further, since the side wall of the capacitor electrodes 12 _1, 12 ₂ is a vertical, as shown in FIG. 3 (g), the ferroelectric center line of the memory, the capacitor has a symmetrical structure. Therefore, the problem that the hysteresis curve shifts and the element characteristics deteriorate does not occur.

Further, since the capacitor electrode 12 ₁ is connected directly to the plug 7, unlike the conventional ferroelectric memory shown in FIG. 15, opening the high aspect ratio contact hole, the plug and wiring 92 It does not need to be formed. That is, the ferroelectric memory according to the present embodiment has a structure in which the formation of the contact portion is extremely easy.

[0036] The first capacitor electrode 12 ₁ and the second capacitor electrode 12 ₂ of the shape, as shown in the plan view of FIG. 4, the portion facing the serpentine, tooth shape, etc.,
The shape may be other than a straight line. By adopting such a shape, the contact area between the capacitor electrodes 12 ₁ and 12 ₂ and the ferroelectric film 13 is increased, and the capacitance of the capacitor can be further increased. This modification can also be applied to the second to eighth embodiments described below.

(Second Embodiment) FIGS. 5 and 6 are sectional views showing steps of a method for manufacturing a ferroelectric memory according to a second embodiment of the present invention. 1 to 3 are denoted by the same reference numerals as those in FIGS. 1 to 3, and detailed description is omitted (the same applies to other embodiments).

In the first embodiment, a capacitor dielectric film is formed after forming a capacitor electrode. In the present embodiment, conversely, the capacitor electrode is formed after the capacitor dielectric film is formed.

First, the step shown in FIG. 1A is performed. Next, as shown in FIG. 5A, the insulating film 9 is processed by using photolithography and RIE to form grooves 10 ₁ and 10 ₂ . The positions and shapes of the grooves 10 ₁ and 10 ₂ are the same as the positions and shapes of the capacitor dielectric film to be formed later.

Next, as shown in FIG. 5B, the grooves 10 ₁ ,
A ferroelectric film 13 is deposited on the entire surface so as to embed 10 ₂ .

Next, as shown in FIG. 5C, the ferroelectric film 13 outside the trenches 10 ₁ and 10 ₂ is removed using CMP and the surface is flattened to form a capacitor made of the ferroelectric film 13. A dielectric film is formed.

Next, as shown in FIG. 6D, the insulating film 9 is selectively removed.

Next, as shown in FIG. 6E, the conductive film 12 is formed on the entire surface so as to fill a groove formed by removing the insulating film 9.
Is deposited.

Thereafter, as shown in FIG.
The conductive film 12 outside the groove formed by removing the insulating film 9 by using
While removing the surface and flattening the surface
12 ₁, 12_TwoIs formed, and the ferroelectric memory is completed.

In this embodiment, effects similar to those of the first embodiment can be obtained.

(Third Embodiment) FIG. 7 shows a third embodiment of the present invention.
FIG. 11 is a process sectional view illustrating the method for manufacturing the ferroelectric memory according to the embodiment. In this embodiment, a method of forming a ferroelectric film using a capacitor electrode formed by directly patterning a conductive film as a mold will be described. Therefore, the insulating film 9 is not used.

First, as shown in FIG. 1A, a gate portion 2, a gate upper insulating film 3, source / drain regions 4, 5, a first interlayer insulating film 6, a plug 7, 8
To form Next, as shown in FIG. 7A, a conductive film 12 is deposited on the entire surface.

Next, as shown in FIG. 7B, the conductive film 12 is processed by photolithography and RIE to form capacitor electrodes 12 ₁ and 12 ₂ .

Next, as shown in FIG. 7C, a ferroelectric film 13 is deposited on the entire surface so as to fill the gap between the capacitor electrodes 12 ₁ and 12 ₂ .

Thereafter, FIG. 3 described in the first embodiment
Through the step (g), a ferroelectric memory is completed.

In this embodiment, the same effects as in the first embodiment can be obtained. Further, the conductive film 1 is not used without using the insulating film 9.
By directly patterning 2 to form a capacitor electrode, the number of steps can be reduced.

(Fourth Embodiment) FIG. 8 shows a fourth embodiment of the present invention.
FIG. 11 is a process sectional view illustrating the method for manufacturing the ferroelectric memory according to the embodiment. In the present embodiment, a method for forming a capacitor electrode using a capacitor dielectric film formed by directly patterning a ferroelectric film as a mold will be described. Therefore, the insulating film 9 is not used.

First, as shown in FIG. 1A, a gate portion 2, a gate upper insulating film 3, source / drain regions 4 and 5, a first interlayer insulating film 6, a plug 7, 8
To form

Next, as shown in FIG. 8A, a ferroelectric film 13 is deposited on the entire surface. Thereafter, annealing is performed to harden the ferroelectric film.

Next, as shown in FIG. 8B, the ferroelectric film 13 is processed by photolithography and RIE to form a capacitor dielectric film.

Next, as shown in FIG. 8C, the gap between the ferroelectric films (capacitor dielectric films) 13 is
A conductive film 12 is deposited on the entire surface.

In the subsequent steps, the ferroelectric memory is completed through the step of FIG. 6F described in the first embodiment.

According to this embodiment, the same effects as those of the first embodiment can be obtained except for the effect on the ferroelectric film 13. Further, the ferroelectric film 13 is not used without using the insulating film 9.
Is directly patterned to form a capacitor dielectric film, whereby the number of steps can be reduced.

(Fifth Embodiment) FIG. 9 and FIG.
It is a process sectional view showing the manufacturing method of the ferroelectric memory according to the fifth embodiment of the present invention. In the present embodiment, a method for manufacturing a ferroelectric memory in which the side and bottom surfaces of a capacitor electrode are covered with a protective film will be described.

First, the steps of FIGS. 1A and 1B of the first embodiment are performed. Next, as shown in FIG. 9A, the side and bottom surfaces of the grooves 10 ₁ and 10 ₂ are covered.
A protective film 16 is deposited on the entire surface.

The protective film 16 protects the ferroelectric film by supplying oxygen to the ferroelectric film (capacitor dielectric film) or prevents diffusion between the capacitor electrode and the ferroelectric film. This protects the capacitor electrode or the ferroelectric film. Thereby, the element characteristics and the reliability can be improved. For example, when the material of the protective film 16 is Pt as the material of the capacitor electrode and the material of the ferroelectric film is PZT,
SRO.

Next, as shown in FIG.
Then, a conductive film 12 serving as first and second capacitor electrodes is deposited on the entire surface so as to fill the trenches 10 ₁ and 10 ₂ through the steps.

Next, as shown in FIG. 9C, the conductive film 12 and the protective film 1 outside the trenches 10 ₁ and 10 ₂ are formed using CMP.
6 is removed and the surface is flattened to form capacitor electrodes 12 _{1 and} 12 ₂ .

Next, as shown in FIG.
Is selectively removed, and as shown in FIG. 10E, the capacitor electrode 1 having the side and bottom surfaces covered with the protective film 16 is formed.
2 _1, 12 so as to fill the gap between the _two, the ferroelectric film 13
Is deposited on the entire surface. Thereafter, annealing is performed to harden the ferroelectric film.

Thereafter, as shown in FIG. 10F, the ferroelectric film 13 is polished by CMP until the surfaces of the capacitor electrodes 12 _{1 and} 12 ₂ and the protective film 16 are exposed. Then, a ferroelectric memory is completed.

In this embodiment, the same effects as those of the first embodiment can be obtained, and by introducing the protective film 16, the device characteristics and reliability can be improved.

(Sixth Embodiment) FIG. 11 is a process sectional view showing a method for manufacturing a ferroelectric memory according to a sixth embodiment of the present invention. In the present embodiment, a method for forming a capacitor electrode using a capacitor dielectric film formed by directly patterning a ferroelectric film as a mold will be described.

As shown in FIG. 1A, a gate portion 2, a gate upper insulating film 3, source / drain regions 4, 5, a first interlayer insulating film 6, and plugs 7, 8 are formed on a Si substrate 1. Form.

Next, as shown in FIG. 11A, a ferroelectric film 13 is deposited on the entire surface. Thereafter, annealing is performed to harden the ferroelectric film.

Next, as shown in FIG. 11B, the ferroelectric film 13 is processed by photolithography and RIE to form a capacitor dielectric film. Next, as shown in FIG. 3B, the side and top surfaces of the ferroelectric film 13 (capacitor dielectric film), and the first interlayer insulating film 6 and the ferroelectric film 13 (capacitor dielectric film). Plug 7, 8
A protective film 16 is deposited on the entire surface so as to cover the surface.

Next, as shown in FIG.
A conductive film 12 is deposited on the entire surface so as to fill gaps in the ferroelectric film (capacitor dielectric film) 13 covered with 6.

[0072] Thereafter, as shown in FIG. 11 (d), the ferroelectric film (capacitor dielectric film) 13, the conductive film 12 to the protective film 16 surface is exposed is polished by CMP, the capacitor electrodes 12 _1, 12 ₂ is formed, the ferroelectric memory is completed.

In the present embodiment, the same effects as those of the second embodiment can be obtained, and the device characteristics and reliability can be improved by introducing the protective film 16.

(Seventh Embodiment) FIGS. 12 and 13
FIG. 19 is a process sectional view illustrating the method for manufacturing the ferroelectric memory according to the seventh embodiment of the present invention. In the present embodiment, a method for manufacturing a ferroelectric memory in which the side and bottom surfaces of a ferroelectric film (capacitor dielectric film) are covered with a protective film will be described.

First, the step of FIG. 5A of the second embodiment
I do. Next, as shown in FIG.₁, 1
0_TwoOver the entire surface so as to cover the side and bottom surfaces of the
Is deposited. The protective film 17 is made of a ferroelectric film (capacitor-inducing).
Protective), improve ferroelectric properties, and improve reliability.
Improve the performance. The material of the protective film 17 is, for example, Si
O _x, SiN_x, AlO_x, TiO_xIt is.

Next, as shown in FIG.
A ferroelectric film 13 is deposited so as to fill the trenches 10 ₁ and 10 ₂ via. Thereafter, annealing is performed to harden the ferroelectric film.

Next, as shown in FIG. 12C, the ferroelectric film 13 and the protective film 17 outside the trenches 10 ₁ and 10 ₂ are removed using CMP, and the surface is flattened to remove the capacitor dielectric film. To form

Next, as shown in FIG.
Is selectively removed, and as shown in FIG. 13E, a conductive film is formed so as to fill a gap between the ferroelectric films (capacitor dielectric films) 13 whose side and bottom surfaces are covered with the protective film 17. 12 is deposited on the entire surface.

[0079] Thereafter, as shown in FIG. 13 (f), the ferroelectric film (capacitor dielectric film) 13, the conductive film 12 until the surface of the protective film 17 is exposed is polished by CMP, the capacitor electrode 12 ₁ , 12 ₂ is formed, the ferroelectric memory is completed.

In this embodiment, the same effects as those of the first embodiment can be obtained. Further, by introducing the protective film 17, the device characteristics and the reliability can be improved.

(Eighth Embodiment) FIG. 14 is a process sectional view showing a method of manufacturing a ferroelectric memory according to an eighth embodiment of the present invention. In the present embodiment, a method of forming a capacitor electrode using a capacitor dielectric film formed by directly forming a protective film and patterning a ferroelectric film as a mold will be described.

First, as shown in FIG. 1A, a gate portion 2, a gate upper insulating film 3, source / drain regions 4 and 5, a first interlayer insulating film 6, a plug 7, 8
To form

Next, as shown in FIG. 15A, a ferroelectric film 13 is deposited on the entire surface. Thereafter, annealing is performed to harden the ferroelectric film.

Next, as shown in FIG. 15B, the ferroelectric film 13 is processed by photolithography and RIE to form a capacitor dielectric film, and then a protective film 17 is deposited on the entire surface.

Next, as shown in FIG. 15C, a conductive film 12 is formed on the entire surface so as to fill gaps between the ferroelectric film (capacitor dielectric film) 13 whose side and top surfaces are covered with the protective film 17. accumulate.

In the subsequent steps, the ferroelectric memory is completed through the steps of FIG. 14E and FIG. 14F described in the seventh embodiment.

In this embodiment, the same effects as those of the second embodiment can be obtained, and by introducing the protective film 17, the device characteristics and the reliability can be improved.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the capacitor electrodes 12 ₁ and 12 ₂ are formed of the same material, but may be formed of different materials. For example, capacitor electrode 1
2 _1, 12 ₂ materials Pt, Ir, IrO _2, Ru, R
uO ₂ .

When changing the material of the capacitor electrodes 12 ₁ and 12 ₂ , a sacrificial film is formed for each conductive film or is directly patterned for each conductive film to form the capacitor electrode 1 1.
It will form a 2 _1, 12 _2. As an effect of the case where the capacitor is formed of a different material, an improvement in the reliability of the capacitor can be given.

Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements described in the embodiment, if the problem described in the section of the problem to be solved by the invention can be solved, the constituent Can be extracted as an invention. In addition, various modifications can be made without departing from the scope of the present invention.

[0091]

As described above in detail, according to the present invention, a semiconductor device provided with a ferroelectric memory capable of realizing both a large capacity of a capacitor and miniaturization (high integration) of a ferroelectric memory, and a method of manufacturing the same. Can be realized.

[Brief description of the drawings]

FIG. 1 is a view showing a manufacturing process of a ferroelectric memory according to a first embodiment of the present invention;

FIG. 2 is a view showing a manufacturing process of the ferroelectric memory following FIG. 1;

FIG. 3 is a view showing a manufacturing process of the ferroelectric memory following FIG. 2;

FIG. 4 is a plan view showing a modification.

FIG. 5 is a view showing a manufacturing process of the ferroelectric memory according to the second embodiment of the present invention;

FIG. 6 is a view showing a manufacturing process of the ferroelectric memory following FIG. 5;

FIG. 7 is a view showing a manufacturing process of the ferroelectric memory according to the third embodiment of the present invention;

FIG. 8 is a view showing a manufacturing process of a ferroelectric memory according to a fourth embodiment of the present invention.

FIG. 9 is a view showing a manufacturing process of a ferroelectric memory according to a fifth embodiment of the present invention;

FIG. 10 is a view showing a manufacturing process of the ferroelectric memory following FIG. 9;

FIG. 11 is a view showing a manufacturing process of the ferroelectric memory according to the sixth embodiment of the present invention;

FIG. 12 is a view showing a manufacturing process of the ferroelectric memory according to the seventh embodiment of the present invention;

FIG. 13 is a view showing a manufacturing process of the ferroelectric memory following FIG. 13;

FIG. 14 is a view showing a manufacturing process of the ferroelectric memory according to the eighth embodiment of the present invention;

FIG. 15 shows a basic structure of a conventional ferroelectric memory.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Si substrate 2 ... Gate part (gate insulating film / gate electrode) 3 ... Gate upper insulating film 4,5 ... Source / drain region 6 ... First interlayer insulating film 7,8 ... Plug 9 ... Insulating film (sacrifice film) ) 10 ₁ , 10 ₂ ... groove 12 ... conductive film 12 ₁ ... first capacitor electrode 12 ₂ ... second capacitor electrode 13 ... ferroelectric film (capacitor dielectric film) 14 ... wiring 15 ... second interlayer insulation Film 16, 17… Protective film

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Mune Yabuki 8 Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa Prefecture Inside the Toshiba Yokohama Office (72) Inventor Hideo Shinomiya 8 Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa (72) Inventor Eiji Ito 8-8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa F-term (reference) 5F083 AD42 FR02 GA21 GA25 JA14 JA15 JA38 JA42 JA43 MA06 MA17 MA20 PR21 PR40

Claims (12)

[Claims] 1. A semiconductor substrate having a main surface, and a ferroelectric memory formed on the main surface of the semiconductor substrate, wherein the ferroelectric memory has a first capacitor electrode and a second capacitor electrode. A capacitor having a ferroelectric film interposed between the first capacitor electrode and a MIS transistor having one source / drain electrically connected to the first capacitor electrode; A semiconductor device, wherein a direction of polarization induced in a body film is parallel to the main surface of the semiconductor substrate. 2. A semiconductor substrate having a main surface, and a ferroelectric memory formed on the main surface of the semiconductor substrate, wherein the ferroelectric memory has a first capacitor electrode and a second capacitor electrode. A capacitor having a ferroelectric film inserted between the first capacitor electrode and a MIS transistor having one source / drain electrically connected to the first capacitor electrode; Capacitor electrode, ferroelectric film and second
Wherein the direction in which the capacitor electrodes are arranged is parallel to the main surface of the semiconductor substrate. 3. A method of manufacturing a semiconductor device comprising: a semiconductor substrate having a main surface; and a ferroelectric memory formed on the main surface of the semiconductor substrate. Forming a MIS transistor on the main surface of the semiconductor substrate, forming an interlayer insulating film covering the MIS transistor on the semiconductor substrate, and forming a first MIS transistor on the same surface on the interlayer insulating film. And forming a second capacitor electrode; and forming a capacitor dielectric film between the first and second capacitor electrodes. 4. The semiconductor according to claim 3, wherein the step of forming the first and second capacitor electrodes includes a step of forming a conductive film and a step of patterning the conductive film. Device manufacturing method. 5. A step of forming a dielectric film on a region including the first and second capacitor electrodes, and a step of forming a ferroelectric film serving as the capacitor dielectric film on the dielectric film. Removing the surfaces of the dielectric film and the ferroelectric film until the surfaces of the first and second capacitor electrodes are exposed to form the capacitor dielectric film. The method for manufacturing a semiconductor device according to claim 4. 6. The step of forming the first and second capacitor electrodes includes forming a sacrificial film having a plurality of openings, filling the openings with a conductive film, and removing the sacrificial film. 4. The method of manufacturing a semiconductor device according to claim 3, further comprising the steps of: 7. The method according to claim 1, wherein the conductive film includes a first conductive film and the first conductive film.
7. The method of manufacturing a semiconductor device according to claim 6, further comprising a second conductive film formed as the first and second capacitor electrodes formed on the conductive film. 8. A method for manufacturing a semiconductor device comprising: a semiconductor substrate having a main surface; and a ferroelectric memory formed on the main surface of the semiconductor substrate. Forming a MIS transistor on the main surface of the semiconductor substrate, forming an interlayer insulating film covering the MIS transistor on the semiconductor substrate, and forming a capacitor dielectric on a portion of the interlayer insulating film. Forming a body film; and forming a first capacitor electrode and a second capacitor electrode in the same plane on the interlayer insulating film so as to sandwich the capacitor dielectric film. A method for manufacturing a semiconductor device. 9. The semiconductor according to claim 8, wherein the step of forming the capacitor dielectric film includes a step of forming a ferroelectric film and a step of patterning the ferroelectric film. Device manufacturing method. 10. A step of forming a first conductive film on a region including the capacitor dielectric film, and a second conductive film serving as the first and second capacitor electrodes on the first conductive film. 10. The semiconductor device according to claim 9, further comprising a step of forming a film and a step of etching the surfaces of the first and second conductive films until the surface of the capacitor dielectric film is exposed. Manufacturing method. 11. The step of forming a capacitor dielectric film includes the steps of forming a sacrificial film having a plurality of openings, filling the openings with a dielectric film, and removing the sacrificial film. The method for manufacturing a semiconductor device according to claim 8, wherein: 12. The dielectric film according to claim 1, wherein said dielectric film includes a first dielectric film and a ferroelectric film as said capacitor dielectric film formed on said first dielectric film. Item 1
0. A method for manufacturing a semiconductor device according to item 0.