WO1997050042A1 - A method and apparatus for providing concurrent access by a plur ality of agents to a shared memory - Google Patents

A method and apparatus for providing concurrent access by a plur ality of agents to a shared memory Download PDF

Info

Publication number
WO1997050042A1
WO1997050042A1 PCT/US1997/010447 US9710447W WO9750042A1 WO 1997050042 A1 WO1997050042 A1 WO 1997050042A1 US 9710447 W US9710447 W US 9710447W WO 9750042 A1 WO9750042 A1 WO 9750042A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory
access
agent
shared
memory portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1997/010447
Other languages
English (en)
French (fr)
Inventor
Manish Muthal
Nilesh V. Shah
Kuljit Bains
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to AU33976/97A priority Critical patent/AU3397697A/en
Priority to JP50322998A priority patent/JP3976342B2/ja
Priority to DE69724463T priority patent/DE69724463T2/de
Priority to EP97930056A priority patent/EP0972251B1/en
Priority to KR1019980710671A priority patent/KR100317517B1/ko
Publication of WO1997050042A1 publication Critical patent/WO1997050042A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1647—Handling requests for interconnection or transfer for access to memory bus based on arbitration with interleaved bank access

Definitions

  • the present invention pertains to the field of computer systems. More particularly, the present invention relates to a computer system that employs a memory controller and a graphics controller which share a memory resource.
  • a number of computer systems employing a microprocessor utilize a memory controller and a graphics controller.
  • the memory controller controls access by the microprocessor, and other peripheral integrated circuits, to system memory.
  • the graphics controller controls the display of data provided by the microprocessor onto a display screen, such as a cathode ray tube (CRT) using a frame buffer.
  • a display screen such as a cathode ray tube (CRT) using a frame buffer.
  • CTR cathode ray tube
  • Both the system memory and the frame buffer are typically implemented using arrays of Dynamic Random Access Memory (DRAM).
  • DRAM Dynamic Random Access Memory
  • the memory controller has exclusive access to the system memory
  • the graphics controller similarly has exclusive access to the frame buffer.
  • SMBA Shared Memory Buffer Architecture
  • UMA Unified Memory Architecture
  • a shared memory architecture as discussed above is implemented by providing an array of DRAM accessible by both the memory controller and the graphics controller, the associated memory space of the DRAM array being partitioned between system memory and the frame buffer.
  • the memory controller typically has access to all of the shared memory, including the po ⁇ ion designated as the frame buffer. Accordingly, if the frame buffer is not required, the memory controller may access that portion of memory designated as the frame buffer, and utilize that portion of the memory as system memory.
  • an arbitration unit or arbiter
  • the present invention seeks to address the performance penalties resulting from a shared memory configuration as discussed above.
  • a computer system including a memory controller and a graphics controller.
  • the computer system employs a Shared Frame Buffer Architecture, and accordingly has a shared memory in the form of a bank of DRAMs.
  • the shaied memory is accessible by both the memory and graphics controllers.
  • the shared memory includes at least one shared DRAM row in which a Shared Frame Buffer (SFB) aperture is defined.
  • An interface selectively provides access to the SFB aperture by the graphics controller or the memory controller. This facilitates concurrent access to the SFB aperture by the graphics controller, and to the remaining DRAM rows by the memory controller while maintaining the accessibility to the at least one shared DRAM row by the memoiy controller.
  • the SFB aperture is preferably defined at a low memory location within the shared memory.
  • the interface includes a selector circuit, such as, for instance, a multiplexer or Q-switch, coupled to receive respective memory address and control signals from the graphics controller and the memory controller, via a dedicated bus from each of these controllers.
  • the selector circuit is operable selectively to present either memory address to the shared DRAM row, in which the SFB aperture is defined, and also selectively to provide access to the shared DRAM row by either controller over a data bus.
  • the selector circuit receives a control input from a logic circuit, which determines whether a memory access request received from the memory controller is to an address in the at least one shared DRAM row, or to an address in the remaining DRAM rows.
  • a method of providing concurrent access by a graphics controller and a memory controller to a shared memory including a first memory portion and a second memory portion.
  • the first memory portion which may be single DRAM row, incorporates a Shared Frame Buffer (SFB) aperture
  • FFB Shared Frame Buffer
  • Figure 1 is a block diagram showing a computer system in which the present invention can be implemented.
  • Figure 2 is a block diagram illustrating a computer system incorporating a first embodiment of the present invention.
  • Figure 3 is a block diagram illustrating a computer system incorporating a second embodiment of the present invention.
  • Figure 4 is a block diagram illustrating a computer system incorporating a third embodiment of the present invention.
  • Figure 5 is a flowchart illustrating a method of providing concurrent access by first and second agents to a shared memory according to the invention.
  • a computer system 10 having as its principle components a processor 12, a memory controller 14, a memory arbiter 16, a graphics controller 18, and a shared memory 20.
  • the proces.sor 12 executes various instructions and is coupled to a host bus 22.
  • a bus bridge 24 facilitates communication between ihe host bus 22 and a peripheral bus 26.
  • the peripheral bus 26 may be operated according to ihe Peripheral Components Interconnect (PCI) Local Bus Specification Revision 2. 1 published June 1 , 1995, in which case the bus bridge 24 is a Host-to-PCl bridge.
  • the bus bridge 24 includes a data path unit 28 and a system controller 30.
  • the memory controller 14 and the memory arbitration unit 16 are implemented within the system controller 30.
  • ihe data path unit 28 comprises a 82438VX daia path unit
  • the system controller 30 comprises a 82437VX system controller, both of which are manufactured by Intel Corporation of Santa Clara, California.
  • the memory controller 14 and the memory arbitration unit 16 need not be implemented within a system controller, and may be independent functional units within the computer system 10.
  • the bus bridge 24 is coupled to the shared memory 20 by a dedicated memory bus 32.
  • the memory bus 32 comprises control and address lines 32. 1 and data lines 32.2. More specifically, control signals provided by the memory controller on the lines 32.1 include a Write Enable signal (WE), a Row Access Strobe signal (RAS#), and a Column Address Strobe signal (CAS#).
  • WE Write Enable signal
  • RAS# Row Access Strobe signal
  • CAS# Column Address Strobe signal
  • the memory controller 14 drives a Memory Address signal (MA) onto the control and addiess lines 32.1. Data is transferred to and from the shared memory 20 on the 64-bit data lines 32.1.
  • the graphics controller 18 is similarly coupled lo the shared memory 20 by a bus 34, which comprises control and address lines 34.1 , which are connected to the control and address lines 32.1 of the memory bus 32, and data lines 34.2, which are similarly connected to the data lines at 32.2.
  • the shared memory 20 is shown to comprise N rows of DRAM 20.1 to 20.N, each row of DRAM being coupled to receive control and address signals on lines 32.1 of the memory bus 32, and to receive and to output data on data lines at 32.2 of the memory bus 32. Each row of DRAM can accordingly be accessed by either the memory controller 14 or the graphics controller 18, depending on which of these agents has control of the memory bus 32.
  • DRAM row 20. N is shown to incorporate a shared frame buffer aperture 25, the frame buffer aperture 25 being designated for use by the graphics controller 18.
  • the frame buffer aperture 25 is located at the top of the system memoiy 20 reported to the operating system, and memory above the frame buffer 25 may never be allocated by the operating system.
  • the size and location of the frame buffer 25 within the shared memory 20 are definable and can be modified depending on the requirements of the computer system 10. Note that only a single set of control and address lines 32.1 and data lines 32.2 connect the shared memory 20 to the other components of the computer system 10 through a single port interface.
  • the memory coiuroller 14 is coupled to receive memory access requests from a number of components within the computer system 10, such as the processor 12, PCI masters and expansion bus bridges. The memory controller 14 may then read data from, or write data to, the shared memory 20 in response lo such memory access requests. For some operations, such as a DRAM refresh, the memory controller 14 acquires access to all portions of the shared memory 20. For other operations, such as memory access requests, the memory controller 14 is only required to access the system memory portion (i.e. addressable memory that has not been allocated to the shared frame buffer aperture 25 within the shaied memory 20). For still other operations, the memory controller 14 may be required to access the shared frame buffer aperture 25.
  • the graphics controller 18 accesses the shared frame buffer ape ⁇ ure 25 within the shared memory 20 for the purposes of storing graphics data therein for ultimate display on a display device (not shown), such as a cathode ray tube (CRT) or a liquid crystal display (LCD), which is coupled to the peripheral bus at 26.
  • a display device such as a cathode ray tube (CRT) or a liquid crystal display (LCD)
  • the graphics controller 18 is coupled to the peripheral bus 26, and receives
  • graphics, data and commands via the peripheral bus 26.
  • graphics, data and commands originate from the processor 12, or a number of other devices or components connected to the peripheral bus 26, in a manner well known in the art.
  • the arbitration unit 16 also termed a "memory arbiter" is provided for coordinating access to the memory bus 32 by the memory controller 14 and the graphics controller 18. More specifically, the arbitration unit 16 receives memory access requests from both the memory controller 14 and the graphics controller 18, determines the relative priority of these access requests, and then grants access to a particular agent, or device, depending on the relative priorities of the requests. In one embodiment, the memory controller 14 is granted default control of the memory bus 32 to access the shared memory 20. The arbitration unit 16 is coupled to receive a memory bus request signal (MREQ#) via line 35 from the graphics controller 18, which indicates to the arbitration unit 16 that the graphics controller 18 desires access to the memory bus 32.
  • MREQ# memory bus request signal
  • the arbitration unit 16 then arbitrates between the access request of the graphics controller 18 and contending access requests from the memory controller 14. If the arbitration unit 16 determines that the graphics controller 18 is to be given access to the shared memory 20, the arbitration unit 16 asserts a memory bus grant signal (MGNT#) on line 36.
  • MGNT# memory bus grant signal
  • a memory arbitration protocol under which the arbitration unit 16 may function is described in U.S. Patent Application serial number 08/516,495, entitled “Method and Apparatus for Arbitrating Access Requests to a Shared Computer System Memory by a Graphics Controller and a Memory Controller", filed August 17, 1995, and assigned to the assignee of the present invention.
  • the arbitration unit 16 is shown to be incorporated within the system controller 30, the arbitration unit 16 could be implemented as a separate circuit.
  • access requests from the graphics controller 18 contend with memory access requests from the memory controller 14, which in turn may originate from a number of other components within the computer systems 10. It is furthermore important to note that the graphics controller 18 in fact only requires access to the single DRAM row 20.N incorporating the shared frame buffer 25. To acquire such access, the graphics controller 18 must have control of the single memory bus 32. Accordingly, when the graphics controller 18 has control of the memory bus 32, the memory controller 14 is precluded from issuing access requests originating within itself or received from any one of a number of other devices. Accordingly, system perfomiance penalties may be suffered as a result of the lowered memory bandwidth resulting from the shared memory configuration.
  • FIG. 2 there is shown a computer system 210 for implementing a method of providing concurrent access by at least two agents, such as a memory controller 214 and a graphics controller 218 to a shared memory 220.
  • the shared memory 220 is shown to include only two memory portions, in the form of DRAM rows 220.1 and 220.2.
  • a shared frame buffer aperture 225 is implemented in DRAM row 220.2.
  • the computer system 210 comprises a proces.sor 212 coupled to a host bus 222, which communicates with a peripheral bus 226 via a bus bridge 224.
  • the bus bridge 224 incorporates a data path unit 228 and a system controller 230, in which the memory controller 214 and a memory arbitration unit 216 may be implemented.
  • the arbitration unit 216 receives memory request signals ( MREQ#) via line 235 from the graphics controller 218 and issues memoiy access grant signals (MGNT#) on line 236.
  • the computer system 210 furthermore incorporates an interface 240 coupled between the shared memory 220, and the bus bridge 224 and the graphics controller 218.
  • the interface 240 is coupled to the memory bus 232, which comprises control and address lines 232.1 and data lines 232.2.
  • the interface 240 is also coupled to a frame buffer bus 234, comprising control and address lines 234.1 and data lines 234.2.
  • the interface 240 is furthermore coupled to the shaied memoiy 220 by two further buses, namely buses 242 and 244.
  • the bus 242 is dedicated to addressing and providing access to the DRAM row 220.2, which includes the shared frame buffer aperture 225.
  • the bus 244 provides access to the remaining rows of DRAM within the shared memory 220, which in the illustrated example comprises only DRAM row 220.1.
  • the interface 240 facilitates concurrent access by the memory controller 214 and the graphics controller 218 to the shared memory 220 when the memory controller 214 requests access to a memory location in a first portion of the shared memory 220, namely DRAM row 220.1 , and when the graphics controller 218 requests access to a memory location in a second portion of the shared memory 220, namely DRAM row 220.2.
  • the switches 246. 1 and 246.2 within the interface 240 are switched to a first state, by asserting an appropriate signal on line 248, this signal having been generated by the logic circuitry 231 incorporated within the system controller 230.
  • Q- switch 246.1 provides a data path between data lines 244.2 and 232.2, so as to allow data to be propagated crizot the data path unit 228 and DRAM row 220.1.
  • the memory controller 214 is able to address DRAM row 220.1 via control and address line 244.2.
  • Q-switch 246.2 creates a signal path between control and address line 234.1 and 242.1 , so as to allow the graphics controller 218 to control and access DRAM row 220.2.
  • the data can then be propagated between DRAM row 220.2 and the graphics controller 218 via data lines 234.2.
  • memory controller 214 is concurrently able to access DRAM row 220. 1.
  • graphics controller 218 is concurrently able to access the shared buffer aperture 222 in DRAM row 220.2.
  • DRAM row 220.2 comprises system memory and thus memory controller 214 requires access to DRAM row 220.2, and conflicting requests from the memory controller 216 and the graphics controller 218 for access to DRAM row 220.2 may be generated.
  • Arbitration unit 2 16 then performs an arbitration protocol and grams access to the appropriate controller by placing the Q- switches 246. 1 and 246.2 in appropriate stales. Thus, concurrent access is not facilitated, as the memory access requests from the graphics and memory controllers are to the same DRAM row 220.2.
  • Q-swiiches 246.1 and 246.2 which may be implemented as uni-directional or bi-directional field effect transistors (FETs), may be substituted by any suitable selector means, such as multiplexors, or tri-state buffers.
  • FETs field effect transistors
  • the shared frame buffer 422 As operating system loads and accesses are often to memory addresses located at or adjacent the top of the memory, it is desirable to locate the shared frame buffer 422 at a memory location just above the DOS application region within the memory 420. By locating the shared frame buffer 422 at a lower location within the memory 420, the probability of the memory controller 414 and the graphics controller 418 requesting access to the same DRAM row is lessened. Accordingly, the concurrent access capability of the present invention can be more fully utilized.
  • the Shared Frame Buffer need not be located within a single DRAM row as discussed above, but could be fragmented and located on a plurality of DRAM rows.
  • teachings of the present invention can be extended to provide concurrent access by a graphics controller to those DRAM rows in which the SFB resides, and by the memory controller to the other DRAM rows.
  • step 550 it is determined whether the graphics controller access request is to a memory address within the same DRAM row as the address of the memory access requests received from the memory controller. If the memory access requests of the respective controllers are to memory addresses within the same DRAM row, the method proceeds to step 560 for arbitration between the access requests. On completion of arbitration, an arbitrator unit will grant access to either the graphics controller or the memory controller at step 540. Alternatively, if at step 550, it is determined that the graphics controller access request is to a memory location not within the same DRAM row, concurrent access to the shared memory is granted to both controllers at step 570.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
  • Image Input (AREA)
  • Image Processing (AREA)
  • Dram (AREA)
PCT/US1997/010447 1996-06-27 1997-06-13 A method and apparatus for providing concurrent access by a plur ality of agents to a shared memory Ceased WO1997050042A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
AU33976/97A AU3397697A (en) 1996-06-27 1997-06-13 A method and apparatus for providing concurrent acces by a plurality of agents to a shared memory
JP50322998A JP3976342B2 (ja) 1996-06-27 1997-06-13 複数のエージェントから共用メモリに同時にアクセスできるようにする方法および装置
DE69724463T DE69724463T2 (de) 1996-06-27 1997-06-13 Verfahren und gerät um einen gleichzeitigen zugriff von mehreren agenten auf einem gemeinsamen speicher zu gewährleisten
EP97930056A EP0972251B1 (en) 1996-06-27 1997-06-13 A method and apparatus for providing concurrent acces by a plurality of agents to a shared memory
KR1019980710671A KR100317517B1 (ko) 1996-06-27 1997-06-13 복수의에이전트에의한공유메모리로의동시액세스를제공하는방법및장치

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/672,099 1996-06-27
US08/672,099 US5815167A (en) 1996-06-27 1996-06-27 Method and apparatus for providing concurrent access by a plurality of agents to a shared memory

Publications (1)

Publication Number Publication Date
WO1997050042A1 true WO1997050042A1 (en) 1997-12-31

Family

ID=24697142

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1997/010447 Ceased WO1997050042A1 (en) 1996-06-27 1997-06-13 A method and apparatus for providing concurrent access by a plur ality of agents to a shared memory

Country Status (8)

Country Link
US (1) US5815167A (https=)
EP (1) EP0972251B1 (https=)
JP (1) JP3976342B2 (https=)
KR (1) KR100317517B1 (https=)
AU (1) AU3397697A (https=)
DE (1) DE69724463T2 (https=)
TW (1) TW358180B (https=)
WO (1) WO1997050042A1 (https=)

Families Citing this family (60)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6058459A (en) 1996-08-26 2000-05-02 Stmicroelectronics, Inc. Video/audio decompression/compression device including an arbiter and method for accessing a shared memory
TW360823B (en) * 1996-09-30 1999-06-11 Hitachi Ltd Data processor and graphic processor
US5941968A (en) * 1997-04-14 1999-08-24 Advanced Micro Devices, Inc. Computer system for concurrent data transferring between graphic controller and unified system memory and between CPU and expansion bus device
US6282625B1 (en) 1997-06-25 2001-08-28 Micron Electronics, Inc. GART and PTES defined by configuration registers
US6249853B1 (en) 1997-06-25 2001-06-19 Micron Electronics, Inc. GART and PTES defined by configuration registers
US6118462A (en) * 1997-07-01 2000-09-12 Memtrax Llc Computer system controller having internal memory and external memory control
US6057862A (en) * 1997-07-01 2000-05-02 Memtrax Llc Computer system having a common display memory and main memory
JPH11120156A (ja) * 1997-10-17 1999-04-30 Nec Corp マルチプロセッサシステムにおけるデータ通信方式
US6965974B1 (en) * 1997-11-14 2005-11-15 Agere Systems Inc. Dynamic partitioning of memory banks among multiple agents
US6091431A (en) * 1997-12-18 2000-07-18 Intel Corporation Method and apparatus for improving processor to graphics device local memory performance
US6157398A (en) * 1997-12-30 2000-12-05 Micron Technology, Inc. Method of implementing an accelerated graphics port for a multiple memory controller computer system
US7071946B2 (en) * 1997-12-30 2006-07-04 Micron Technology, Inc. Accelerated graphics port for a multiple memory controller computer system
US6252612B1 (en) * 1997-12-30 2001-06-26 Micron Electronics, Inc. Accelerated graphics port for multiple memory controller computer system
US6272584B1 (en) * 1998-09-10 2001-08-07 Compaq Computer Corporation System board with consolidated EEPROM module
DE60007252T2 (de) * 1999-03-05 2004-09-16 Amulet Technologies, LLC, Campbell Graphischer benutzerschnittstellentreiber für eingebettete systeme
US6601147B1 (en) * 1999-03-31 2003-07-29 International Business Machines Corporation Computer system and method for maintaining an integrated shared buffer memory in a group of interconnected hosts
EP1059586B1 (en) * 1999-06-09 2004-09-08 Texas Instruments Incorporated Shared memory with programmable size
US6469703B1 (en) 1999-07-02 2002-10-22 Ati International Srl System of accessing data in a graphics system and method thereof
US6526462B1 (en) * 1999-11-19 2003-02-25 Hammam Elabd Programmable multi-tasking memory management system
US6774903B1 (en) * 2000-11-06 2004-08-10 Ati International Srl Palette anti-sparkle enhancement
US7379069B2 (en) * 2001-02-15 2008-05-27 Sony Corporation Checkerboard buffer using two-dimensional buffer pages
US6791557B2 (en) * 2001-02-15 2004-09-14 Sony Corporation Two-dimensional buffer pages using bit-field addressing
US6801204B2 (en) * 2001-02-15 2004-10-05 Sony Corporation, A Japanese Corporation Checkerboard buffer using memory blocks
US6831650B2 (en) * 2001-02-15 2004-12-14 Sony Corporation Checkerboard buffer using sequential memory locations
US6831651B2 (en) * 2001-02-15 2004-12-14 Sony Corporation Checkerboard buffer
US6795079B2 (en) * 2001-02-15 2004-09-21 Sony Corporation Two-dimensional buffer pages
US6768490B2 (en) * 2001-02-15 2004-07-27 Sony Corporation Checkerboard buffer using more than two memory devices
US6850241B2 (en) * 2001-02-15 2005-02-01 Sony Corporation Swapped pixel pages
US6992674B2 (en) * 2001-02-15 2006-01-31 Sony Corporation Checkerboard buffer using two-dimensional buffer pages and using state addressing
US7205993B2 (en) * 2001-02-15 2007-04-17 Sony Corporation Checkerboard buffer using two-dimensional buffer pages and using memory bank alternation
US6828977B2 (en) * 2001-02-15 2004-12-07 Sony Corporation Dynamic buffer pages
US6831649B2 (en) * 2001-02-15 2004-12-14 Sony Corporation Two-dimensional buffer pages using state addressing
US7088369B2 (en) * 2001-02-15 2006-08-08 Sony Corporation Checkerboard buffer using two-dimensional buffer pages and using bit-field addressing
US6803917B2 (en) * 2001-02-15 2004-10-12 Sony Corporation Checkerboard buffer using memory bank alternation
US6765580B2 (en) * 2001-02-15 2004-07-20 Sony Corporation Pixel pages optimized for GLV
US7038691B2 (en) * 2001-02-15 2006-05-02 Sony Corporation Two-dimensional buffer pages using memory bank alternation
US6765579B2 (en) * 2001-02-15 2004-07-20 Sony Corporation Pixel pages using combined addressing
US6622203B2 (en) * 2001-05-29 2003-09-16 Agilent Technologies, Inc. Embedded memory access method and system for application specific integrated circuits
US7174415B2 (en) * 2001-06-11 2007-02-06 Zoran Corporation Specialized memory device
US20030058368A1 (en) * 2001-09-24 2003-03-27 Mark Champion Image warping using pixel pages
US6965980B2 (en) * 2002-02-14 2005-11-15 Sony Corporation Multi-sequence burst accessing for SDRAM
US7185126B2 (en) * 2003-02-24 2007-02-27 Standard Microsystems Corporation Universal serial bus hub with shared transaction translator memory
US6959355B2 (en) * 2003-02-24 2005-10-25 Standard Microsystems Corporation Universal serial bus hub with shared high speed handler
US6874042B2 (en) * 2003-03-11 2005-03-29 Dell Products L.P. System and method for using a switch to route peripheral and graphics data on an interconnect
JP2005165592A (ja) * 2003-12-02 2005-06-23 Matsushita Electric Ind Co Ltd データ転送装置
JP2005222245A (ja) * 2004-02-04 2005-08-18 Renasas Northern Japan Semiconductor Inc プロセッサ
JP4500610B2 (ja) * 2004-07-07 2010-07-14 キヤノン株式会社 映像信号処理装置、メモリ制御方法、及びプログラム
US20060227759A1 (en) * 2004-09-14 2006-10-12 Bohm Mark R Peripheral Sharing USB Hub
US20060059293A1 (en) * 2004-09-14 2006-03-16 Henry Wurzburg Universal serial bus switching hub
US7433990B2 (en) * 2006-01-24 2008-10-07 Standard Microsystems Corporation Transferring system information via universal serial bus (USB)
US7523243B2 (en) * 2006-04-14 2009-04-21 Standard Microsystems Corporation Multi-host USB device controller
US7480753B2 (en) * 2006-04-27 2009-01-20 Standard Microsystems Corporation Switching upstream and downstream logic between ports in a universal serial bus hub
US20080005262A1 (en) * 2006-06-16 2008-01-03 Henry Wurzburg Peripheral Sharing USB Hub for a Wireless Host
KR100888427B1 (ko) * 2006-09-15 2009-03-11 엠텍비젼 주식회사 공유 메모리를 구비한 디지털 처리 장치 및 데이터 출력방법
US7949815B2 (en) * 2006-09-27 2011-05-24 Intel Corporation Virtual heterogeneous channel for message passing
US20090063717A1 (en) * 2007-08-28 2009-03-05 Bohm Mark R Rate Adaptation for Support of Full-Speed USB Transactions Over a High-Speed USB Interface
US8180975B2 (en) * 2008-02-26 2012-05-15 Microsoft Corporation Controlling interference in shared memory systems using parallelism-aware batch scheduling
KR101283482B1 (ko) * 2009-12-11 2013-07-12 한국전자통신연구원 Ｐｃｉ 익스프레스 프로토콜 처리 장치
US8397006B2 (en) * 2010-01-28 2013-03-12 Freescale Semiconductor, Inc. Arbitration scheme for accessing a shared resource
US8799532B2 (en) 2011-07-07 2014-08-05 Smsc Holdings S.A.R.L. High speed USB hub with full speed to high speed transaction translator

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4156904A (en) * 1976-08-25 1979-05-29 Hitachi, Ltd. Computer systems having a common memory shared between a central processor and a CRT display
US5450542A (en) * 1993-11-30 1995-09-12 Vlsi Technology, Inc. Bus interface with graphics and system paths for an integrated memory system
US5459846A (en) * 1988-12-02 1995-10-17 Hyatt; Gilbert P. Computer architecture system having an imporved memory

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4980828A (en) * 1988-11-25 1990-12-25 Picker International, Inc. Medical imaging system including use of DMA control for selective bit mapping of DRAM and VRAM memories
WO1995015528A1 (en) * 1993-11-30 1995-06-08 Vlsi Technology, Inc. A reallocatable memory subsystem enabling transparent transfer of memory function during upgrade

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4156904A (en) * 1976-08-25 1979-05-29 Hitachi, Ltd. Computer systems having a common memory shared between a central processor and a CRT display
US5459846A (en) * 1988-12-02 1995-10-17 Hyatt; Gilbert P. Computer architecture system having an imporved memory
US5450542A (en) * 1993-11-30 1995-09-12 Vlsi Technology, Inc. Bus interface with graphics and system paths for an integrated memory system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP0972251A4 *

Also Published As

Publication number Publication date
EP0972251B1 (en) 2003-08-27
US5815167A (en) 1998-09-29
JP2001523361A (ja) 2001-11-20
EP0972251A4 (en) 2000-01-19
JP3976342B2 (ja) 2007-09-19
DE69724463D1 (de) 2003-10-02
AU3397697A (en) 1998-01-14
EP0972251A1 (en) 2000-01-19
DE69724463T2 (de) 2004-07-08
KR100317517B1 (ko) 2002-02-19
KR20000022251A (ko) 2000-04-25
TW358180B (en) 1999-05-11

Similar Documents

Publication Publication Date Title
US5815167A (en) Method and apparatus for providing concurrent access by a plurality of agents to a shared memory
US5911149A (en) Apparatus and method for implementing a programmable shared memory with dual bus architecture
US5613075A (en) Method and apparatus for providing deterministic read access to main memory in a computer system
US6076139A (en) Multimedia computer architecture with multi-channel concurrent memory access
EP1163593B1 (en) Apparatus for communicating between multiple functional units in a computer environment
GB2216368A (en) Bus arbitration method and apparatus
JPH05120129A (ja) 多重バンク大域メモリ・カード
US5717873A (en) Deadlock avoidance mechanism and method for multiple bus topology
GB2287621A (en) High performance symmetric arbitration protocol with support for I/O requirements
JP3039557B2 (ja) 記憶装置
US7174403B2 (en) Plural bus arbitrations per cycle via higher-frequency arbiter
US5640519A (en) Method and apparatus to improve latency experienced by an agent under a round robin arbitration scheme
US6317813B1 (en) Method for arbitrating multiple memory access requests in a unified memory architecture via a non unified memory controller
KR100869938B1 (ko) 주문형 집적 회로
US20060282588A1 (en) Processor system that allows for simultaneous access by multiple requestors to a target with multiple ports
US5748203A (en) Computer system architecture that incorporates display memory into system memory
US6249847B1 (en) Computer system with synchronous memory arbiter that permits asynchronous memory requests
US20030018859A1 (en) Arbitration in local system for access to memory in a distant subsystem
CA2239426A1 (en) Shared memory system
US20050268023A1 (en) Multi-port random access memory
KR100210404B1 (ko) 공유 메모리 억세스 제어장치
EP0818008B1 (en) Dynamic ram in a microprocessor system
JP2900892B2 (ja) 情報処理装置
GB2318487A (en) Bus arbitration system
JPH07262125A (ja) 情報処理装置

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AL AM AT AT AU AZ BA BB BG BR BY CA CH CN CU CZ CZ DE DE DK DK EE EE ES FI FI GB GE GH HU IL IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SK TJ TM TR TT UA UG UZ VN YU ZW AM AZ BY KG KZ MD RU TJ TM

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH KE LS MW SD SZ UG ZW AT BE CH DE DK ES FI FR GB GR

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 1019980710671

Country of ref document: KR

ENP Entry into the national phase

Ref country code: JP

Ref document number: 1998 503229

Kind code of ref document: A

Format of ref document f/p: F

WWE Wipo information: entry into national phase

Ref document number: 1997930056

Country of ref document: EP

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

NENP Non-entry into the national phase

Ref country code: CA

WWP Wipo information: published in national office

Ref document number: 1997930056

Country of ref document: EP

WWP Wipo information: published in national office

Ref document number: 1019980710671

Country of ref document: KR

WWG Wipo information: grant in national office

Ref document number: 1019980710671

Country of ref document: KR

WWG Wipo information: grant in national office

Ref document number: 1997930056

Country of ref document: EP