Classifications

• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
  • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
  • C23C14/48—Ion implantation
• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
  • C23C14/58—After-treatment
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
  • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
  • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D1/00—Resistors, capacitors or inductors
  • H10D1/60—Capacitors
  • H10D1/68—Capacitors having no potential barriers
  • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures

Definitions

• the present invention relates to a process for producing a thin film of solid material, this material possibly being a dielectric, a conductor or a semi-insulator. It can be crystalline or not. It may be an amorphous or polycrystalline semiconductor whose crystallographic planes are of any orientation. This material may have
• a particularly interesting application of the method according to the invention relates to the production of ferroelectric capacitor memories.
• j _5 Numerous processes are known for producing thin films of solid material. These methods depend on the nature of the material and the thickness of the desired film. It is thus possible to deposit thin films of a solid material on the surface of a part by
• a thin film can also be obtained by thinning a wafer of the desired material by mechanical or chemical abrasion, the thin film obtained then being glued or fixed to a part serving as a support.
• the fixing of a thin film 25 on the surface of a part is intended to modify the properties of the part superficially.
• a first implantation step by bombardment of the flat face of the wafer by means of ions creating, in the volume of the wafer and at a depth close to the depth of penetration of the ions, a layer of "gaseous microbubble" separating the wafer in a lower region constituting the mass of the substrate and an upper region constituting the thin film, the ions being chosen from ions of rare gas or hydrogen gas;
• a second step of bringing the planar face of the wafer into intimate contact with a support made up of at least one layer of rigid material can be achieved for example using an adhesive substance or by the effect of a prior preparation of the surfaces and optionally a heat and / or electrostatic treatment to promote interatomic connections between the support and the brochure;
• This temperature is greater than or equal to about 400 ° C for silicon.
• This implantation is capable of creating a layer of gaseous microbubbles which will end at the end of the heat treatment in a fracture zone.
• the heat treatment is carried out at a temperature sufficient to create, by crystalline rearrangement effect in the semiconductor material such as for example by the growth effect of the microcavities and / or by the pressure effect of the microbubbles, the zone fracture and separation between the two regions.
• cavities or microbubbles can be observed or not by transmission electron microscopy.
• a gas such as, for example, hydrogen
• microbubbles can be observed or not by transmission electron microscopy.
• silicon In the case of silicon, one can have microcavities whose size can vary from a few nm to a few hundred nm.
• these cavities can only be observed during the heat treatment step, step during which nucleation is then carried out to allow the end of the heat treatment to be achieved. the fracture between the thin film and the rest of the substrate.
• the first ion implantation step is carried out by presenting a plane face of a wafer of semiconductor material to an ion beam, the plane of this plane face being either substantially parallel to a main crystallographic plane in the case where the semiconductor material is perfectly monocrystalline, or slightly inclined with respect to a main crystallographic plane of the same indices for all the grains in the case where the material is polycrystalline.
• gas microbubbles means any cavity or microcavity generated by the implantation of ions of hydrogen gas or of rare gases in the material.
• the cavities can be in very flattened form, that is to say of low height, for example of the order of a few inter-atomic distances, as well as in substantially spherical form or in any other form different from the two forms. previous.
• cavities may or may not contain a free gas phase and / or gas atoms from the implanted ions fixed on atoms of the material forming the walls of the cavities. These cavities are generally called in Anglo-Saxon terminology “platelets”, “microblisters” or even “bubbles”.
• the heat treatment is carried out at a sufficient temperature (for the duration of the treatment applied) to create the separation between the two regions. The time and temperature pair of the heat treatment depends on the dose of implanted ions.
• the process described in document FR-A-2 681 472 relates to the production of a thin film from a substrate of semiconductor material with a crystalline structure.
• the progress of the different stages of the process has been explained as resulting from the interaction between implanted ions and the crystal lattice of the semiconductor material.
• the inventors of the present invention were surprised to find that the implantation of hydrogen gas ions or rare gases can also cause the formation of microcavities in solid materials other than a crystalline semiconductor material, and that a treatment subsequent heat can cause the mass of the material to be separated into two parts at the level of the microcavities. Indeed, the heat treatment leads, whatever the type of solid material, to the coalescence of the microcavities which bring weakening of the structure at the level of the microcavity layer. This embrittlement allows the separation of the material under the effect of internal stresses and / or pressure in the microcavities, this separation being able to be natural or assisted by application of external stresses.
• microcavity layer is meant an area containing microcavities which may be located at different depths and may or may not be adjacent to each other.
• the subject of the invention is therefore a process for producing a thin film of solid material, crystalline or not, chosen from a dielectric material, a conductive material, a semi-insulating material, an unordered semiconductor material, characterized in that 'It consists in subjecting a substrate of said solid material to the following steps:
• an ion implantation step during which one face of the substrate is bombarded with ions chosen from ions of rare gases and hydrogen gas, in order to create, in the volume of the substrate and at a depth close to the average depth of ion penetration, a layer of microcavities separating the substrate into two regions, - a heat treatment step intended to bring the layer of microcavities to a temperature sufficient to cause separation between the two regions of the substrate either naturally or with the using an applied constraint.
• a step of fixing said face of the substrate to a support This step may be necessary in case the thin layer is not rigid enough by itself. She may be desired since, generally, the thin layer is intended to be placed on a support. In this case, the support must be able to withstand the final heat treatment step.
• the fixing of said face of the substrate to the support can be done by means of an adhesive substance or by means of a treatment promoting interatomic bonds.
• This method according to the invention applies in particular to obtaining a thin film of ferroelectric material, from a substrate of ferroelectric material, and to its fixing on a support.
• the support being made of semiconductor material
• at least one electronic control circuit is produced on one face of this support, the thin film of ferroelectric material is fixed on the support so as to serve as a dielectric for a memory capacity controlled by said circuit of electronic control to thus constitute a memory point.
• the electronic control circuit is of the MOS transistor type.
• the method according to the invention can also be applied to obtain a thin film of sapphire on a support, a thin film of corrosion-resistant metal on a support or a thin film of magnetic material on a support.
• FIG. 1 is a partial view in cross section of an integrated circuit produced on one face of a semiconductor substrate
• FIG. 2 illustrates the step of ion implantation carried out through one face of a substrate made of ferroelectric material, according to the present invention
• FIG. 3 illustrates the fixing step according to the present invention, consisting in adhering the face of the semiconductor substrate where the integrated circuit has been produced on the face of the substrate of ferroelectric material having been bombarded with ions, 10.
• FIG. 4 illustrates the step of the method according to the invention leading to the separation of the thin film from the rest of the substrate made of ferroelectric material,
• FIG. 5 is a partial sectional view of a memory point with ferroelectric capacitor
• the electronic circuit shown in section in Figure 1 was produced using current microelectronics techniques.
• the so-called “plug” technique, the mechanochemical oxidation planarization technique and the so-called “Damascene” technique have been used to make connections buried in an oxide but flush with the surface thereof.
• the circuit was developed on one side 2 of a P-type silicon substrate 1. From side 2, boxes were made, only boxes N, 31 and 32 and type N + being represented in this figure, and field oxide was grown to obtain isolation zones 41 and 42 to the left of the box 31 and to the right of the box 33.
• the boxes 31 and 33 are intended to constitute the drains of two MOS type transistors , the box 32 constituting their common source.
• word lines 51 and 52 of polycrystalline silicon have been deposited, with the interposition of thin oxide layers 61 and 62.
• Word lines 51 and 52 have been covered with layers of insulating material 65 and 66. This insulating material also covers the zones 41 and 42 in the form of layers 63 and 64.
• a line of bits 8 made of aluminum provides electrical contact with the source 32.
• An oxide layer 7 has been deposited to cover all of the elements described previously. In the oxide layer 7 are deposited flush electrodes 91 and 92 made of platinum and provided with TiN barrier sublayers. The electrodes 91 and 92 are connected by "plugs" 11 and 12 to the drains 31 and 33 of the transistors. They are buried, the circuit then having an external planar face 15.
• a thin film of ferroelectric material according to the method of the present invention, this thin film being intended to form. the capacitor dielectric.
• FIG. 2 represents, seen from the side, a substrate 100 made of ferroelectric material, for example 5 made of PbZrTi ⁇ 3 (PZT).
• the flat face 101 of the substrate 100 is bombarded with ions, for example hydrogen ions of energy 200 keV and at a dose equal to ÎO-L 'cm ⁇ 2.
• the ion bombardment is shown by arrows in Figure 2.
• the implanted ions Q induce microcavities which are distributed in a layer 102 in the vicinity of a plane parallel to the planar face 101, this plane being located at a distance from the planar face 101 corresponding to the average depth of penetration of the ions.
• the thickness of region 103 is about 800 nm.
• Layer 102 is formed by a layer of microcavities.
• planar face 101 of the substrate made of f-irroelectric material 100 and the planar face 15 of the electronic circuit 5 produced on the semiconductor substrate 1 are treated for example chemically so as to make them adherent to one another by simple contacting.
• FIG. 3 represents the two associated substrates 100 and 1, the planar face 15 of the semiconductor substrate 1 adhering to the planar face 101 of the substrate 100 made of ferroelectric material.
• the assembly is then heat treated at approximately 500 ° C., which has the consequence of inducing a separation of the two regions 103 and 104 of the substrate 100 made of ferroelectric material at the level of the layer.
• the external face 105 of the thin film 103 is possibly finely polished.
• the device shown in FIG. 5 is obtained where a memory point with two capacitors is formed by the deposition on the flat face 105 of the thin film 103 of a common electrode 16.
• a final encapsulation can be added to protect the entire circuit.
• Such a ferroelectric thin film can also be used to form a layer of ferroelectric material deposited directly on the silicon to produce MOS transistors where the control gate is replaced by this ferroelectric layer whose state of polarization determines the blocked or passing state. of the transistor.
• the application of the process according to the invention to dielectric materials makes it possible in particular to produce anti-wear layers of sapphire ( ⁇ > -alumina) on glass or silica supports.
• a thin layer of alumina makes it possible to protect the glass or the silica serving as a support, for example for optical components, from wear and scratches.
• An implantation of hydrogen ions of approximately 8.10 ⁇ atoms / cm ⁇ and 110 keV of energy makes it possible to obtain a thin layer or sapphire of approximately 1 ⁇ m in thickness. This small thickness is compatible with any subsequent shaping of the glass or of the silica serving as a support for producing optics, for example.
• the method according to the invention also applies to metallic materials. It makes it possible to produce anti-corrosion layers and diffusion barriers.
• metallic monocrystalline layers instead of polycrystalline layers brings a significant advantage in terms of efficiency as diffusion barrier to chemical attack and corrosion in particular. Indeed, the existence of significant diffusion phenomena at grain boundaries, in polycrystalline materials, limits the effectiveness of the thin layers produced in these materials.
• Another example of application relates to the production of memories using, for the storage of information, magnetic domains (bubbles) and the walls of magnetic domains (Bloch walls).
• magnetic domains bubbles
• Bloch walls the walls of magnetic domains
• the method according to the invention makes it possible to transfer a thin layer of ferrimagnetic garnet material onto a silicon substrate serving as a support and comprising integrated circuits.
• integrated circuits combine electronic, logic and analog devices, integrated micro-windings capable of generating localized magnetic fields so as to drive, move and detect the magnetic domains or the walls of the domains in the thin layer of ferrimagnetic garnet.

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• Chemical & Material Sciences (AREA)
• Engineering & Computer Science (AREA)
• Metallurgy (AREA)
• Chemical Kinetics & Catalysis (AREA)
• Organic Chemistry (AREA)
• Mechanical Engineering (AREA)
• Materials Engineering (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• Power Engineering (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Semiconductor Memories (AREA)
• Physical Vapour Deposition (AREA)
• Semiconductor Integrated Circuits (AREA)

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• 1996
  • 1996-05-15 FR FR9606085A patent/FR2748850B1/fr not_active Expired - Fee Related
• 1997
  • 1997-05-13 EP EP97924080A patent/EP0902843B1/fr not_active Expired - Lifetime
  • 1997-05-13 DE DE69701571T patent/DE69701571T2/de not_active Expired - Lifetime
  • 1997-05-13 JP JP54059597A patent/JP4659929B2/ja not_active Expired - Lifetime
  • 1997-05-13 KR KR1019980709202A patent/KR20000011051A/ko not_active Withdrawn
  • 1997-05-13 US US09/147,266 patent/US6190998B1/en not_active Expired - Lifetime
  • 1997-05-13 WO PCT/FR1997/000842 patent/WO1997043461A1/fr not_active Ceased
• 2008
  • 2008-08-21 JP JP2008213117A patent/JP2009010409A/ja active Pending

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