WO1997033309A1 - Procede de formation d'un dispositif a semi-conducteur presentant des tranchees - Google Patents

Procede de formation d'un dispositif a semi-conducteur presentant des tranchees Download PDF

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Publication number
WO1997033309A1
WO1997033309A1 PCT/GB1997/000615 GB9700615W WO9733309A1 WO 1997033309 A1 WO1997033309 A1 WO 1997033309A1 GB 9700615 W GB9700615 W GB 9700615W WO 9733309 A1 WO9733309 A1 WO 9733309A1
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Prior art keywords
trench
trenches
layer
wider
substrate
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PCT/GB1997/000615
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English (en)
Inventor
Jonathan Leslie Evans
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Totem Semiconductor Ltd.
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Publication of WO1997033309A1 publication Critical patent/WO1997033309A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0335—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate

Definitions

  • the present invention relates to a method of manufacturing a semiconductor device (such as a trench gated semiconductor power device) .
  • the two trenches may comprise different parts of a single trench.
  • step (i) may comprise forming an array of interlinked trenches where one area of the device (for instance a trench contact area) has trench widths wider than in another area of the device (for instance an active area) .
  • the trenches may be connected for electrical continuity.
  • the two trenches may be separate and unconnected.
  • the width of the narrower trench needs to be less than twice the thickness of the layer of material.
  • An example of material which is "grown" is polysilicon.
  • the narrower trench could be filled with a layer of material which is thinner than half of the trench width.
  • the conformal deposition method comprises Chemical Vapour Deposition (CVD) , or spin-on deposition using material in a solvent or a flowed glass.
  • CVD Chemical Vapour Deposition
  • Conformal deposition results in the substrate being deposited in a fashion which attempts to maintain a constant thickness across the topology. Therefore the conformal deposition will tend to fill trenches with a dimension less than twice the thickness of the layer of material, but will cover with constant thickness surfaces of areas wider than this (i.e. the surfaces of the wider trench) .
  • the narrower trench may not be completely filled during the conformal deposition, but in general the level of material deposited in the narrow trench will be greater than the level in the wider trench.
  • the method of the present invention may be employed in one or more stages of the semiconductor device fabrication process.
  • the semiconductor device comprises a trench gated semiconductor power device such as a power MOSFET, power MESFET or power IGBT.
  • the device may comprise a logic transistor.
  • the wider trench typically comprises a gate contact trench which is subsequently filled with gate contact material, and the narrower trench comprises an active gate trench.
  • the device may comprise a memory cell. In this case the wider trench typically forms the contact to a buried cell (the narrower trench) .
  • step (ii) The type of material deposited in step (ii) will depend upon the type of device being fabricated, and the particular stage of the fabrication process.
  • the method may comprise conformal deposition followed by isotropic etching and selective etch back of the gate contact trench which results in a deeper gate contact trench. This allows a greater thickness of top ⁇ side contact deposition without the source contact (which contacts with the narrower trench) shorting out with the gate contact (which contacts with the gate contact trench) .
  • the substrate may be conformally deposited with a conductive gate electrode material such as polysilicon. The polysilicon can then be anisotropically etched back to below the silicon substrate surface, and removing the polysilicon from the bottom of the gate contact trench.
  • the method of the present invention may be employed in a planarization step in which material such as BPSG is conformally deposited and isotropically etched back to remove all of the glass in the gate contact trench.
  • the method of fabricating the semiconductor device only uses a single mask, the mask being used to form the at least two trenches in the substrate. Subsequent steps in the fabrication process do not require a conventional mask, the function of the conventional mask being carried out by the material which is left in the bottom of the narrower trench.
  • Figure 1 compares conformal deposition with non- conformal deposition
  • Figure 2 illustrates isotropic and anisotropic etches of the conformally deposited material
  • Figure 3a is a plan view of a substrate after the trenches have been etched, and before deposition;
  • Figure 3b is an enlarged plan view of part of the substrate shown in Figure 3a;
  • Figures 3c to 15 are schematic cross-sections along line A of the substrate after various stages in a method of manufacturing a device according to the present invention. in which:-
  • Figure 3c shows the substrate after trench etch
  • Figure 4 shows conformal deposition which fills the trenches
  • Figure 5 shows an optional selective etch back of the gate contact area followed by thick oxide deposition/growth.
  • Figure 6 shows conformal polysilicon deposition
  • Figure 7 shows an anisotropic etch back of polysilicon to below the silicon surface level
  • Figure 8 shows optional deposition of a silicide material (such as tantalum silicide) ;
  • Figure 9 shows the formation of the source/drain/emitter regions
  • Figure 10 shows planarization of the active trenches; (usually an oxide/glass material e.g. BPSG or spin on glass) ;
  • oxide/glass material e.g. BPSG or spin on glass
  • Figure 11 shows the trench planarisation which is completed with an etch back
  • Figure 12 shows final metallization
  • Figure 13 shows how the optional etching of the polysilicon after trench planarization (Fig. 11) allows a thicker top-side metallization to take place;
  • Figure 14 shows how a combination of the above polysilicon etch can be combined with the optional selective etch back and oxidation of Fig. 5;
  • Figure 15 shows the final stage of the processing being a passivation.
  • Figure 1 contrasts a method of conformal deposition (Figure la) with a process of non-conformal deposition ( Figure lb) .
  • a substrate 30 comprising a wider trench 31 and a narrower trench 32 are conformally coated with a layer of material 33.
  • the width of the trench 32 is less than twice the thickness of the layer 33, the narrower trench 32 is filled whilst larger areas (including the wider trench 31) are merely covered.
  • An example of a non-conformal deposition is evaporation of metal.
  • the layer of metal 34 does not coat the side walls of the trenches and fills the narrower trench 32 and wider trench 34 by equivalent amounts.
  • the invention can exploit the advantages of conformal deposition in two ways as illustrated in Figures 2a and 2b.
  • the isotropic etch of Figure 2a etches a given thickness away in all directions. In this case, the wider trench 31 is completely stripped of material 33 and the narrower trench 32 is still partially filled with the material 33.
  • the anisotropic etch of Figure 2b the anisotropic etch only etches vertically. In this case, the bottom of the wider trench 31 is stripped of material but is not fully etched away from the side walls of the wider trench 31.
  • the wider trench 31 may be etched away to give a deeper trench than the trench 32, which is effectively masked by the material 34 which remains.
  • the isotropic or anisotropic etch ( Figure 2a and Figure 2b) may be followed by another conformal or non-conformal deposition step.
  • the processing begins with a substrate which will be typically silicon or some other material.
  • silicon is a suitable substrate although the technique is not limited to silicon.
  • the substrate may be a bonded wafer in some applications.
  • the bulk of the substrate will usually be heavily doped - N or P-type depending on whether the device to be manufactured is a power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or an Insulated Gate Bipolar Transistor (IGBT) .
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • IGBT Insulated Gate Bipolar Transistor
  • On top of this substrate will be two layers of epitaxially grown silicon of the opposite polarity. (In some cases these layers might be diffused and not grown) .
  • the next stage is to define a masking pattern.
  • this will be a thin silicon nitride or oxide layer that will have been etched according to a pattern printed by the first and only mask into a photoresist layer. This will characterise the device into two areas - the gate contact area (wide open areas) and the active area
  • the next stage will be to etch trenches into the silicon substrate. This will usually be done using a plasma etcher but can be performed using a wet etch technique.
  • Figure 3a is a plan view of a silicon substrate which is being processed according to the present invention to produce a power MOSFET.
  • the device can be separated into two distinct areas - the gate contact area 50 and the active area 5 (which are conceptually divided by a dotted line 6) .
  • Figure 3b is an enlarged view of a portion 51 of the substrate 1. As can be seen in Figure 3b, the substrate 1 has been masked and etched to leave a gate contact trench 4 to which a bond contact will eventually be attached.
  • Figure 3c is a cross-section along the line A in Figure 3b.
  • the active area 5 has a very large area of narrow trenches 7,8 which are interspersed with a hexagonal array of masked areas 52,53 etc.
  • Figures 3c to 15 are schematic cross-sections along line A in Figure 3b.
  • the upper p-type layer 2 and lower n- type layer 3 are grown or diffused on a silicon substrate (not shown) .
  • the active area 5 is distinguished by being a very large area of narrow trenches usually in the form of a hexagonal or square cellular array (although a stripe geometry can also be used) .
  • a small part of the active area containing only two active trenches 7,8 is shown in Figures 3c-15. These Figures are not to scale - the gate contact trench 4 is typically greater than 60 ⁇ m wide and the active trenches 7,8 are typically between 0.5 and 2 ⁇ m wide.
  • the technique described here allows very high cell density structures to be manufactured which gives better device performance.
  • the trenches are formed using a mask 9. The essence of a one mask process is however to reduce the processing cost and to increase yield through the use of robust "self-aligned techniques".
  • Fig. 4 we perform our first conformal process (Fig. 4) .
  • the substrate is conformally deposited with a material 10 which allows the selective removal of both silicon and silicon dioxide.
  • the material 10 are polymer based materials such as photoresist, and silicon nitride.
  • Fig. 4 When partially etched back isotropically by the thickness of the layer 10, this will expose the sides 11,12 and bottom 13 of the gate contact trench 4 whilst protecting the narrow active trenches 7,8. This is because the active trenches 7,8 are narrow enough to be filled with the material 10.
  • the next stage involves a conformal deposition of the gate electrode material 16 (Fig. 6) which typically will be doped polysilicon (although any conductive material could be used) . This is then anisotropically etched back to just below the silicon surface 17 (Fig. 7) . This means that the polysilicon 16 is removed by etching away vertically downwards and not sideways at all. This can be done using a plasma etcher. This will leave the polysilicon in the form shown.
  • Figure 8 shows the layer of non-conformally deposited silicide 18 deposited on the mask 9 and polysilicon 16.
  • n+ region 55 we now need to planarize the trenches in the active area so that the gate and source are not short circuited. Again this can be done with a conformal deposition of a dielectric material 20 (i.e. an insulator such as silicon dioxide) - Fig. 10. This can be isotropically (i.e. the same in all directions) etched back to complete the planarization and remove all of the glass in the gate contact trench 4. This results in the structure shown in Figure 11 where the active trenches 7,8 are covered in the dielectric 20 whilst the gate contact trench 4 is exposed.
  • a dielectric material 20 i.e. an insulator such as silicon dioxide
  • the original masking material 9 e.g. silicon nitride
  • contact material such as aluminium.
  • the back side of the wafer has a metal drain contact 25 deposited over the entire area of the silicon substrate 60.
  • the upper side (where all the processing has been done) has contact material 21 evaporated on so that the deposition is not conformal (see Figure 12) . This results in a physical break or discontinuity in the deposited film at the edge of the gate contact trench as indicated at 22.
  • the contact material 21 in the active area 5 constitutes a source contact
  • the contact material 21 in the gate contact trench 4 constitutes a gate contact.
  • Fig. 14 is an alternative to Figure 12 which shows how the optional two stage etch shown in Figures 4 and 5 is advantageous. If the gate contact trench is very deep, then we can deposit a larger amount of contact material 21 before reaching the surface level of the silicon, thus maintaining the break 22.
  • the thick oxide layer 15 also protects the gate contact. If the break 22 is not maintained it is likely that the material 21 in the active area and the gate contact area will meet and short circuit. For very high power devices, thick contacts will be necessary and the gate contact area will need to be correspondingly deep.
  • An alternative is to make the trench depths deep across the entire wafer. This has the disadvantage of compromising the breakdown voltage (if a two-thickness oxide process is not used) whilst also making the trench fill processes more difficult. This would however, be a good alternative in low voltage devices (-30V) .
  • the techniques described use a combination of processes which differ in their ability to fill or conformally cover trenches of varying widths. This means that a material is deposited in a fashion that the device is covered in a layer which attempts to maintain a constant thickness across the topology.
  • Such a technique (usually a chemical vapour deposition (CVD) , spin on material in a solvent or a flowed glass) will tend to fill gaps with a dimension less than twice the thickness of the film, but will cover with constant thickness, surfaces of areas wider than this.
  • CVD chemical vapour deposition
  • the resulting device structure is fully self aligned and exhibits potentially excellent performance.

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

L'invention porte sur un procédé de fabrication de dispositifs à semi-conducteur consistant à: (i) tracer dans un substrat au moins deux tranchées (4, 7, 8) dont l'une est plus large que l'autre; (ii) déposer une couche d'un matériau (10, 16, 20) sur le substrat, tranchées comprises, par un procédé de dépôt conforme; et (iii) décaper une partie de la couche de matériau. La largeur des tranchées et l'épaisseur de la couche de matériau sont choisies telles que le matériau soit décapé en partant du fond de la tranchée la plus large (4) et non en partant du fond de la tranchée la plus étroite (7, 8).
PCT/GB1997/000615 1996-03-06 1997-03-05 Procede de formation d'un dispositif a semi-conducteur presentant des tranchees WO1997033309A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB9604764.2A GB9604764D0 (en) 1996-03-06 1996-03-06 Semiconductor device fabrication
GB9604764.2 1996-03-06

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WO1997033309A1 true WO1997033309A1 (fr) 1997-09-12

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PCT/GB1997/000615 WO1997033309A1 (fr) 1996-03-06 1997-03-05 Procede de formation d'un dispositif a semi-conducteur presentant des tranchees

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WO2000042665A1 (fr) * 1999-01-11 2000-07-20 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Composant de puissance mos et procede de fabrication dudit composant
EP1085577A2 (fr) * 1999-09-13 2001-03-21 Shindengen Electric Manufacturing Company, Limited Transistor à effet de champ, de puissance, à grille en tranchée, et sa méthode de fabrication
WO2004102673A2 (fr) * 2003-05-15 2004-11-25 Analog Power Limited Dispositifs dmos a tranchees et leurs methodes et procedes de fabrication
EP1187193A3 (fr) * 2000-09-07 2005-01-05 SANYO ELECTRIC Co., Ltd. Dispositif de circuit intégré semi-conducteur et son procédé de fabrication
CN106449751A (zh) * 2015-08-04 2017-02-22 株式会社东芝 半导体装置及其制造方法

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Cited By (10)

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Publication number Priority date Publication date Assignee Title
WO2000042665A1 (fr) * 1999-01-11 2000-07-20 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Composant de puissance mos et procede de fabrication dudit composant
US6462376B1 (en) 1999-01-11 2002-10-08 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Power MOS element and method for producing the same
EP1085577A2 (fr) * 1999-09-13 2001-03-21 Shindengen Electric Manufacturing Company, Limited Transistor à effet de champ, de puissance, à grille en tranchée, et sa méthode de fabrication
EP1085577A3 (fr) * 1999-09-13 2001-11-21 Shindengen Electric Manufacturing Company, Limited Transistor à effet de champ, de puissance, à grille en tranchée, et sa méthode de fabrication
US6737704B1 (en) 1999-09-13 2004-05-18 Shindengen Electric Manufacturing Co., Ltd. Transistor and method of manufacturing the same
US6872611B2 (en) 1999-09-13 2005-03-29 Shindengen Electric Manufacturing Co., Ltd. Method of manufacturing transistor
EP1187193A3 (fr) * 2000-09-07 2005-01-05 SANYO ELECTRIC Co., Ltd. Dispositif de circuit intégré semi-conducteur et son procédé de fabrication
WO2004102673A2 (fr) * 2003-05-15 2004-11-25 Analog Power Limited Dispositifs dmos a tranchees et leurs methodes et procedes de fabrication
WO2004102673A3 (fr) * 2003-05-15 2005-01-20 Analog Power Ltd Dispositifs dmos a tranchees et leurs methodes et procedes de fabrication
CN106449751A (zh) * 2015-08-04 2017-02-22 株式会社东芝 半导体装置及其制造方法

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