WO1997026605A1 - Module de memoire a processeur integre - Google Patents

Module de memoire a processeur integre Download PDF

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Publication number
WO1997026605A1
WO1997026605A1 PCT/US1997/000839 US9700839W WO9726605A1 WO 1997026605 A1 WO1997026605 A1 WO 1997026605A1 US 9700839 W US9700839 W US 9700839W WO 9726605 A1 WO9726605 A1 WO 9726605A1
Authority
WO
WIPO (PCT)
Prior art keywords
processor
memory
substrate
circuit board
printed circuit
Prior art date
Application number
PCT/US1997/000839
Other languages
English (en)
Inventor
David P. Chengson
William L. Schmidt
Unmesh Auagarwala
Alan D. Foster
Edward C. Priest
John D. Manton
Ali Mira
Original Assignee
Silicon Graphics, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Graphics, Inc. filed Critical Silicon Graphics, Inc.
Publication of WO1997026605A1 publication Critical patent/WO1997026605A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/14—Mounting supporting structure in casing or on frame or rack
    • H05K7/1422—Printed circuit boards receptacles, e.g. stacked structures, electronic circuit modules or box like frames
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7864—Architectures of general purpose stored program computers comprising a single central processing unit with memory on more than one IC chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • the present invention pertains to computer memory and processors. Specifically, the present invention relates to a soc etable computer memory and processor module.
  • SIMM single in-line memory module
  • a SIMM is typically comprised of a printed circuit board with at least one memory component such as a RAM, SRAM, DRAM, and the like attached thereto.
  • the SIMM also commonly includes a multi-pin/pad single in-line connector for connecting the SIMM to the device being upgraded.
  • a detailed description of such a SIMM is found in commonly owned United States Patent No. 5,272,664 to Alexander et al., filed April 21, 1993 entitled "High Memory Capacity DRAM SIMM.” United States Patent No. 5,272,664 is incorporated herein by reference.
  • Prior Art Figure l is a side cut away view of a pair of SIMMs 10 and 12 conventionally mounted to a mother board 14.
  • SIMMs 10 and 12 include a memory component 16 and 18, respectively.
  • Memory components 16 and 18 are attached to substrates 20 and 22, respectively.
  • SIMM 10 is attached to mother board 14 via edge connector 24.
  • SIMM 12 is attached to mother board 14 via edge connector 26.
  • a processor 28 with a heat sink 30 coupled thereto is bonded to mother board 14.
  • an extended bus is required for processor 28 to access memory components 16 or 18. That is, in the prior art, signals traveling from processor 28 to SIMM 10, for example, must travel from processor 28 along an address line present in mother board 14. The signals must continue to travel along the address line through mother board 14 and to edge connector 24 up into substrate 20. The signals then travel along a cache bus in substrate 20 of SIMM 10. The cache bus extends from edge connector 24 to memory component 16.
  • heat sink 30 extends beyond the periphery of processor 28.
  • heat sink 30 prevents SIMMs 10 and 12 from being placed directly next to processor 28.
  • memory components 16 and 18 are separated from mother board 14 by at least the height of edge connector 24.
  • the cache buses must extend at least from the memory component and through the vertical length of the edge card connector.
  • the present invention may be described as a processor and memory module comprising: a substrate having first and second opposing surfaces; the substrate having an electrically conductive path formed therein; a first memory component mounted on the first surface of the substrate, the first memory component coupled to the electrically conductive path; a second memory component mounted on the second surface of the substrate, the second memory component coupled to the electrically conductive path; a processor mounted on the first surface of the substrate, the processor coupled to the electrically conductive path, the processor having a plurality of contact pads disposed thereon; and electrical connectors disposed on the second surface of the substrate, the electrical connectors electrically coupleable to respective contact pads of the processor, the electrical connectors removably attachable to a mother board such that the substrate, with the first and second memory components and the processor mounted thereto, is removably attachable to the mother board.
  • PIMM processor-inclusive memory module
  • the processor-inclusive memory module (PIMM) of the present invention includes a printed circuit board having first and second opposing surfaces.
  • the printed circuit board also has an address line formed therein.
  • a first SRAM is mounted on the first surface of the printed circuit board.
  • the first SRAM is coupled to the address line by a short first cache bus.
  • the present PIMM is further comprised of a second SRAM mounted on the second surface of the printed circuit board.
  • the first and second SRAMs are synchronous SRAMs (SSRAMs) .
  • the second SRAM is coupled to the address line by a short second cache bus.
  • the second SRAM is mounted on the second surface of the printed circuit board directly opposite the first SRAM mounted on the first surface of the printed circuit board.
  • a processor is also mounted on the first surface of the printed circuit board, and is coupled to the address line.
  • the processor has a plurality of contact pads disposed thereon.
  • Electrical connectors extend from the second surface of the printed circuit board.
  • the electrical connectors are electrically coupled to respective contact pads of the processor.
  • the electrical connectors are adapted to be removably attached to a mother board. In so doing, the present PIMM is removably attachable to a mother board.
  • the first and second SRAMs access said address line using said first and second cache buses at a speed of up to 200 MHz.
  • the PIMM includes four SRAMs mounted to a first surface of the printed circuit board. Furthermore, an additional four SRAMs are mounted to the other side of the printed circuit board, directly opposite of the first four SRAMs mounted on the first surface of the printed circuit board.
  • the SRAMs are fashioned from a clam-shelled BGA configuration. This allows a pair of vertically aligned SRAMS on either side of the circuit board to share the same via. Since the top and bottom SRAMs can share the same via, the number of required vias is minimized. As a result, this greatly reduces blockages and delays, while enhancing signal integrity.
  • the present embodiment also includes a tag SRAM mounted to the printed circuit board.
  • a heat sink is thermally coupled to the processor.
  • the present invention also includes an embodiment wherein the second SRAM is thermally coupled to the mother board.
  • the PIMM includes probe test points and built-in high frequency probes disposed on the printed circuit board for setting clock taps and for testing the processor and the first and second SRAMs.
  • FIGURE 1 is a side cut away view of a pair of Prior Art SIMMs conventionally mounted to a mother board.
  • FIGURE 2 is a cut-away, partially exploded, perspective view of the top surface of a processor-inclusive memory module (PIMM) in accordance with the present claimed invention.
  • PIMM processor-inclusive memory module
  • FIGURE 3 is a cut-away perspective view of the bottom surface of processor-inclusive memory module (PIMM) in accordance with the present claimed invention.
  • PIMM processor-inclusive memory module
  • FIGURE 4 is a partial cut-away view illustrating address and cache bus lines of the present processor-inclusive memory module (PIMM) in accordance with the present claimed invention.
  • FIGURE 5 is a side sectional view of one embodiment of the present processor-inclusive memory module (PIMM) coupled to a mother board in accordance with the present claimed invention.
  • Figure 6 shows a circuit diagram of the electrical layout of the PIMM.
  • PIMM 40 consists of a substrate 42 having a processor 44 and nine memory components (46, 48a, 48b, 50a, 50b, 52a, 52b, 54a, and 54b) mounted thereon.
  • substrate 42 is a printed circuit board
  • processor 44 is an R10000 (R10K) processor by Silicon Graphics of Mountain View, California.
  • Memory components (46, 48a, 48b, 50a, 50b, 52a, 52b, 54a, and 54b) are synchronous static random access (SSRAM) components which form, for example, either a 1 MB or 4 MB secondary cache for processor 44.
  • SSRAM synchronous static random access
  • memory components 48a, 48b, 50a, 50b, 52a, 52b, 54a, and 54b are 64K x 18 SSRAM's used for secondary cache, while memory component 46 is a 32k x 36 SSRAM which provides cache coherency.
  • SSRAMs 46, 48a, 48b, 50a, 50b, 52a, 52b, 54a, and 54b have the following characteristics:
  • the present invention provides both memory components and a processor on a single socketable substrate.
  • the present PIMM allows a user to independently test the memory components and the processor before the PIMM is incorporated into a larger system.
  • the socketability of the present PIMM further provides convenient replaceability. That is, the present PIMM is easily removable from the larger system to, for example, add additional memory, replace a memory component or processor, upgrade the processor, and the like.
  • specific substrate, processor, and memory components are recited in the present embodiment, the present invention is also well to the use of other types of substrates, processors, and memory components. Referring still to Figure 2, in the present embodiment, substrate 42 is approximately 4.6 inches long and 2.6 inches wide. Processor 44 is centrally mounted on substrate 42.
  • processor 44 is contained in a ceramic package with the contact pads, not shown, disposed on the bottom of processor 44 and arranged in a Land Grid Array (LGA) package of 599 pins.
  • the ceramic package size is 47.5mm x 47.5 mm.
  • the ceramic LGA package is inserted into low inductance spring contact socket 45 attached to substrate 42.
  • Each of the contact pads of processor 44 is electrically coupled to a respective low inductance spring contact, typically shown as 45. Electrical connection between contact pads of processor 44 and respective low inductance spring contacts 45 occurs when processor 44 is compressed into low inductance spring contact socket 47.
  • the low inductance spring contacts 45 provide multiple parallel conductive paths to each of the contact pads of processor 44.
  • low inductance spring contacts 45 are CIN::APSE Button-Only contacts manufactured by Cinch of Elk Grove Village, Illinois. It will be understood by those of ordinary skill in the art that the present invention is also well suited to the use of other types of low inductance electrical connections between processor 44 and substrate 42.
  • Figure 3 a cut-away perspective view of the bottom surface of PIMM 40 is shown. Electrical connectors, typically shown as 56, extend from the bottom surface of another low inductance spring contact 58. Each of electrical connectors 56 is electrically couplable through substrate 42 to a respective low inductance spring contact 45 of Figure 2, and thus to a respective contact pad of processor 44. Electrical connectors 56 are adapted to be removably inserted onto a mother board, not shown.
  • the following list provides sample electrical connector (pin) names and functions for the present PIMM. Pin Name: Function:
  • the present PIMM is removably attachable to a mother board.
  • the present invention passes signals between processor 44 and mother board 42.
  • electrical connectors 56 of low inductance spring contact 58 are CIN: :APSE Plunger-Button contacts manufactured by Cinch of Elk Grove Village, Illinois.
  • the present invention is also well suited to the use of other types of low impedance electrical connectors.
  • the present invention provides a low-impedance PIMM. That is, the present PIMM is a controlled inductance module which eliminates inductance problems associated with the prior art.
  • SSRAMs 48a and 48b, SSRAMs 50a and 50b, SSRAMs 52a and 52b, SSRAMs 54a and 54b are mounted on opposing surfaces of substrate 42 in a "clam shell" fashion. That is, SSRAM 48a, as an example, is mounted on the top surface of substrate 42, while SSRAM 48b is mounted on the bottom surface of substrate 42 directly opposite SSRAM 48a. Likewise, SSRAM 50a, is mounted on the top surface of substrate 42 with SSRAM 50b mounted on the bottom surface of substrate 42 directly opposite SSRAM 50a, and so on.
  • SRAMS 46, 48a, 48b, 50a, 50b, 52a, 52b, 54a, and 54b are mounted to substrate 42 using a Ball Grid Array (BGA) configuration. More specifically, in the present embodiment, SRAMS 46, 48a, 48b, 60a, 50b, 52a, 52b, 54a, and 54b, are mounted to substrate 42 in a 119 pin BGA of dimension 14 mm x 22 mm using a 7 x 17 matrix BGA configuration.
  • BGA Ball Grid Array
  • Power requirements in the present embodiment for SRAMS 46, 48a, 48b, 50a, 50b, 52a, 52b, 54a, and 54b include a VDD of 3.3 volts to 3.6 volts, and a VDDQ of 1.4 volts to 1.6 volts.
  • VDD 3.3 volts to 3.6 volts
  • VDDQ 1.4 volts to 1.6 volts.
  • the clam shell BGA attachment of SRAMS 46, 48a, 48b, 50a, 50b, 52a, 52b, 54a, and 54b to substrate 42 makes it difficult to access the address, data, and clock nets of SRAMS 46, 48a, 48b, 50a, 50b, 52a, 52b, 54a, and 54b.
  • the present PIMM includes probe test points typically shown as 55 which allow a user of the present PIMM to test SRAMS 46, 48a, 48b, 50a, 50b, 52a, 52b, 54a, and 54b, without having to access address, data, and clock nets in a typical manner.
  • very small 950 ohm resistors are coupled on-board to the test points 55.
  • applying a 50 ohm transmission line test cable to the 950 ohm resistive test pads provides 20:1 passive test probes.
  • active test probes can be implemented in place of the passive test probes.
  • These test probes operate at very high frequencies, in the order of several gigahertz (GHz) . The importance of having these high frequency test probes is to provide a mechanism for determining the proper clock delays. Since a single clock is used to clock the data to both the SSRAMs and processor 44, there exist different set-up and hold times which need to be met.
  • a programmable read-only memory contains information relating to a set of mode bits. These mode bits are used to control the selection amongst a range of different clock taps.
  • the clock taps are selected according to the particular configuration of individual computer systems. Because different configurations require different clock frequencies, a variety of clock taps are used to grant the ability of varying the clock delays to the desired frequencies.
  • FIG. 4 a partial cut-away view illustrating address and cache bus lines of the present PIMM is shown.
  • SRAMs 46, 48a, 48b, 50a, 50b, 52a, 52b, 54a, and 54b in a clam shell configuration, the present invention provides several benefits.
  • a portion of an electrically conductive path (address line) 60 extends through substrate 42.
  • Address line portion 60 is electrically coupled to processor 44.
  • Address line portion 60 extends to a location between SSRAMs 48a, 48b, 50a, 50b.
  • address line portion 60 is coupled to a second address line portion 62 which is perpendicular to address line portion 60.
  • address line portions 60 and 62 form a T-shape.
  • address line portion 62 extends to between SSRAMs 48a and 48b.
  • address line portion 62 extends to between SRAMS 50a and 50b.
  • a very short electrically conductive path (cache bus) 64a electrically couples SRAM 48a to address line portion 62.
  • a very short electrically conductive path (cache buses) 64b electrically couples SRAM 48b to address line portion 62.
  • very short electrically conductive paths (cache buses) 66a and 66b electrically couple SRAMs 50a and 50b, respectively to address line portion 62.
  • cache buses similar short cache bus configurations couple SRAMs 52a, 52b, 54a, and 54b to a T-shaped address line.
  • the present PIMM eliminates the extended address lines or cache buses found in the prior art. That is each of SSRAMs 46, 48a, 48b, 50a, 50b, 52a, 52b, 54a, and 54b, is coupled to a centrally located address line by a very short cache bus. Instead having a cache bus which extends from a SSRAM all the way to the processor, the present PIMM reduces the cache bus length to just long enough to couple the SSRAM to the centrally located address line. Furthermore, instead of using numerous circuitous address lines, the present PIMM employs a single centrally located address line to communicate with four SSRAMs.
  • the present PIMM eliminates significant speed limiting transmission line effects associated with the prior art.
  • the present PIMM provides cache lines which can operate up to 200 MHz.
  • all communication between the processor and SRAMs 46, 48a, 48b, 50a, 50b, 52a, 52b, 54a, and 54b takes place on the present PIMM.
  • the present invention simplifies routing of the mother board to which the PIMM is removably coupled. The simplified routing allows a less complex mother board having fewer layers to be used.
  • the simplified routing schemes, and less complex mother board provides substantial cost reductions to end users of the present PIMM. Furthermore, because 200 MHz signals operate on the present PIMM, the present invention eliminates electrical discontinuity problems associated with the prior art. More specifically, the present invention eliminates the need for high speed signals to pass through an electrical connector such as connectors 24 and 26 of Prior Art Figure 1.
  • processor 44 and SSRAMs 46, 48a, 48b, 50a, 50b, 52a, 52b, 54a, and 54b occurs on the present PIMM.
  • the present invention eliminates the need for numerous connections between the present PIMM and a mother board.
  • many of the electrical connectors typically shown as 56, in Figure 3 are used for providing power and ground instead of transferring signals between the mother board and the present PIMM.
  • the increased number of power and ground pins further reduces the inductance of the present PIMM over prior art devices. This is beneficial due to the large transient current present during simultaneous switching.
  • FIG. 5 a side sectional view of one embodiment of the present PIMM coupled to a mother board is shown.
  • processor 44 When processor 44 is operating at 200 MHz, power output is approximately 30 watts. Such power output must be dissipated to prevent processor 44 from burning up.
  • a heat sink 68 is coupled to the top surface of processor 44. Heat sink 68 is thermally coupled to processor 44 by a thermal pad 70.
  • the present invention does not limit the size of the heat sink which can be attached thereto. That is, as shown in Prior Art Figure 1, the size of the heat sink is limited by the presence of SIMMs 10 and 12. In the present PIMM, heat sink size limitations are removed.
  • heat sink 68 extends over the surface of the SSRAMs of the present PIMM.
  • heat sink 68 is also thermally coupled to the top surface of, for example, SRAMS 48a and 50a by thermal pads 72 and 74, respectively.
  • Low inductance spring contact 58 directly contacts a mother board 76. Excess heat present in low inductance spring contact 58 is then transferred and dissipated through mother board 76.
  • SSRAMs 48b and 50b are coupled to mother board 76 by thermal pads 78 and 80, respectively.
  • the present PIMM further includes screws, typically shown as 82 and 84. Screws 82 and 84 compress heat sink 68 towards mother board 76. The compression insure good electrical contact and efficient thermal transfer in the present PIMM. A stiffening plate 86 prevents mother board 76 from warping due to the compression.
  • the present invention is also well suited to having a serial PROM located on substrate 42.
  • the serial PROM contains a unique identification number and vendor information.
  • the present PIMM further includes a system bus, not shown, which communicates with the mother board.
  • the system bus leaving the PIMM can operate at up to 200 MHz.
  • no high speed, i.e. 200 MHz signal transfer is required between processor 44 and mother board 76.
  • almost all signals to and from processor 44 and cache, and also from processor 44 to mother board 76 will be HSTL .
  • the incoming clock signal will be differential LVPECL, and the JTAG will be LVTTL.
  • SSRAMs 46, 48a, 48b, 50a, 50b, 52a, 52b, 54a, and 54b and processor 44 will have boundary scan, however SSRAMs 46, 48a, 48b, 50a, 50b, 52a, 52b, 54a, and 54b are not fully JTAG 1149.1 compliant.
  • all input and output signals to processor 44 are HSTL except for the processor clock which is differential LVPECL.
  • JTAG signals are LVTTL, and, in an embodiment which includes a serial PROM, the PROM line requires a separate protocol.
  • System bus requirements in the present embodiment include a VDD of 3.3 volts to 3.6 volts, and a VDDQ of 1.4 volts to 1.6 volts.
  • the PIMM operates over a voltage range of 3.3V to 3.6V.
  • Voltage required for VDDQ (HSTL) on the processor and SSRAM's is 1.5 volts +/- O.l volts.
  • the voltage required for line terminations is 1.5V +/- O.l volts.
  • V ref for the input receivers is 0.75 volts and is generated on the present PIMM with a resistor/capacitor network.
  • Figure 6 shows a circuit diagram of the electrical layout of the PIMM.
  • the microprocessor is coupled to a secondary cache, which in the currently preferred embodiment, is comprised of ten 64KX18 SSRAMs 602-611.
  • SSRAMs 604-607 reside on the same side of the printed circuit board. Whereas, SSRAMs 602-603 and 608-609 reside on the opposite site of the printed circuit board with respect to SSRAMs 604-607.
  • SSRAM 610 is used to store the cache tag information.
  • SSRAM 611 is an optional/empty socket.
  • a number of clock lines CLK are used to clock SSRAMS 602-611 and microprocessor 601.
  • address lines ADDR extend from microprocessor 601 to each of the SSRAMs 602-611.
  • address lines specify unique locations within the SSRAMS 602-611 that are to be accessed (i.e., read/write operations).
  • a number of data lines DATA are used to write the data to or read the data from the SSRAMS 602-611.
  • the microprocessor 601 interfaces with the circuitry residing on the motherboard, not shown, via a host of system signals.
  • the present invention provides a memory module which does not require extended address lines or cache buses, a memory module which is capable of operating at speeds up to 200 MHz, and a memory module which is socketable.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

L'invention porte sur un processeur et un module mémoire comprenant un substrat présentant deux surfaces opposées, une première mémoire montée sur la première surface et une deuxième mémoire montée sur la deuxième surface du substrat, un processeur monté sur la première surface et des connecteurs électriques disposés sur la deuxième surface du substrat et pouvant être raccordés électriquement à des plots du processeur et réversiblement attachables à une carte mère de manière à ce que le substrat ainsi que les deux mémoires et le processeur susmentionnés puissent être réversiblement raccordables à la carte mère.
PCT/US1997/000839 1996-01-22 1997-01-14 Module de memoire a processeur integre WO1997026605A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/589,532 US5710733A (en) 1996-01-22 1996-01-22 Processor-inclusive memory module
US589,532 1996-01-22

Publications (1)

Publication Number Publication Date
WO1997026605A1 true WO1997026605A1 (fr) 1997-07-24

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Families Citing this family (69)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6069793A (en) * 1997-01-24 2000-05-30 Hitachi, Ltd. Circuit module and information processing apparatus
US5867419A (en) * 1997-01-27 1999-02-02 Silicon Graphics, Inc. Processor-inclusive memory module
US5922059A (en) * 1997-03-14 1999-07-13 Css Labs, Inc. Circuit board connector
US7133726B1 (en) * 1997-03-28 2006-11-07 Applera Corporation Thermal cycler for PCR
US6867964B1 (en) * 1997-11-19 2005-03-15 Intel Corporation Horizontal mount for a processor
JPH11214638A (ja) 1998-01-29 1999-08-06 Mitsubishi Electric Corp 半導体記憶装置
US5978223A (en) * 1998-02-09 1999-11-02 International Business Machines Corporation Dual heat sink assembly for cooling multiple electronic modules
JPH11340421A (ja) * 1998-05-25 1999-12-10 Fujitsu Ltd メモリ及びロジック混載のｌｓｉデバイス
US6185635B1 (en) * 1998-05-30 2001-02-06 Alcatel Networks Corporation Method and circuit for transporting data based on the content of ingress data words and egress data words
TW444158B (en) * 1998-07-08 2001-07-01 Hon Hai Prec Ind Co Ltd Heat sink device and its manufacture method
JP3104686B2 (ja) * 1998-08-25 2000-10-30 日本電気株式会社 集積回路装置
US6467018B1 (en) 1999-01-04 2002-10-15 International Business Machines Corporation Method and apparatus for addressing individual banks of DRAMs on a memory card
US6163474A (en) * 1999-01-05 2000-12-19 Intel Corporation Memory card which is thermally controlled
US6181004B1 (en) 1999-01-22 2001-01-30 Jerry D. Koontz Digital signal processing assembly and test method
US6262890B1 (en) * 1999-03-18 2001-07-17 International Business Machines Corporation Computer system utilizing front and backside mounted memory controller chipsets
US6373715B1 (en) * 1999-12-17 2002-04-16 Intel Corporation Orienting multiple processors on two sides of a printed circuit board
US6785780B1 (en) 2000-08-31 2004-08-31 Micron Technology, Inc. Distributed processor memory module and method
US6707671B2 (en) * 2001-05-31 2004-03-16 Matsushita Electric Industrial Co., Ltd. Power module and method of manufacturing the same
US7215022B2 (en) * 2001-06-21 2007-05-08 Ati Technologies Inc. Multi-die module
US6721195B2 (en) * 2001-07-12 2004-04-13 Micron Technology, Inc. Reversed memory module socket and motherboard incorporating same
DE10139085A1 (de) * 2001-08-16 2003-05-22 Infineon Technologies Ag Leiterplattensystem, Verfahren zum Betreiben eines Leiterplattensystems, Leiterplatteneinrichtung und deren Verwendung, und Halbleitervorrichtung und deren Verwendung
US20030106708A1 (en) * 2001-12-12 2003-06-12 Hao-Yun Ma Heat sink securing means with back plate
US7133972B2 (en) * 2002-06-07 2006-11-07 Micron Technology, Inc. Memory hub with internal cache and/or memory access prediction
US8837161B2 (en) * 2002-07-16 2014-09-16 Nvidia Corporation Multi-configuration processor-memory substrate device
US7200024B2 (en) * 2002-08-02 2007-04-03 Micron Technology, Inc. System and method for optically interconnecting memory devices
US7117316B2 (en) * 2002-08-05 2006-10-03 Micron Technology, Inc. Memory hub and access method having internal row caching
US7149874B2 (en) * 2002-08-16 2006-12-12 Micron Technology, Inc. Memory hub bypass circuit and method
US7836252B2 (en) * 2002-08-29 2010-11-16 Micron Technology, Inc. System and method for optimizing interconnections of memory devices in a multichip module
US7102907B2 (en) * 2002-09-09 2006-09-05 Micron Technology, Inc. Wavelength division multiplexed memory module, memory system and method
US7271581B2 (en) * 2003-04-02 2007-09-18 Micron Technology, Inc. Integrated circuit characterization printed circuit board, test equipment including same, method of fabrication thereof and method of characterizing an integrated circuit device
US7245145B2 (en) * 2003-06-11 2007-07-17 Micron Technology, Inc. Memory module and method having improved signal routing topology
US7120727B2 (en) * 2003-06-19 2006-10-10 Micron Technology, Inc. Reconfigurable memory module and method
US7260685B2 (en) * 2003-06-20 2007-08-21 Micron Technology, Inc. Memory hub and access method having internal prefetch buffers
US7107415B2 (en) * 2003-06-20 2006-09-12 Micron Technology, Inc. Posted write buffers and methods of posting write requests in memory modules
US7428644B2 (en) * 2003-06-20 2008-09-23 Micron Technology, Inc. System and method for selective memory module power management
US7007125B2 (en) * 2003-06-24 2006-02-28 International Business Machines Corporation Pass through circuit for reduced memory latency in a multiprocessor system
US7389364B2 (en) * 2003-07-22 2008-06-17 Micron Technology, Inc. Apparatus and method for direct memory access in a hub-based memory system
US7133727B2 (en) * 2003-08-01 2006-11-07 Invensys Systems, Inc. System and method for continuous online safety and reliability monitoring
US7117119B2 (en) * 2003-08-01 2006-10-03 Invensys Systems, Inc System and method for continuous online safety and reliability monitoring
US20050050237A1 (en) * 2003-08-28 2005-03-03 Jeddeloh Joseph M. Memory module and method having on-board data search capabilities and processor-based system using such memory modules
US7136958B2 (en) 2003-08-28 2006-11-14 Micron Technology, Inc. Multiple processor system and method including multiple memory hub modules
US7194593B2 (en) * 2003-09-18 2007-03-20 Micron Technology, Inc. Memory hub with integrated non-volatile memory
US7120743B2 (en) 2003-10-20 2006-10-10 Micron Technology, Inc. Arbitration system and method for memory responses in a hub-based memory system
US7234070B2 (en) * 2003-10-27 2007-06-19 Micron Technology, Inc. System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding
JP2005251784A (ja) * 2004-03-01 2005-09-15 Renesas Technology Corp 半導体モジュールおよびその製造方法
US7213082B2 (en) 2004-03-29 2007-05-01 Micron Technology, Inc. Memory hub and method for providing memory sequencing hints
US6980042B2 (en) * 2004-04-05 2005-12-27 Micron Technology, Inc. Delay line synchronizer apparatus and method
US20050227417A1 (en) * 2004-04-06 2005-10-13 Honeywell International Inc. Packaging assembly utilizing flip chip and conductive plastic traces
US7310748B2 (en) 2004-06-04 2007-12-18 Micron Technology, Inc. Memory hub tester interface and method for use thereof
US7212408B2 (en) * 2004-12-28 2007-05-01 Intel Corporation Multi-slot socket for mounting integrated circuits on circuit board
US7761624B2 (en) * 2006-09-28 2010-07-20 Virident Systems, Inc. Systems and apparatus for main memory with non-volatile type memory modules, and related technologies
US20080082750A1 (en) * 2006-09-28 2008-04-03 Okin Kenneth A Methods of communicating to, memory modules in a memory channel
US8074022B2 (en) * 2006-09-28 2011-12-06 Virident Systems, Inc. Programmable heterogeneous memory controllers for main memory with different memory modules
US7761623B2 (en) * 2006-09-28 2010-07-20 Virident Systems, Inc. Main memory in a system with a memory controller configured to control access to non-volatile memory, and related technologies
US7761626B2 (en) * 2006-09-28 2010-07-20 Virident Systems, Inc. Methods for main memory in a system with a memory controller configured to control access to non-volatile memory, and related technologies
US9984012B2 (en) 2006-09-28 2018-05-29 Virident Systems, Llc Read writeable randomly accessible non-volatile memory modules
US8949555B1 (en) 2007-08-30 2015-02-03 Virident Systems, Inc. Methods for sustained read and write performance with non-volatile memory
US7761625B2 (en) * 2006-09-28 2010-07-20 Virident Systems, Inc. Methods for main memory with non-volatile type memory modules, and related technologies
WO2008040028A2 (fr) * 2006-09-28 2008-04-03 Virident Systems, Inc. Systèmes, procédés et appareil avec une commande de mémoire programmable pour une mémoire principale hétérogène
WO2008051940A2 (fr) * 2006-10-23 2008-05-02 Virident Systems, Inc. Procédés et dispositif destinés à des modules de mémoire à double rangée de connexions pour mémoire flash
US9921896B2 (en) 2007-08-30 2018-03-20 Virident Systems, Llc Shutdowns and data recovery to avoid read errors weak pages in a non-volatile memory system
US9251899B2 (en) * 2008-02-12 2016-02-02 Virident Systems, Inc. Methods for upgrading main memory in computer systems to two-dimensional memory modules and master memory controllers
US8856464B2 (en) * 2008-02-12 2014-10-07 Virident Systems, Inc. Systems for two-dimensional main memory including memory modules with read-writeable non-volatile memory devices
US8417873B1 (en) 2008-06-24 2013-04-09 Virident Systems, Inc. Random read and read/write block accessible memory
US9513695B2 (en) 2008-06-24 2016-12-06 Virident Systems, Inc. Methods of managing power in network computer systems
CN101819455A (zh) * 2009-02-27 2010-09-01 鸿富锦精密工业（深圳）有限公司 主板散热器
CN101853058A (zh) * 2009-03-30 2010-10-06 鸿富锦精密工业（深圳）有限公司 主板散热器
JP5431793B2 (ja) * 2009-05-29 2014-03-05 新光電気工業株式会社 放熱部品、電子部品装置及び電子部品装置の製造方法
CN103809708A (zh) 2012-11-07 2014-05-21 辉达公司 平板电子设备及其辅助散热装置、以及两者的组件

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0392892A1 (fr) * 1989-03-31 1990-10-17 General Electric Cgr S.A. Module mémoire compact pour carte de mémoire de données d'un processeur d'images
DE9015468U1 (de) * 1990-11-12 1991-01-31 Block, Karl-Heinz, 26169 Friesoythe Elektronischer Schaltungsaufbau als Zusatz für eine elektronische Schaltung
EP0446367A1 (fr) * 1989-10-04 1991-09-18 Fanuc Ltd. Dispositif de commande
EP0504411A1 (fr) * 1990-09-19 1992-09-23 Fujitsu Limited Dispositif a semi-conducteur comportant de nombreuses broches a fils conducteurs
US5315482A (en) * 1991-10-21 1994-05-24 Hitachi, Ltd. Semiconductor apparatus of module installing type
EP0660399A2 (fr) * 1993-12-20 1995-06-28 STMicroelectronics, Inc. Boîtier à réseau de billes pour circuits intégrés avec conductivité thermique

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU628547B2 (en) * 1989-05-19 1992-09-17 Compaq Computer Corporation Modular computer memory circuit board
US5317344A (en) * 1989-12-22 1994-05-31 Eastman Kodak Company Light emitting diode printhead having improved signal distribution apparatus
US5287247A (en) * 1990-09-21 1994-02-15 Lsi Logic Corporation Computer system module assembly
US5260892A (en) * 1991-11-21 1993-11-09 Sun Microsystems, Inc. High speed electrical signal interconnect structure
US5266912A (en) * 1992-08-19 1993-11-30 Micron Technology, Inc. Inherently impedance matched multiple integrated circuit module
US5535342A (en) * 1992-11-05 1996-07-09 Giga Operations Corporation Pld connector for module having configuration of either first PLD or second PLD and reconfigurable bus for communication of two different bus protocols
JP3319624B2 (ja) * 1993-02-24 2002-09-03 株式会社日立製作所 情報機器用モジュールおよびこれに用いられるコネクタ
US5272664A (en) * 1993-04-21 1993-12-21 Silicon Graphics, Inc. High memory capacity DRAM SIMM
US5412538A (en) * 1993-07-19 1995-05-02 Cordata, Inc. Space-saving memory module
JPH07111379A (ja) * 1993-10-12 1995-04-25 Toppan Printing Co Ltd マルチチップモジュール実装型プリント配線板
JP2944405B2 (ja) * 1993-12-29 1999-09-06 日本電気株式会社 半導体素子の冷却構造および電磁遮蔽構造
US5446960A (en) * 1994-02-15 1995-09-05 International Business Machines Corporation Alignment apparatus and method for placing modules on a circuit board
CA2147018A1 (fr) * 1994-04-29 1995-10-30 Lit-Yan Kam Puits de chaleur metallique mecano-soude
US5400220A (en) * 1994-05-18 1995-03-21 Dell Usa, L.P. Mechanical printed circuit board and ball grid array interconnect apparatus
US5574627A (en) * 1995-07-24 1996-11-12 At&T Global Information Solutions Company Apparatus for preventing the formation of condensation on sub-cooled integrated circuit devices

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0392892A1 (fr) * 1989-03-31 1990-10-17 General Electric Cgr S.A. Module mémoire compact pour carte de mémoire de données d'un processeur d'images
EP0446367A1 (fr) * 1989-10-04 1991-09-18 Fanuc Ltd. Dispositif de commande
EP0504411A1 (fr) * 1990-09-19 1992-09-23 Fujitsu Limited Dispositif a semi-conducteur comportant de nombreuses broches a fils conducteurs
DE9015468U1 (de) * 1990-11-12 1991-01-31 Block, Karl-Heinz, 26169 Friesoythe Elektronischer Schaltungsaufbau als Zusatz für eine elektronische Schaltung
US5315482A (en) * 1991-10-21 1994-05-24 Hitachi, Ltd. Semiconductor apparatus of module installing type
EP0660399A2 (fr) * 1993-12-20 1995-06-28 STMicroelectronics, Inc. Boîtier à réseau de billes pour circuits intégrés avec conductivité thermique

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"NOVEL MEMORY CARD", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 37, no. 10, 1 October 1994 (1994-10-01), pages 505 - 508, XP000475756 *
PAQUIN K: "THERMALLY ACTIVATED ATTACHMENT MECHANISM", MOTOROLA TECHNICAL DEVELOPMENTS, vol. 18, 1 March 1993 (1993-03-01), pages 173 - 175, XP000349616 *

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