WO1997020393A1 - Procede de generation d'un signal de sortie en reponse a un signal externe et a un premier signal de reference ainsi que circuit numerique a verrouillage de phase dote d'un oscillateur commande en tension - Google Patents

Procede de generation d'un signal de sortie en reponse a un signal externe et a un premier signal de reference ainsi que circuit numerique a verrouillage de phase dote d'un oscillateur commande en tension Download PDF

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Publication number
WO1997020393A1
WO1997020393A1 PCT/DK1996/000481 DK9600481W WO9720393A1 WO 1997020393 A1 WO1997020393 A1 WO 1997020393A1 DK 9600481 W DK9600481 W DK 9600481W WO 9720393 A1 WO9720393 A1 WO 9720393A1
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WO
WIPO (PCT)
Prior art keywords
signal
counter
circuit
external
voltage
Prior art date
Application number
PCT/DK1996/000481
Other languages
English (en)
Inventor
Anders Bøje NIELSEN
Original Assignee
Dsc Communications A/S
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dsc Communications A/S filed Critical Dsc Communications A/S
Priority to AU10655/97A priority Critical patent/AU1065597A/en
Publication of WO1997020393A1 publication Critical patent/WO1997020393A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H03L7/143—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by switching the reference signal of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/181—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Definitions

  • the invention concerns a method of generating an output signal in response to an external signal and a first ref ⁇ erence signal, wherein an internal signal is currently generated to replace the external signal if the external signal drops out.
  • the output signal may e.g. originate from a circuit whose output voltage is to match a constant input voltage.
  • the voltage is usually fed back from the output of the cir ⁇ cuit to a comparator circuit which compares the input signal and the signal fed back. In the event that the voltage of the output signal changes, the output signal from the comparator circuit will ensure that the output signal is adjusted.
  • SE C2 501 385 discloses a circuit intended for coupling an internal reference frequency m a phase-locked circuit if the reference frequency used drops out.
  • the document describes a method wherein the reference frequency used is currently stored, and if it drops out, the stored value is coupled to control a voltage-controlled oscilla- tor. This known method is not sufficiently accurate in all cases, since the coupling of the internal reference frequency will cause phase errors m the phase-locked circuit.
  • an ob ect of the invention is to provide a method of the type mentioned m the opening paragraph, wherein an output signal to be maintained in relation to an input signal, can be generated with very great accuracy if the input signal drops out.
  • This object is achieved according to the invention m that the difference between the internal signal and the external signal is currently monitored to calculate an adjustment signal, and that, if the external signal drops out, the output signal is generated by means of the feed- back loop in response to the internal signal and the sig ⁇ nal fed back, adjusted by the calculated adjustment sig ⁇ nal .
  • the absent input signal may hereby be replaced by a new input signal, a reference signal generated on the basis of the original input signal being used for adapting the circuit conditions in accordance with what they were prior to the drop-out of the input signal.
  • This general principle may advantageously be used in con ⁇ nection with so-called SDH communications equipment, m which a so-called STM-1 frame may be transferred between network elements.
  • the frame consists of 270 columns with 9 bytes in each column.
  • the first 9 columns m a frame contain overhead functions, frame loci, etc.
  • a frame is transferred from one network element to another with a period of 125 ⁇ sec. This means that all bits in the frame, which are transmitted serially, e.g. through an optical fibre, must have been transmitted after 125 ⁇ sec., which means m turn that the bits must be trans- ferred with 155.520 megabits/sec, since a total of 19,940 must be transferred m 125 ⁇ sec.
  • phase-locked loop may be used for this pur- pose, adapted so that an output signal maintains a con ⁇ stant value m relation to an input signal.
  • a phase-locked loop may be arranged to emit an output sig- nal which has a frequency corresponding to the transfer of 155,520 megabits per second.
  • the input signal drops out for some reason, it is desirable that another signal which is very close to the signal dropped out can be connected very rapidly, so that the output frequency may be kept at a stable value.
  • this wish is fulfilled by a method in connection with a digital voltage-controlled oscillator which is characterized in that the output sig- nal from the voltage-controlled oscillator is counted in a counter circuit which is latched by the external sig ⁇ nal, said latched value being then used for controlling the voltage-controlled oscillator, that the external sig ⁇ nal and the internal signal are currently monitored to calculate an adjustment value, and that, in case of drop ⁇ out of the external signal, the output signal from the voltage-controlled oscillator is adjusted by the adjust ⁇ ment value and the counter circuit is latched instead by the internal signal, said latched value being then used for controlling the voltage-controlled oscillator.
  • the out ⁇ put signal of the voltage-controlled oscillator while being locked to the external frequency, is supplied to an 11-bit counter whose contents are latched with a period determined by the internal frequency, and that the re ⁇ sulting value is used in the calculation of the adjust ⁇ ment value.
  • another advantage is that, in case of drop-out of the external frequency, the adjust ⁇ ment value last calculated is supplied to a third counter which counts with a frequency derived from the output frequency of the voltage-controlled oscillator, and, each time the third counter has counted to a value calculated on the basis of the adjustment value, a clock pulse will be removed from or added to the output signal of the voltage-controlled oscillator before said signal is sup ⁇ plied to the counter circuit, as the internal frequency will have resulted in one clock period too many or too few in relation to what it would if the external fre ⁇ quency was still present.
  • phase dif ⁇ ference would mean that the regulation circuit would re ⁇ ceive a transient that might disturb the stable regula- tion. Therefore, it is important that this, too, may be taken into account.
  • the invention also concerns a digital phase-locked cir ⁇ cuit having a voltage-controlled oscillator whose output signal is locked to an external signal, and wherein a counter, whose output is adapted to be latched with a latch signal determined by the external signal, is adapted to count the output signal from the voltage-con ⁇ trolled oscillator, which is adapted to be controlled by the latched value, and moreover comprising an adjustment circuit.
  • This circuit is characterized in that the adjustment cir ⁇ cuit is adapted to calculate an adjustment value in re ⁇ sponse to the external signal and an internal signal and, m case of drop-out of the external signal, to adjust the output signal of the oscillator by the adjustment value before said signal is supplied to the counter input of the counter circuit so as to compensate for the differ ⁇ ence between the external signal and the internal signal.
  • a digital phase-locked circuit enabling insertion of an internal signal, if the external signal drops out, while supplying to the phase detector a compensation signal which ensures that the phase lock op- erates substantially without changes relative to what it did before the external signal dropped out.
  • the adjustment circuit comprises an 11-bit counter whose output is connected to the input on a cal- culating circuit.
  • fig. 1 shows a basic structure of a circuit according to the principles of the invention
  • fig. 2 shows an example of an embodiment of a digital phase-locked circuit of the invention.
  • Fig. 1 basically shows a circuit which may be used in a regulation circuit from a process where an output signal having a predetermined relation to an external input signal is to be generated. This situation is shown in fig. 1, where switches 1 and 2 controlled by a detector circuit 3 are in the position shown in the figure.
  • the external input signal and a first feedback signal are connected to a comparator circuit 4 adapted to generate an output signal, which controls a signal generator 5 generating the output signal.
  • the first feedback signal is generated by means of the output signal via a circuit 6 having a predetermined transfer function.
  • the matter described above corresponds closely to a well-known regu ⁇ lation loop.
  • the invention relates to the situation where the external input signal drops out for some reason, it being impor ⁇ tant that the output signal continues to be generated es ⁇ sentially as if nothing had happened on the input side.
  • an internal func ⁇ tion generator 7 being provided, emitting an input signal which is very close to the external signal. Since the ex ⁇ ternal input signal constantly varies slightly with time, the internal input signal, of course, usually does not correspond completely to the external signal, and there ⁇ fore it does not suffice to replace the external input signal by an internal input signal merely by switching in the event that the detector circuit 3 detects that the external input signal has disappeared.
  • the circuit 8a calculates an adjustment signal which corresponds to the difference between the internal input signal and the external input signal.
  • This adjustment signal is supplied to an adjust ⁇ ment circuit 9 capable of adjusting the first feedback signal by a value which corresponds precisely to the dif ⁇ ference between the two input signals.
  • the switches 1 and 2 controlled by the detector circuit 3 switch to the position shown m dashed line, so that the internal input signal instead of the external one is now supplied on one input of the comparator circuit, while the other input of the comparator circuit receives a signal which differs just as much from the original feedback signal as the difference between the two input signals.
  • the com ⁇ parator circuit 4 will not see any direct change m its input signals, and nor will the output signal from the signal generator 5 be directly by affected by the disap ⁇ pearance of the external input signal.
  • the numeral 10 designates a digital phase-locked loop
  • 12 represents an adjustment circuit for use in the adjustment of the phase-locked circuit 10. Since the invention does not address the actual digital phase-locked loop, this circuit will ust be explained briefly, but sufficiently to understand how the adjust- ment circuit 12 operates.
  • the phase-locked circuit 10 has a voltage-controlled os ⁇ cillator 17, whose output signal is fed back to a counter 13 which currently counts pulses from the output of the voltage-controlled oscillator 17.
  • the counter 13 is a free-running counter whose value is latched in a latching circuit 23 so as to latch with a period of 125 ⁇ sec., corresponding to 8 kHz in the input signal.
  • the output signal from the latching circuit 23 is fed to a compensa- tion unit 14 which staggers the count in the latch 23 m an expedient manner to provide even regulation values, which are fed to an integrator 15, 18 and from there to a digital-to-analog converter 16 which controls the volt ⁇ age-controlled oscillator 17.
  • the adjustment circuit 12 has an 11-bit counter 26 which counts pulses from the output of the voltage- controlled oscillator, said counter 26 being periodically latched by an internal signal with a period of about 1 second derived from the frequency of the internal signal.
  • the counter circuit 26 can constantly compare the external signal with the internal signal, and any differ ⁇ ence will be reflected by a signal on the output of the counter 26.
  • the difference between the external signal and the internal signal may be determined very ac ⁇ curately m periods of about 1 second. If the 8 kHz sig ⁇ nal drops out, the counter 26 instantaneously stores the value latched last and supplies a signal in response thereto to a third counter 22, which currently counts up or down from this fixed value with a frequency synchro ⁇ nous with the output frequency of the voltage-controlled oscillator 10, e.g. by 1/8 of this frequency.
  • the counter 22 is dimensioned such that when it has counted a plurality of pulses corresponding to the said value, it will apply a signal to a circuit 25 which adds a clock pulse to or subtracts a clock pulse from the os ⁇ cillator 17, which corresponds to compensation for the difference that existed between the external signal and the internal signal at the time when the external signal dropped out.
  • the circuit constantly cor- rects for the difference that existed between the exter ⁇ nal signal and the internal signal, so that the circuit does not change its output signal.
  • the circuit 12 provides for correction of frequency differences between the external signal and the internal signal .
  • the external signal and the internal signal can ⁇ not have the same phase at the moment when the internal signal is connected. This means that if the internal sig- nal was connected directly, without taking any steps to allow for the phase differences, the circuit would no longer be phase-locked. The reason is that the latching circuit is latched by the pulses which are supplied by the external signal. If, e.g., the external signal sud- denly disappears, and a value exactly corresponding to a pulse m the external signal has been latched, an inter ⁇ nal signal with a temporally different pulse will latch by another value m the latching circuit, which would correspond to the difference between the phases of the internal and external signals.
  • the circuit is adapted such that the first time the circuit is latched by the new signal, the last-latched value from before the disappearance of the external signal is main ⁇ tained, and this value is moreover entered into the counter which will proceed with its count from there. Then, the internal signal latches the counter m the sub ⁇ sequent periods .

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

Un circuit numérique (10) à verrouillage de phase comporte un oscillateur commandé en tension (17) dont le signal de sortie est mesuré dans un compteur (13) qui est verrouillé en fonction de la fréquence d'un signal d'entrée externe. Si la fréquence externe perd de son niveau, une fréquence générée au niveau interne verrouille le circuit de comptage (13) et un signal d'ajustement provenant d'un circuit de compensation (12) ajuste le détecteur de phase. Le circuit de compensation (12) consiste en un compteur à 11 bits (26) qui mesure le signal de sortie provenant d'un oscillateur commandé en tension (17). Le contenu du compteur (26) est renouvelé par périodes déterminées par le signal interne. Si le signal externe perd de son niveau, le compteur (26) est verrouillé instantanément sur la dernière valeur verrouillée et un troisième compteur (22) produit un signal qui peut être envoyé sous forme de signal d'entrée au compteur (13), ledit troisième compteur (22) étant conçu pour appliquer un signal à un circuit lorsque la valeur mesurée dans le troisième compteur (22) correspond à une valeur calculée par le compteur (26).
PCT/DK1996/000481 1995-11-24 1996-11-22 Procede de generation d'un signal de sortie en reponse a un signal externe et a un premier signal de reference ainsi que circuit numerique a verrouillage de phase dote d'un oscillateur commande en tension WO1997020393A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU10655/97A AU1065597A (en) 1995-11-24 1996-11-22 A method of generating an output signal in response to an external signal and a first reference signal, as well as digital phase-locked circuit having a voltage-controlled oscillator

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DK132995A DK132995A (da) 1995-11-24 1995-11-24 Fremgangsmåde til frembringelse af et udgangssignal, i afhængighed af et eksternt signal og et første referencesignal, samt digitalt faselåskredsløb med en spændingsstyret oscillator
DK1329/95 1995-11-24

Publications (1)

Publication Number Publication Date
WO1997020393A1 true WO1997020393A1 (fr) 1997-06-05

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PCT/DK1996/000481 WO1997020393A1 (fr) 1995-11-24 1996-11-22 Procede de generation d'un signal de sortie en reponse a un signal externe et a un premier signal de reference ainsi que circuit numerique a verrouillage de phase dote d'un oscillateur commande en tension

Country Status (3)

Country Link
AU (1) AU1065597A (fr)
DK (1) DK132995A (fr)
WO (1) WO1997020393A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003034647A1 (fr) * 2001-10-12 2003-04-24 Infineon Technologies Ag Dispositif de reconstruction de donnees a partir d'un signal de donnees reçu et dispositif emetteur-recepteur correspondant
EP1892837A1 (fr) * 2006-08-22 2008-02-27 NEC Corporation Circuit d'alimentation d'une horloge et procédé d'alimentation d'une horloge

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0530393A1 (fr) * 1991-09-02 1993-03-10 Siemens Aktiengesellschaft Méthode et dispositif pour la synchronisation d'un générateur d'horloge d'un système de commutation de communication
EP0631407A2 (fr) * 1993-06-07 1994-12-28 Alcatel STR AG Procédé et dispositif de commutation à phase exact d'impulsions homogènes avec relation des phases différentes
EP0650259A1 (fr) * 1993-10-23 1995-04-26 Alcatel SEL Aktiengesellschaft Circuit générateur de signaux d'horloge
EP0652642A1 (fr) * 1993-11-05 1995-05-10 AT&T Corp. Procédé et appareil pour un circuit à boucle de synchronisation de phase comportant un mode de maintien de la fréquence

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0530393A1 (fr) * 1991-09-02 1993-03-10 Siemens Aktiengesellschaft Méthode et dispositif pour la synchronisation d'un générateur d'horloge d'un système de commutation de communication
EP0631407A2 (fr) * 1993-06-07 1994-12-28 Alcatel STR AG Procédé et dispositif de commutation à phase exact d'impulsions homogènes avec relation des phases différentes
EP0650259A1 (fr) * 1993-10-23 1995-04-26 Alcatel SEL Aktiengesellschaft Circuit générateur de signaux d'horloge
EP0652642A1 (fr) * 1993-11-05 1995-05-10 AT&T Corp. Procédé et appareil pour un circuit à boucle de synchronisation de phase comportant un mode de maintien de la fréquence

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003034647A1 (fr) * 2001-10-12 2003-04-24 Infineon Technologies Ag Dispositif de reconstruction de donnees a partir d'un signal de donnees reçu et dispositif emetteur-recepteur correspondant
US7088976B2 (en) 2001-10-12 2006-08-08 Infineon Technologies Ag Device for reconstructing data from a received data signal and corresponding transceiver
DE10150536B4 (de) * 2001-10-12 2010-04-29 Infineon Technologies Ag Vorrichtung zur Rekonstruktion von Daten aus einem empfangenen Datensignal sowie entsprechende Sende- und Empfangsvorrichtung
EP1892837A1 (fr) * 2006-08-22 2008-02-27 NEC Corporation Circuit d'alimentation d'une horloge et procédé d'alimentation d'une horloge
US7856075B2 (en) 2006-08-22 2010-12-21 Nec Corporation Clock supply circuit and clock supply method

Also Published As

Publication number Publication date
AU1065597A (en) 1997-06-19
DK132995A (da) 1997-05-25

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