AU1065597A - A method of generating an output signal in response to an external signal and a first reference signal, as well as digital phase-locked circuit having a voltage-controlled oscillator - Google Patents

A method of generating an output signal in response to an external signal and a first reference signal, as well as digital phase-locked circuit having a voltage-controlled oscillator

Info

Publication number
AU1065597A
AU1065597A AU10655/97A AU1065597A AU1065597A AU 1065597 A AU1065597 A AU 1065597A AU 10655/97 A AU10655/97 A AU 10655/97A AU 1065597 A AU1065597 A AU 1065597A AU 1065597 A AU1065597 A AU 1065597A
Authority
AU
Australia
Prior art keywords
signal
voltage
response
generating
well
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU10655/97A
Inventor
Anders Boeje Nielsen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infinera Denmark AS
Original Assignee
DSC Communications AS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by DSC Communications AS filed Critical DSC Communications AS
Publication of AU1065597A publication Critical patent/AU1065597A/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H03L7/143—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by switching the reference signal of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/181—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock
AU10655/97A 1995-11-24 1996-11-22 A method of generating an output signal in response to an external signal and a first reference signal, as well as digital phase-locked circuit having a voltage-controlled oscillator Abandoned AU1065597A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DK132995A DK132995A (en) 1995-11-24 1995-11-24 Method for generating an output signal, dependent on an external signal and a first reference signal, as well as digital phase lock circuit with a voltage controlled oscillator
DK1329/95 1995-11-24
PCT/DK1996/000481 WO1997020393A1 (en) 1995-11-24 1996-11-22 A method of generating an output signal in response to an external signal and a first reference signal, as well as a digital phase-locked circuit having a voltage-controlled oscillator

Publications (1)

Publication Number Publication Date
AU1065597A true AU1065597A (en) 1997-06-19

Family

ID=8103642

Family Applications (1)

Application Number Title Priority Date Filing Date
AU10655/97A Abandoned AU1065597A (en) 1995-11-24 1996-11-22 A method of generating an output signal in response to an external signal and a first reference signal, as well as digital phase-locked circuit having a voltage-controlled oscillator

Country Status (3)

Country Link
AU (1) AU1065597A (en)
DK (1) DK132995A (en)
WO (1) WO1997020393A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10150536B4 (en) * 2001-10-12 2010-04-29 Infineon Technologies Ag Device for reconstructing data from a received data signal and corresponding transmitting and receiving device
JP2008053832A (en) * 2006-08-22 2008-03-06 Nec Corp Clock supply circuit and clock supply method

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0530393B1 (en) * 1991-09-02 1994-12-07 Siemens Aktiengesellschaft Method and apparatus for synchronising a clockcircuit of a switching communication system
AU677832B2 (en) * 1993-06-07 1997-05-08 Alcatel N.V. Hitless switch arrangement
DE4336239A1 (en) * 1993-10-23 1995-04-27 Sel Alcatel Ag Circuit arrangement for a clock generator
CA2130871C (en) * 1993-11-05 1999-09-28 John M. Alder Method and apparatus for a phase-locked loop circuit with holdover mode

Also Published As

Publication number Publication date
DK132995A (en) 1997-05-25
WO1997020393A1 (en) 1997-06-05

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