WO1997012397A1 - Assemblages microelectroniques comprenant des films conducteurs suivant l'axe des z - Google Patents

Assemblages microelectroniques comprenant des films conducteurs suivant l'axe des z Download PDF

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Publication number
WO1997012397A1
WO1997012397A1 PCT/US1996/016023 US9616023W WO9712397A1 WO 1997012397 A1 WO1997012397 A1 WO 1997012397A1 US 9616023 W US9616023 W US 9616023W WO 9712397 A1 WO9712397 A1 WO 9712397A1
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WIPO (PCT)
Prior art keywords
film
metal
pores
filled
membrane
Prior art date
Application number
PCT/US1996/016023
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English (en)
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Texas Instruments Incorporated
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Texas Instruments Incorporated filed Critical Texas Instruments Incorporated
Priority to BR9606658A priority Critical patent/BR9606658A/pt
Priority to AU73932/96A priority patent/AU703591B2/en
Priority to JP9513771A priority patent/JPH10513611A/ja
Priority to EP96936229A priority patent/EP0811245A4/fr
Publication of WO1997012397A1 publication Critical patent/WO1997012397A1/fr
Priority to MXPA/A/1997/003780A priority patent/MXPA97003780A/xx

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H01L23/4922—Bases or plates or solder therefor having a heterogeneous or anisotropic structure
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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    • H05K2201/0104—Properties and characteristics in general
    • H05K2201/0116—Porous, e.g. foam
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    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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    • H05K2201/10378—Interposers
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
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Definitions

  • This invention relates to the assembly and packaging of micro ⁇ electronic devices, including semiconductor circuit chips, printed circuit boards, thin-film networks (TFN's), and multi- chip circuit modules; and more particularly to novel means for interconnecting such devices and modules, electrically and/or thermally.
  • elastomeric polymer films having multiple, metal- filled apertures have been developed for electrical connections, but the metal filling has consisted of either 1) discrete particles (usually spherical) or 2) a single sphere having a diameter slightly greater than the thickness of the polymer film, such that the sphere is barely exposed at both surfaces of the film.
  • the particle-filled films have not been satisfactory, because the particle-to-particle surface contact area within the film is extremely limited, causing excessive electrical and thermal resistance at each contact point; and because the surface contact area between a particle and a bonding pad is also very limited. The sum of all these high-resistance contact points gives the interconnection a poor performance rating.
  • the single sphere approach is also unsatisfactory, because the surface area of the contact point with the sphere, on each side of the film, is too small; and because the film thickness is fixed by the diameter of the spheres, and thus the film cannot readily be deformed to accommodate the need for a non- uniform thickness range.
  • the use of deformable, gold-coated polvmer spheres randomly distributed within a polymeric adhesive has been tried, but each gold-coated sphere had a diameter about the same as the width of a single bonding pad, which gave an unreliable result. Moreover, adjacent spheres could not be kept apart, and there was no potential for substantially reducing the space between bonding pads .
  • An elastomeric connector block comprising a plurality of laminated silicone sheets, with parallel gold traces deposited on the surface of each sheet, has provided electrical connection between circuit boards having terminal pads with a minimum width of 15 mils, which is far too large for connecting pads on an integrated circuit chip.
  • One aspect of the invention is embodied in an assembly of two or more microelectronic parts, wherein electrical and/or thermal interconnection between the parts is achieved by means of multiple, discrete, conductive nanoscopic fibrils or tubules fixed within the pores of an insulating film.
  • the pores are usually perpendicular, or substantially perpendicular to the plane of the film, and extend through the complete thickness of the film.
  • Such a film is said to have anisotropic electrical conductivity, i.e. , Z-axis conductivity, with little or no conductivity in the other directions .
  • the insulating film of the assembly is selected from various materials, including synthetic resin films, also known as polymeric membranes.
  • synthetic resin films also known as polymeric membranes.
  • such films are also capable of providing structural connection between parts, for example, by adhesively bonding the parts together, and thereby permanently fixing the tips of the metal fibrils in contact with the parts.
  • the parts may be held together with a non-bonding Z-axis film in between, by pressure alone, using any suitable clamping mechanism. Such an alternative allows the parts to be readily separated, for the purpose of replacement or repair, etc.
  • a single integrated circuit chip having more than one thousand bonding pads, for example, is now readily packaged, using the interconnection system of the invention.
  • two or more such circuit chips are readily interconnected with each other in accordance with the invention.
  • one or more circuit chips comprising active components may be mounted upon and interconnected with ohmic contacts on a passive substrate.
  • one or more circuit chips may be mounted upon and interconnected with ohmic contact pads on a printed circuit board, or a microstrip line, or TFN, or a package base.
  • TFN microstrip line
  • a suitable Z-axis conductive film useful in accordance with the invention is a synthetic resin membrane having nanometer-sized pores extending through the film, from one membrane surface to the other surface, and having at least some of its pores filled with a conductive material or composition, such as gold or other metals, or with one or more nonmetallic conductive materials.
  • the thickness of the film is within the range of about five microns, up to about 10 mils. The dimensions of the film and the metal fibrils ensure good performance at 50 GHz and higher frequencies.
  • nanoscopic pore diameter in such a membrane is much smaller than the smallest spacing between contact pads on a circuit chip; and therefore no electrical shorting between adjacent contacts can be caused by such metal-filled pores, regardless of chip orientation or alignment.
  • the terms “nanoscopic”, “nanoporous” and “nanometer-sized” include diameters within the range of about 1 nanometer, up to about 10,000 nanometers (10 microns), and preferably from 10 nanometers to 1,000 nanometers (1 micron) .
  • a suitable spacing between pad centers is about 0.5 mil, or about 12.5 microns, which equals 12,500 nanometers.
  • the tip of a metal fibril fixed within a pore having a 10- nanometer diameter covers or contacts only l/1250th of the distance between pad centers.
  • the space between edges of adjacent pads is 0.1 mil, or 2,500 nanometers.
  • Such a metal fibril tip would contact only l/250th of the space between pad edges.
  • a 100-nanometer fibril tip would span only l/25th of the space between pads.
  • a distinguishing feature of the preferred nanoporous films used in accordance with the invention is the aspect ratio of the pores. That is, for a one-mil-thick film, each pore length is one mil, or about 25,000 nanometers; and thus, for a pore diameter of 10 nanometers, the aspect ratio is 2500:1.
  • the range of suitable aspect ratios for use in the invention is from about
  • a further advantage of the invention lies in the fact that precise alignment of the interconnect film with other parts is not required, in order to achieve a desired ohmic interconnection. Acceptable alignment is achieved when some portion of each pad on a chip is aligned with some portion of its counterpart on a substrate or other part to which bonding is desired, provided no overlap with an adjacent pad is allowed.
  • thermal interconnection between parts is achieved in the same manner as described above for electrical interconnection, except that the nanopores are filled with a material having high thermal conductivity.
  • the number and/or size of the pores is increased, so that a high percentage of the membrane volume consists of the filled pores. For example, a membrane consisting of 20% gold by volume has a Z-axis conductivity approaching 60 W/M degree C, whereas a commercial adhesive, designed for heat dissipation, has a thermal conductivity of only 5 W/M degree C.
  • the material in the pores is selected from electrically nonconductive materials having a high thermal conductivity, such as diamond, carbon, or boron nitride, for example.
  • Nanoporous films of the type used in practicing the invention are commercially available for use as nanofiltration membranes. They are made, for example, by exposing a nonporous resin film to accelerated nuclear particles having sufficient energy to pass through the entire thickness of the film, followed by selective chemical etching to remove the particle-damaged tracks, and thereby create nanopores through the complete thickness of the film. The etching step may also remove small amounts of the surrounding undamaged film. Such methods ha ⁇ produced films having pores a sitlail as 10 nanometers in diameter, and pore densities approaching 10 to the ninth power pores per square centimeter. Polycarbonate and polyester resin films having such pore specifications are available from Nuclepore, Inc., and from Poretics Corp. One example is the polycarbonate screen membrane from Poretics, Catalog No. 19368PCTE
  • nanoporous films include the use of lasers, x-rays, gamma rays, or electron beams to burn nanoscopic damage tracks and/or holes through a resin film. Selective chemical etching is then used to create nanoscopic pores, or to enlarge the holes in the film The pores are then filled with a metal or other conductor Dy electroplating, electroless plating, or vapor deposition Excess metal formed on the membrane surface or surfaces is then removed, whereby tne only remaining metal is located in the pores
  • the membrane is then exposed to an etchant that does not attack the metal, so that a small amount of the membrane surface surrounding the tips of the metal fibrils is removed, tnereby providing tips that extend slightly above the remaining membrane surface
  • the exposed tips may then be tinned with solder, to achieve solder contact with the pads of a circuit chip or substrate, etc ,if desired It has been demonstrated, however, that reliable electrical interconnection is achieved by contact alone, without solder bonding or any other form of fixed attachment to the tips of the metal nanofibrils used in accordance with the invention.
  • the pores may be arranged in a rectangular or triangular pattern; and moreover, selected surface areas without pores may be provided, so that conductive thin film patterns may be fabricated on such surface areas of the membrane, for current propagation in x-y directions, combined with z-axis conduction in other areas of the same membrane.
  • the same result can be achieved, beginning with a random distribution of pores, by selectively masking portions of the membrane surface during etching or plating.
  • Polymeric membranes used in accordance with the invention include both thermoplastic and thermosetting polymer films. For example, upon heating the combination of an electronic device in contact with a metal-filled, nanoporous thermoplastic membrane, the softening of the plastic causes an adhesive bonding of the device to the membrane, thereby holding the tips of the metal fibrils in contact with the device.
  • thermosetting polymeric membrane having metal-filled pores is also useful for the same purpose, except that the heating step causes a permanent hardening (cure) of the film, thereby bonding the devices to the surface of the membrane, and holding the fibril tips in place.
  • an elastomeric film composition is preferred.
  • the surface of such a film will conform completely with the microscopic irregularities of a circuit surface, and thereby permit maximum contact area between each film surface and each circuit or substrate surface.
  • Such a film interface also causes virtually all the metal fibril tips to make good contact with the circuit surface, including each bonding pad, on both sides of the film. The net result is a very low resistance interconnection.
  • a pressure-sensitive adhesive surface can be prepared by using a pressure-sensitive adhesive film, or by coating the membrane with a tackifier, such as silicone polymer. Such a tacky surface holds circuit chips in place on the surface of the membrane.
  • the Z-axis conductive films of the invention have the additional advantage of enabling a reliable interconnection of parts that are not perfectly planar. That is, all the contact pads on a device surface are normally designed to lie in precisely the same plane. But if one or more of the pads deviate from the plane, defective or unreliable bonding can result. Now, such nonplanar pads can be reliably bonded, since the films of the invention exhibit a sufficient plastic "flow" to engage all such pads.
  • a large number of pores may be kept open, i.e., unfilled. This allows the film to exhibit compressibility, which is not characteristic of a normal polymeric film.
  • the x-y and/or z coefficient of thermal expansion (CTE) for the membrane can be approximately matched with the CTE of the parts bonded thereto. More specifically, the CTE can be matched with that of silicon, metals and ceramics, such as used in the fabrication of microelectronic semiconductor devices, to provide improved reliability.
  • Liquid crystal polymers and rigid rod polymers are particularly suited for this purpose, including Vectra from Hoechst, xyDAR from AMOCO, Poly X from Max Dern, PIBO from Dow, and certain polyimides from DuPont.
  • Figure 1 is a greatly enlarged cross-sectional view of a prior anisotropically conductive microelectronic connection , using a polymeric adhesive film having 40-micron metal spheres distributed therein .
  • Figure 2 is a greatly enlarged cross-sectional view of a micro- electronic connection interface in accordance with the invention, using a microporous polymeric Z-axis conductive film having a 5-micron diameter gold fibril fixed within each film pore.
  • Figure 3 is a greatly enlarged cross-sectional view of a micro- electronic connection interface in accordance with the invention, using a nanoporous polymeric Z-axis conductive film having a 0.375-micron diameter gold fibril fixed within each film pore.
  • Figure 4 is a greatly enlarged cross-sectional view of a micro ⁇ electronic connection interface in accordance with the invention, using a nanoporous polymeric Z-axis film having a 25-nanometer diameter gold fibril fixed within each pore.
  • Figure 5 is a greatly enlarged cross-sectional view of plural microelectronic interconnections in accordance with the present invention, using a nanoporous polymeric Z-axis film having a 25-nanometer gold fibril within each pore.
  • Figure 6 is a cross-sectional view of a nanoporous resin film having some orthogonal pores filled with gold fibrils.
  • Figure 7 is a cross-sectional view of a nanoporous resin film having oblique and orthogonal pores filled with gold fibrils.
  • Figure 8 is a cross-sectional view of a nanoporous resin film having selected pores filled with gold, and other pores filled with a thermally-conductive dielectric material.
  • Figure 9 is a top view of a package base and an integrated circuit chip to be mounted therein according to the invention.
  • Figure 10 is a cross-sectional view of two circuit chips, inter ⁇ connected with each other in accordance with the invention.
  • Figure 11 is a cross-sectional expanded view of an assembly comprising a plurality of printed circuit boards interconnected with the Z-axis film of the invention.
  • Figure 12 is a perspective view of a Z-axis conductive film, used to form interconnections in accordance with the invention.
  • Figure 13 is a perspective view of a conceptual composite of a Z-axis conductive film, useful in accordance with the invention, showing numerous pore variations and combinations.
  • the prior use of 40-micron metal spheres 11 within a polymeric adhesive film is unsatisfactory, because the sphere provides a very small surface contact area with bonding pads 12 and 13. Although the pads have polished surfaces, nanoscopic irregularities remain, making it more difficult for spheres 11 to achieve good contact. Because the contact area is very small, low-resistance contact is impossible. Even the use of three or more spheres per pad will not correct this problem. A contact pad is not large enough to permit contact with more than three or four such spheres. Moreover, the spheres do not enable adequate tolerance or adjustment to the bonding of nonplanar surfaces.
  • one embodiment of the present invention includes the use of 5-micron diameter metal fibrils 15 within each pore of film 16, such that multiple fibril tips make contact with pad 17.
  • a single fibril tip may not provide substantially more surface contact area with the pad than sphere 11, the key difference is that 230 fibril tips will fit within the same pad area that accommodates only three of the spheres.
  • the total resistance of the contact in Figure 2 is substantially less than the total resistance of the contact in Figure 1; and may be only l/50th or 1/lOOth as great .
  • another embodiment of the invention includes the use of 0.375-micron diameter metal fibrils 21 within the pores of film 22, for making electrical contact with pad 23. Even though each fibril may contact only a single point on pad 23, the number of fibril tips that contact a single pad exceeds 40,000. Thus, the total resistance of the contact in Figure 2 is much greater that the total resistance f the contact in Figure 3.
  • nanoscopic metal fibrils 26 within polymer film 27 have a diameter of ony 25 nanometers, such that the tips are readily capable of entering each of valleys 27 in the surface of pad 28.
  • This intimate contact in combination with the large number of fibrils that contact each pad, provides an even lower resistance contact than the embodiment of Figure 3, and is comparable with the resistance characteristic of an alloyed wire bond.
  • the dynamic thickness range of the film is greater, due to the greater aspect ratio of the film pores, and the greater degree of deformability of the metal fibrils in the pores.
  • Actual contact resistance is a function of a number of parameters, including fibril deflection force, malleability of the metal, surface roughness, planarity of the parts, and others.
  • the film used in accordance with the invention is capable of deforming under pressure to fill the entire space between circuit parts. Consequently, nanoscopic fibrils 31 readily deform, as a result of film compression between pads 32 and 33. Similarly, fibrils 34 readily deform, as a result of film compression between pads 35 and 36. The remaining fibrils 37 are not compressed, and they make no electrical contact, but they do serve to conduct heat.
  • an example of the interconnection means of the invention comprises synthetic polycarbonate resin membrane 41 having a thickness of 1 mil, and up to one million or more parallel nanoscopic pores 42, each pore having a diameter of about 30 nm, at least some of which are filled with gold nanofibrils 43.
  • the gold may be replaced with another metal or other conductive material, including copper, platinum, nickel, and silver, for example.
  • Conductive polymers are also useful nanofibrils for some applications, including polyacetylene, polypyrrole, polythiophene, and polyaniline, for example.
  • Polysilicone membranes are particularly useful in that they have a low elastic modulus which allows the film to accommodate the deflections or deformations associated with the bonding of contact pads on nonplanar surfaces; and also allows greater tolerance to the interconnection of parts having different coefficients of thermal expansion.
  • another example of the interconnection means of the invention comprises synthetic polyester membrane 44 having a thickness of 1 mil, a first multiplicity of parallel nanoscopic pores 45 orthogonal to the membrane surface, a second multiplicity of parallel nanoscopic pores 46 sloped at a substantial angle with respect to pores 45, and preferably a third multiplicity of nanoscopic pores 47, sloped at a substantial angle with respect to both pores 45 and 46.
  • Pores 15 are filled with gold, for example, for the purpose of electrical conduction, while the other pores are filled with a material having greater thermal conductivity than gold, but electrically nonconductive, such as diamond, for example, so that greater heat dissipation is achieved, especially in the x-y directions, compared with the example of Figure 1.
  • another variation of the interconnection membrane comprises synthetic resin film 48 having pores 49 filled with gold, pores 50 filled with a material having greater thermal conductivity than gold, and pores 51 left open, for the purpose of allowing the membrane to exhibit compressibility, and a lower apparent modulus of elasticity than is characteristic of a nonporous membrane having the same composition.
  • a single circuit chip 52 is inverted within package base 53 such that contact pads on the face of the chip are electrically interconnected with pads 54 of base 53, by means of membrane 41, separately illustrated in Figure 1.
  • membrane 41 is required, except to cover all of pads 54, since all portions thereof include gold-filled pores.
  • Approximate alignment of the chip is required, only to ensure that some portion of each contact pad is vertically oriented over some portion of the corresponding pad on base 53.
  • the chip is held in place by the top of the package, (not shown) which is designed to apply pressure to the chip, when the package is fully assembled.
  • membrane 41 is selected to function as an adhesive by itself, with or without first applying heat to soften the membrane surface, so that a permanent chemical bonding of the membrane to both the chip and the package base occurs .
  • two circuit chips 61 and 62 are readily interconnected by means of nanoporous anisotropically conductive membrane 63 having at least some of its pores filled with gold or other conductor.
  • the chips are interconnected with substrate 64 by means of nanoporous anisotropically conductive membrane 65.
  • Z-axis film 81 includes a large number of metal-filled pores 82, a large number of unfilled pores 83, and a substantial area 84 without pores, achieved by masking the area during the pore-forming procedure.
  • Z-axis conductive film 91 includes a variety of pore configurations, and a variety of pore contents .
  • film 91 includes an area of random pore distribution, a rectangular grid array of metal-filled pores, a triangular grid array of metal-filled pores, a square pattern of semiconductor-filled pores, a number of unfilled pores, and a number of partially-filled pores, illustrating conceptually that a multiplicity of combinations and permutations are within the scope of the invention.

Abstract

L'invention concerne un assemblage d'au moins deux éléments microélectroniques, où l'interconnexion électrique et/ou thermique entre les éléments se fait au moyen de fibrilles (15) ou tubules (15) nanoscopiques multiples, discrets et conducteurs, fixés dans les pores d'un film isolant (16). On dit qu'un tel film a une conductivité électrique anisotrope, c'est-à-dire suivant l'axe des Z, avec peu ou pas de conductivité dans les autres directions.
PCT/US1996/016023 1995-09-27 1996-09-27 Assemblages microelectroniques comprenant des films conducteurs suivant l'axe des z WO1997012397A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
BR9606658A BR9606658A (pt) 1995-09-27 1996-09-27 Montagem de microeletrônicos incluindo filmes de condutividade de eixo z
AU73932/96A AU703591B2 (en) 1995-09-27 1996-09-27 Microelectronic assemblies including z-axis conductive films
JP9513771A JPH10513611A (ja) 1995-09-27 1996-09-27 Ｚ軸電導フィルムを含むマイクロ電子組立体
EP96936229A EP0811245A4 (fr) 1995-09-27 1996-09-27 Assemblages microelectroniques comprenant des films conducteurs suivant l'axe des z
MXPA/A/1997/003780A MXPA97003780A (en) 1995-09-27 1997-05-22 Microelectronic assemblies that include conductor films on the eject

Applications Claiming Priority (10)

Application Number Priority Date Filing Date Title
US439195P 1995-09-27 1995-09-27
US439695P 1995-09-27 1995-09-27
US441595P 1995-09-27 1995-09-27
US440295P 1995-09-27 1995-09-27
US439495P 1995-09-27 1995-09-27
US60/004,396 1995-09-27
US60/004,391 1995-09-27
US60/004,402 1995-09-27
US60/004,415 1995-09-27
US60/004,394 1995-09-27

Publications (1)

Publication Number Publication Date
WO1997012397A1 true WO1997012397A1 (fr) 1997-04-03

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PCT/US1996/016023 WO1997012397A1 (fr) 1995-09-27 1996-09-27 Assemblages microelectroniques comprenant des films conducteurs suivant l'axe des z

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EP (1) EP0811245A4 (fr)
JP (1) JPH10513611A (fr)
CN (1) CN1165584A (fr)
AU (1) AU703591B2 (fr)
BR (1) BR9606658A (fr)
CA (1) CA2205810A1 (fr)
TW (1) TW321789B (fr)
WO (1) WO1997012397A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002055431A2 (fr) * 2001-01-10 2002-07-18 Raytheon Company Interconnexion au niveau plaquette
DE102005020453A1 (de) * 2005-04-29 2006-11-09 Infineon Technologies Ag Flachleiterstruktur für ein Halbleiterbauteil und Verfahren zur Herstellung derselben
DE102007055017A1 (de) * 2007-11-14 2009-05-28 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zum Verbinden zweier Fügeflächen

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8963323B2 (en) 2008-06-20 2015-02-24 Alcatel Lucent Heat-transfer structure
KR101944898B1 (ko) 2012-06-11 2019-02-01 에스케이케미칼 주식회사 폴리아릴렌 설파이드 수지 조성물 및 이의 제조 방법
EP2854170B1 (fr) 2013-09-27 2022-01-26 Alcatel Lucent Structure pour une interface de transfert de chaleur et son procédé de fabrication
CN107113984B (zh) * 2014-12-19 2019-06-04 富士胶片株式会社 多层配线基板
US10595440B2 (en) * 2018-03-02 2020-03-17 Northrop Grumman Systems Corporation Thermal gasket with high transverse thermal conductivity

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4283464A (en) * 1979-05-08 1981-08-11 Norman Hascoe Prefabricated composite metallic heat-transmitting plate unit
US5229643A (en) * 1990-07-25 1993-07-20 Hitachi, Ltd. Semiconductor apparatus and semiconductor package
US5298791A (en) * 1991-08-13 1994-03-29 Chomerics, Inc. Thermally conductive electrical assembly
US5358795A (en) * 1991-10-12 1994-10-25 Sumitomo Special Metals Co., Ltd. Heat-conductive material and method of producing the same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6148952A (ja) * 1984-08-16 1986-03-10 Toshiba Corp 半導体装置
EP0854506A3 (fr) * 1987-03-04 1999-03-31 Canon Kabushiki Kaisha Pièce de connexion électrique et pièce de circuit électrique
JPS6412406A (en) * 1987-07-07 1989-01-17 Nitto Denko Corp Directional conductor and manufacture thereof
DE69216658T2 (de) * 1991-02-25 1997-08-07 Canon Kk Vorrichtung und Verfahren zur Verbindung elektrischer Bauelemente
JPH0547219A (ja) * 1991-08-13 1993-02-26 Ricoh Co Ltd 異方性導電膜およびそれを用いた電子部品の接続方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4283464A (en) * 1979-05-08 1981-08-11 Norman Hascoe Prefabricated composite metallic heat-transmitting plate unit
US5229643A (en) * 1990-07-25 1993-07-20 Hitachi, Ltd. Semiconductor apparatus and semiconductor package
US5298791A (en) * 1991-08-13 1994-03-29 Chomerics, Inc. Thermally conductive electrical assembly
US5358795A (en) * 1991-10-12 1994-10-25 Sumitomo Special Metals Co., Ltd. Heat-conductive material and method of producing the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP0811245A4 *

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002055431A2 (fr) * 2001-01-10 2002-07-18 Raytheon Company Interconnexion au niveau plaquette
US6512300B2 (en) 2001-01-10 2003-01-28 Raytheon Company Water level interconnection
WO2002055431A3 (fr) * 2001-01-10 2003-01-30 Raytheon Co Interconnexion au niveau plaquette
US6633079B2 (en) 2001-01-10 2003-10-14 Raytheon Company Wafer level interconnection
DE102005020453A1 (de) * 2005-04-29 2006-11-09 Infineon Technologies Ag Flachleiterstruktur für ein Halbleiterbauteil und Verfahren zur Herstellung derselben
DE102005020453B4 (de) * 2005-04-29 2009-07-02 Infineon Technologies Ag Halbleiterbauteil mit einer Flachleiterstruktur und Verfahren zur Herstellung einer Flachleiterstruktur und Verfahren zur Herstellung eines Halbleiterbauteils
US7589403B2 (en) 2005-04-29 2009-09-15 Infineon Technologies Ag Lead structure for a semiconductor component and method for producing the same
DE102007055017A1 (de) * 2007-11-14 2009-05-28 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zum Verbinden zweier Fügeflächen
DE102007055017B4 (de) * 2007-11-14 2010-11-04 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zum Verbinden zweier Fügeflächen und Bauteil mit zwei verbundenen Fügeflächen

Also Published As

Publication number Publication date
JPH10513611A (ja) 1998-12-22
BR9606658A (pt) 1997-11-04
AU703591B2 (en) 1999-03-25
EP0811245A1 (fr) 1997-12-10
AU7393296A (en) 1997-04-17
TW321789B (fr) 1997-12-01
EP0811245A4 (fr) 1998-11-18
CN1165584A (zh) 1997-11-19
CA2205810A1 (fr) 1997-04-03
MX9703780A (es) 1998-05-31

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