WO1997006523A1 - Systemes et memoires unifies de memoire tampon image/systeme et leurs methodes d'utilisation - Google Patents

Systemes et memoires unifies de memoire tampon image/systeme et leurs methodes d'utilisation Download PDF

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Publication number
WO1997006523A1
WO1997006523A1 PCT/US1996/012829 US9612829W WO9706523A1 WO 1997006523 A1 WO1997006523 A1 WO 1997006523A1 US 9612829 W US9612829 W US 9612829W WO 9706523 A1 WO9706523 A1 WO 9706523A1
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WO
WIPO (PCT)
Prior art keywords
frame buffer
display
memory
processing system
data
Prior art date
Application number
PCT/US1996/012829
Other languages
English (en)
Inventor
G. R. Mohan Rao
Original Assignee
Cirrus Logic, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cirrus Logic, Inc. filed Critical Cirrus Logic, Inc.
Priority to EP96931370A priority Critical patent/EP0843872A1/fr
Priority to JP9508627A priority patent/JPH11510620A/ja
Publication of WO1997006523A1 publication Critical patent/WO1997006523A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/399—Control of the bit-mapped memory using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0024—Peripheral component interconnect [PCI]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/122—Tiling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/125—Frame memory handling using unified memory architecture [UMA]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto

Definitions

  • the present invention relates in general to data processing systems including display subsystems and in particular to unified system/frame buffer memories and systems and methods using the same.
  • a typical processing system with video/graphics display capability includes a central processing unit (C PU ) , a d isplay controller coupled with the C PU by a C PU local bus ( directly and/or through core logic ) , a system memory coupled to the above CPU local bus through core logic, a frame buffer memory coupled to the display controller via a peripheral local bus (e.g., PCI ) , peripheral circuitry (e.g., clock drivers and signal converters, display driver circuitry), and a display unit.
  • CPU central processing unit
  • a d isplay controller coupled with the C PU by a C PU local bus ( directly and/or through core logic )
  • system memory coupled to the above CPU local bus through core logic
  • a frame buffer memory coupled to the display controller via a peripheral local bus (e.g., PCI )
  • peripheral circuitry e.g., clock drivers and signal converters, display driver circuitry
  • the CPU is the system master and generally provides overall system control in conjunction with the software operating system.
  • the C PU communicates with the system memory holding instructions and data necessary for program execution, normally through core logic.
  • the core logic i s two to seven chips, with one or more chips being "address intensive" and one or more other chips being “data path intensive.”
  • the CPU also, in response to user commands and program instructions, controls the contents of the graphics images to be displayed on the display unit via the display controller.
  • the display controller which may be, for example, a video graphics architecture (VGA) controller, generally interfaces the CPU and the display driver c i rcuitry, manages the exchange of graphics and/or video data between the frame buffer and the CPU an d d isplay during display data update and screen refresh operations, controls frame buffer memory operations, and performs additional basic processing on the subject graphics or video data.
  • VGA video graphics architecture
  • t he display controller may also include the capability of performing operations such as line draws and polygon fills.
  • the display controller is for the most part a slave to the CPU.
  • the CPU itself provides the display data necessary to update the display screen when a change in the displayed images (data) is required. Due to overhead constraints on the CPU, (as well as bandwidth limitations on PCI local bus or other buses) and limits on the size of the display controller write buffer, the updated display data is generated and stored in the system memory.
  • the CPU reads the required information (typically both addresses to the frame buffer and pixel data) from the system memory via the core logic and the CPU local bus and then writes that data via the core logic and PCI local bus into the write buffer of the display controller.
  • Multiple CPU cycles i.e., a read and a write cycle
  • DRAM dynamic random access memory
  • DRAMs are constructed only in quadrupling densities (i.e., 256KB, 1MB, 4MB) and the maximum size of each addressable storage location is 16 bits wide.
  • multiple chips are normally required to construct the system memory (which needs to be 64 to 72 bits wide for today's PC systems) , although the full capacity of each individual device may not be used.
  • 4 parallel "by 16" devices are required per bank.
  • each bank would have a corresponding capacity of IMBytes or 4MBytes respectively. If intermediate capacities are required per bank, for example 3MBytes, the larger incrementation must be selected and some memory will go unused. This problem is compounded by the fact that the use of the system memory space is also suboptimal, since the CPU, for operating efficiency, does not necessarily store data contiguously in memory.
  • the frame buffer normally does not need to be large (typically within the range of 0.8 to 1.25 megabytes), it does need to be "wide" to support display refresh bandwidth requirements. For example, assume that the frame buffer is supporting a 64-bit wide data bus to the display controller. To support such a bus, 4 parallel "by 16" DRAMs are required. If conventional 256k by 16 DRAMs are used, the frame buffer will have a total capacity of 2 megabytes. Thus, even with the largest frame buffers (i.e., 1.25 megabytes) substantial amounts of memory space remain unused.
  • the need has arisen for improved apparatus, systems, and methods for more efficiently constructing and managing memory in processing and display systems.
  • the need has arisen for techniques to conserve CPU operating cycles during display updates.
  • such techniques would free rhe CPU to perform other critical operations and thus improve overall system performance.
  • the need has arisen for circuits, systems and methods for more efficiently constructing and managing the system and frame buffer memories required in display processing systems.
  • such apparatus systems and methods should minimize the number of devices required to construct such memories.
  • DRAMs could be multiplexed address/RAS-CAS type systems, or multiple clock/synchronous DRAMs (now under consideration in the industry) or synchronous graphics DRAMs, or DRAMs with special interfaces.
  • a processing system which includes a unified system/frame buffer memory system.
  • both the frame buffer and system memory are collocated in a single integrated circuit or bank of integrated circuits. This is in contrast to the presently-available display control systems where the frame buffer is separate and apart from the system memory and must interface with the remainder of the system through the display controller.
  • the frame buffer area cf the unified memory includes at least 2 physical memory blocks. One block is used for screen refresh by either the display controller or the CPU. The second block is used for display data update.
  • the system CPU can update data in the update frame buffer block by directly writing to the desired locations.
  • these uodates can be made to the update buffer while the refresh buffer is providing data for refresh of its display screen. This is in contrast to presently available systems where to perform an update, the CPU must first store/retrieve the update data in the system memory, read that data from the system memory and then write that data to the display controller write buffer. Not only do the principles of the present invention conserve valuable system ' operating cycles, but also allow for the elimination of the write buffer on the display controller, since reads can be made directly from the refresh buffer.
  • a processing system which includes a unified system memory having a system memory area and a plurality of frame buffer memory areas.
  • the processing system further includes a central processing unit, the unified memory lying within an address space of the central processing unit.
  • the central processing unit is operable to update display data in a first selected one of the frame buffer areas while display data from a second selected one of the frame buffer areas provides data for refresh of a display screen of an associated display device.
  • a processing system is provided which includes a unified memory including at least one system memory space and first and second frame buffer spaces. Circuitry is provided as part of the processing system for updating display data stored in the first frame buffer space.
  • Circuitry is also provided for retrieving display data stored in the second frame buffer space for generating a corresponding display substantially concurrent with the updating of the display data stored in the first frame buffer space. Additionally, the processing system includes circuitry for retrieving display data stored in the first frame buffer space for generating a corresponding updated display.
  • An additional processing system embodies the present invention.
  • the processing system includes the central processing unit, a CPU local bus coupled to the central processing unit, core logic coupled to the CPU local bus, a display controller coupled to the core logic and the above bus and a unified memory system, coupled to the core logic, the unified memory providing a system memory area and a plurality of frame buffer areas.
  • a unified memory is partitioned into a system memory and first and second frame buffer memories. Display data stored in the first frame buffer is updated while display data stored in the second frame buffer is used for generating a corresponding display. Upon completion of the updating of data in the first frame buffer, the data stored in the first frame buffer is retrieved for generating a corresponding updated display.
  • Systems embodying principles of the present invention have substantial advantages over those of the prior art. In particular, such principle can save CPU operating cycles during display updates freeing the CPU to perform other critical operations and thus improving overall system performance. Additionally, the unified system memory of the present invention allows for the more efficient construction and operation of the memory spaces required in a processing/display system. In particular, by collocating the system memory and frame buffer memory, unused memory space can be minimized an d consequently more compact, inexpensive, and efficient systems can be implemented.
  • FIGURE 1 is a functional block diagram of a portion of a processing system responsible for the generation and control of display data according to the principles of the present invention
  • FIGURE 2 is a functional block diagram of one possible construction of the unified memory depicted in FIGURE 1;
  • FIGURE 3 is a functional block diagram of an integrated display controller/unified memory device suitable in one application in the system of FIGURE 1.
  • FIGURE 1 is a high level functional block diagram of the portion of a processing system 100 controlling the display of graphics and/or video data.
  • System 100 includes a central processing unit 101, a CPU local bus 102, core logic 103, a display controller 104, a unified system/display memory 105, a digital to analog converter (DAC) 106 and a display device 107.
  • DAC digital to analog converter
  • CPU 101 is the "master" which controls the overall operation of system 100. Among other things, CPU 101 performs various data processing functions and determines the content of the graphics data to be displayed on display unit 107 in response to user commands and/or the execution of application software.
  • CPU 101 may be for example a general purpose microprocessor, such as an Intel Pentium class microprocessor or the like, used in commercial personal computers.
  • CPU 101 communicates with the remainder of system 100 via CPU local bus 102, which may be for example a special bus, or a general bus (common in the industry) .
  • Memory 105 is a "unified" memory system since the system memory and frame buffer are collocated in a single integrated circuit or bank of integrated circuits. This is in contrast to the prior art systems discussed above where the frame buffer is separate and apart from the system memory and interfaces with the remainder of the system through the display controller.
  • Core logic 103 under the direction of CPU 101, controls the exchange of data, addresses, and instructions between CPU 101, display controller 104, and unified memory 105.
  • Core logic 103 may be any one of a number of commercially available core logic chip sets designed for compatibility with the remainder of the system, and in particular with CPU 101.
  • One or more core logic chips, such as chip 112 in the illustrated system, are typically "address intensive" while one or more core logic chips, such as chip 114 in FIGURE 1, are “data intensive.”
  • CPU 101 can directly communicate with core logic 103 or through an external (L2) cache 115. It should be noted that CPU 101 can also include on-board (Ll) cache.
  • L2 cache 115 may be for example a 256KByte fast SRAM device(s).
  • Display controller 104 may be any one of a number of commercially available VGA display controllers.
  • Display controller 104 may receive data, instructions and/or addresses from CPU 101 either through core logic 103 ox directly from CPU 101 through CPU local bus 102. Data, instructions, and addresses are exchanged between display controller 104 and unified memory 105 through core logic 103. Further, addresses and instructions may be exchanged between core logic 103 and display controller 104 via a local bus which may be for example a PCI local bus.
  • display controller 104 controls screen refresh, executes a limited number of graphics functions such as line draws, polygon fills, color space conversion, display data interpolation and zooming, and video streaming and handles other ministerial chores such as power management. Video data may be directly input into display controller 104.
  • Digital to analog converter 106 receives digital data from controller 104 and outputs the analog data to drive display 107 in response.
  • DAC 106 is integrated with display controller 104 onto a single chip.
  • DAC 106 may also include a color palette, YUV to RGB format conversion circuitry, and/or X- and Y- zooming circuitry, to name a few options.
  • Display 107 may be for example a CRT unit, a liquid crystal display, electroluminescent display, plasma display, or other type of display device which displays images on a screen as a plurality of pixels. It should also be noted that in alternate embodiments, "display" 107 may be another type of output device such as a laser printer or similar document view/print appliance.
  • unified memory 105 embodies both a system memory 109 and the display frame buffer, which is divided into frame buffer block A 110 and frame buffer block B 111.
  • System memory 109 is preferably a traditional system memory which stores data, addresses, and instructions under the command of CPU 101 as required for executing various processing functions and applications programs.
  • each frame buffer block 110 and 111 resides in the same CPU address space as system memory 109.
  • each frame buffer block 110 and 111 is assigned a contiguous block (set) of addresses within the address space of CPU 101, although the address blocks assigned to the two banks may or may not be contiguous with each other.
  • the addresses allotted frame buffer banks A and B may change depending on the partitioning of unified memory 105 by the operating system being executed by CPU 101.
  • 111 maps pixel by pixel to the screen of display 107 as is done in a conventional frame buffer.
  • each frame buffer bank 110/111 maintains the pixel data corresponding to a display screen.
  • One memory bank 110/111 is the "display memory” or “refresh memory” which the display controller 104 accesses (using addresses generated by display controller 104) to refresh the screen on display 107.
  • CPU 101 may also directly access the frame buffer bank 110/111 currently acting as the display memory and refresh the screen of display 107 itself. In this case, display controller 104 would either be bypassed or would simply act as a pipeline for the pixel data being sent to DAC 106 and display 107.
  • all the display data is in one contiguous "refresh block" in the refresh memory which allows the display controller to access the refresh data stored therein with minimal intervention of CPU 101 (if the display data were to be stored in non-contiguous areas of the memory, more CPU intervention would be required to "direct” the display controller to the data.) Since 75% of all display processing time is normally used for screen refresh, the ability to shift the display refresh to the display controller can substantially improve system performance as the CPU 101 is made available for other tasks.
  • the other frame buffer bank 110/111 is used exclusively for screen update.
  • CPU 101 updates the display data within the refresh frame buffer block 110/111 by directly writing to the locations holding the data being modified.
  • the prior art multiple step process of writing to the system memory, reading from the system memory when the display controller write buffer is available, and then writing to frame buffer is thereby reduced to a series of direct write operations to the frame buffer update block.
  • the update of each word of pixel data within the "screen update" bank is performed using only one CPU cycle for each word of data being updated ( depending on such factors as the width of the data bus and/or number of bits of data CPU 101 can write to unified memory 105 at one time, each word being modified can represent one or more pixels) .
  • the number of CPU clock cycles which are required to perform the screen update is essentially halved.
  • the display controller write buffers can even be eliminated. Display refresh in this instance may be performed by simply retrieving data directly from the refresh frame buffer block 110/111, and pipelined through display controller 104 towards display unit 107. In this case the refresh buffer essentially replaces the display controller write buffer.
  • Unified system/frame buffer memory 105 may either be constructed as a monolithic chip or as a multiple chip (device) subsystem. Such a subsystem 200 is illustrated in FIGURE 2.
  • System 200 is comprised of a plurality of memory banks 201. When used in system
  • each bank 201a is coupled to core logic 103 by an address bus 202, a data bus 203, and a control bus 204.
  • Banks 201 may operate in a non-multiplexed addressing scheme with address bus 202 simultaneously presenting both column and row address bits to banks 201.
  • banks 201 may operate in a multiplexed ( RAS/CAS ) scheme, as well as "synchronous DRAM schemes" ( a synchronous clock, in addition to RAS and CAS), with row and column address multiplexed on address bus 202.
  • Control bus 204 carries the conventional DRAM control signals (such as RAS and CAS) in a multiplexed address scheme, output enable, and read/write.
  • each bank 201 is associated with a separate set and bank selection is a function of the addresses presented on address bus 202.
  • unified memory 105 In the application of unified system/frame buffer memory 105, one bank 201 may be used for frame buffer block A, a second bank 201 used for frame buffer block B and the remaining banks 201 used for system memory 109.
  • unified memory 105 is an 8-megabyte (64-megabit) memory suitable for supporting a state of the art operating -system such as Microsoft Windows 95.
  • each bank 201 is a 1-megabyte DRAM device. In order to perform a 1-bit out of 64-megabit selection (i.e. a "by 1" device is being used), 26 address bits are required in a non-multiplexed scheme.
  • each bank is constructed as a by 4, by 8, by 16, by 32, or by 64-bit device, then the number of address bits is appropriately reduced.
  • 3 bits of each address word (for example, the 3 least significant bits) are used for bank select.
  • CPU 101 simply modifies these 3 address bits.
  • FIGURE 3 is a functional block diagram of an alternate processing system 300.
  • display controller 104 and DAC 106 have been integrated along with system memory 105 and a plurality of frame buffer blocks onto a single chip monolithic integrate d circuit 301.
  • Display controller/DAC 104/106 accesses each frame buffer block through an internal address and data bus 306, which is also used to drive display device 107.
  • CPU 101 can directly write to any frame buffer block to affect a display update.
  • one or more of the other frame buffer blocks can be used to refresh the display screen.
  • a pair of blocks 304A and 304B are provided as memory spaces for a corresponding pair of video frame buffers A and B.
  • a pair of blocks 305A and 305B which provide a corresponding pair of graphics frame buffers A and B.
  • the video frame buffer blocks 304A and 304B are alternately used as a video update block (buffer) and a video refresh block ( buffer) .
  • buffers 305A and 305B which alternately act as update and refresh blocks ( buffers) only for the graphics data.
  • MPEG motion picture expert's group
  • Block 307 is dedicated to storing data in the MPEG format and is also within the address base of CPU 101.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Graphics (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

Système de traitement (100) comprenant un système mémoire unifié (105) présentant une zone mémoire système (109) et une série de zones mémoire tampon image (110/111). Une unité centrale de traitement (101) comporte dans son espace adresse une mémoire (105) de système unifié et fonctionne pour mettre à jour les données d'affichage dans la première des zones tampon image choisies (110/111) tandis que les données d'affichage d'une deuxième zone image tampon choisie (110/111) fournissent les données de rafraîchissement de l'écran d'affichage d'un dispositif d'affichage associé.
PCT/US1996/012829 1995-08-08 1996-08-05 Systemes et memoires unifies de memoire tampon image/systeme et leurs methodes d'utilisation WO1997006523A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP96931370A EP0843872A1 (fr) 1995-08-08 1996-08-05 Systemes et memoires unifies de memoire tampon image/systeme et leurs methodes d'utilisation
JP9508627A JPH11510620A (ja) 1995-08-08 1996-08-05 統合されたシステム／フレームバッファメモリ及びシステム、ならびにそれらの使用方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US51257495A 1995-08-08 1995-08-08
US08/512,574 1995-08-08

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WO1997006523A1 true WO1997006523A1 (fr) 1997-02-20

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EP (1) EP0843872A1 (fr)
JP (1) JPH11510620A (fr)
KR (1) KR19990036270A (fr)
WO (1) WO1997006523A1 (fr)

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WO1999028893A1 (fr) * 1997-12-01 1999-06-10 Mediaq, Inc. Architecture informatique haute performance hautement integree dont la memoire a limites fixes est extensible
WO1999034294A1 (fr) * 1997-12-24 1999-07-08 Creative Technology Ltd. Systeme de controle de memoire multicanal optimal
JP2001505342A (ja) * 1997-09-09 2001-04-17 メムトラックス エルエルシー 内部メモリ及び外部メモリコントロールを具備したコンピュータシステムコントローラ
US6414688B1 (en) * 1999-01-29 2002-07-02 Micron Technology, Inc. Programmable graphics memory method
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US7554551B1 (en) * 2000-06-07 2009-06-30 Apple Inc. Decoupling a color buffer from main memory
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LT3290043T (lt) 2015-06-01 2023-04-11 Saisei Pharma Co., Ltd. Fermentu apdorotas pieno produktas, jo gamybos būdas, kompozicija ir produktas

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KR19990036270A (ko) 1999-05-25
JPH11510620A (ja) 1999-09-14
EP0843872A1 (fr) 1998-05-27

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