WO1996042110A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO1996042110A1
WO1996042110A1 PCT/JP1996/001444 JP9601444W WO9642110A1 WO 1996042110 A1 WO1996042110 A1 WO 1996042110A1 JP 9601444 W JP9601444 W JP 9601444W WO 9642110 A1 WO9642110 A1 WO 9642110A1
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Prior art keywords
chip
conductor
semiconductor device
inductor
integrated circuit
Prior art date
Application number
PCT/JP1996/001444
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French (fr)
Japanese (ja)
Inventor
Takeshi Ikeda
Tsutomu Nakanishi
Akira Okamoto
Original Assignee
Niigata Seimitsu Co., Ltd.
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Publication date
Application filed by Niigata Seimitsu Co., Ltd. filed Critical Niigata Seimitsu Co., Ltd.
Priority to AU58442/96A priority Critical patent/AU5844296A/en
Publication of WO1996042110A1 publication Critical patent/WO1996042110A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10162—Shape being a cuboid with a square active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Definitions

  • the present invention relates to a semiconductor device in which a conductor used as an inductor or the like is formed in a part of an integrated circuit.
  • the inductor is an important circuit component, and it can be said that it is an indispensable component depending on the circuit to be composed.
  • an oscillator circuit using LC resonance and a tuning circuit included in a transceiver can be realized only by using an inductor.
  • the present invention has been made in view of such a point, and a purpose thereof is to form a semiconductor having a large inductance on a chip and to integrate the entire circuit including the inductor into a semiconductor. It is to provide a device.
  • FIG. 1 is a plan structural view of the chip of one embodiment
  • FIG. 2 is a top view showing a state where the chip shown in FIG. 1 is housed in a package
  • FIG. 3 is a plan view of the chip shown in FIG.
  • Figure 4 shows a schematic structure of a chip in which an inductor conductor is formed in the inner layer surface of the chip.
  • Figure 5 shows a partial cross-sectional structure near the inductor conductor.
  • FIG. 6 is a diagram showing a schematic structure of a chip in which a part of an inductor conductor is formed inside a bonding pad.
  • FIG. 1 is a plan view of a chip according to an embodiment.
  • an integrated circuit (not shown) is formed on a chip 10, and a plurality of bonding pads 12 are provided on the chip 10 outside the integrated circuit.
  • a predetermined number of turns of the inductor conductor 14 is formed in a spiral shape, that is, a bonding state. It is formed so as to go around the pad 12.
  • an n-type silicon substrate or another semiconductor material eg, an amorphous material such as germanium or amorphous silicon
  • a metal thin film such as aluminum or gold, or a semiconductor material such as polysilicon is used.
  • Inductor conductor 1 4 mask. C except that the pattern is different can be formed by semiconductor manufacturing techniques conventional various Incidentally, inductors evening conductor 1 4, a portion of an integrated circuit formed on the chip 1 0 A predetermined connection is made between the inductor conductor 14 and the integrated circuit using a bond wire or the like.
  • FIG. 2 and 3 are views showing a state where the chip 10 shown in FIG. 1 is housed in a package, FIG. 2 is a top view, and FIG. 3 is a side view.
  • the bonding pads 12 on the chip 10 and the package terminals 16 provided in the package are connected by bonding wires 18. Since the bonding wire 18 is generally attached in a state of being bent into a convex shape as shown in FIG. 3, there is no possibility that the bonding wire 18 and the conductor 14 are in contact with each other. Therefore, as shown in Fig. 1, Even when the conductor 14 is formed outside the inking pad 12, bonding can be performed in the same manner as in the past.
  • the spiral conductor 14 is formed in the vicinity of the outer edge of the chip surface, the diameter of the conductor 14 can be increased. The size of the inductance can be obtained. Further, when forming an integrated circuit on the chip 10, it is necessary to consider the arrangement of various active elements and passive elements, but in the present embodiment, the inductor conductor 14 is placed near the outer edge of the chip surface. Therefore, the formation of the inductor conductor 14 does not affect the arrangement of other integrated circuits. Therefore, there is no need to consider physical interference between the inductor conductor 14 and other integrated circuits, and the design and manufacturing processes are simplified. Also, since the bonding pad 12 and the package terminal 16 are connected by the bonding wire 18 bent in a convex shape, there is no possibility that the bonding wire 18 contacts the conductor 14. Bonding can be performed using the conventional manufacturing process as it is.
  • the conductor 14 is formed on the chip 10 between the bonding pad 12 and the outer edge of the chip 10.
  • the inductor conductor 14 can also be formed on the substrate.
  • FIG. 4 is a view showing a schematic structure of a chip 10 in which an inductor conductor 14 is formed in an inner layer surface of the chip 10.
  • each of the bonding pads 12 requires some area to connect the bonding wires 18. Accordingly, if the inductor conductor 14 is formed in the inner layer surface of the chip 10 facing the bonding pad 12 as shown in FIG. 4, the inductor conductor 14 is formed on the chip surface. It is not necessary to do so, and high-density mounting on the chip surface becomes possible. Also, even if the inductor conductors 14 are formed, the chip area does not need to be increased, so that the semiconductor device can be downsized.
  • the conductor 14 is formed in the inner layer surface of the chip 10 facing the bonding pad 12, but the integrated circuit formation area on the chip 10 is formed.
  • the conductor 14 may be formed in the chip inner layer surface facing the outer region of the chip, for example, in the chip inner layer surface facing the bonding pad 12 and the integrated circuit.
  • one inductor conductor 14 is formed outside the bonding pad 12, but two or more inductor conductors 14 may be formed.
  • each of the inductor conductors 14 can be transformer-coupled, so that the entire circuit including the transformer can be integrated. Becomes possible.
  • the plurality of conductors 14 may have a multilayer structure of two or more layers.
  • a two-layer structure it can be used as a part of a distributed constant type element in addition to the case of transformer coupling. That is, as shown in FIG. 5, a partial cross-sectional structure around the conductor 14 is shown. The insulating layer is formed so that all or a part of the conductor 14 is opposed to the first conductor 14 formed in a spiral shape.
  • a composite element having a distributed constant capacity formed between the two inductor conductors 14 and 14a can be formed.
  • the conductor 14 constituting a part of such a composite device a conductor 14 formed between the bonding pad 12 and the outer edge of the chip 10 or on the inner layer surface of the chip is used. It can also be used.
  • the entirety of the inductor conductor 14 is formed between the plurality of bonding pads 12 and the outer edge of the chip 10. It may be formed inside the pad 12.
  • FIG. 6 is a diagram showing a schematic structure of the chip 10 in which a part of the inductor conductor 14 is formed inside the bonding pad 12.
  • FIG. 6A shows a partial area of the chip surface.
  • Fig. 2 (B) shows an example in which two or more inductor conductors 14 are arranged in parallel.
  • the inductor conductors 14 By arranging the inductor conductors 14 as shown in FIG. 13B, the area between the bonding pad 12 and the outer edge of the chip 10 can be effectively used, and a plurality of inductor conductors having a low degree of magnetic coupling are provided. 14 can be formed.
  • the conductor 14 on the chip 10 is connected to the chip
  • the inductor conductor 14 is used as an antenna coil. be able to.
  • the operating voltage can be supplied to the integrated circuit formed on the chip 10 by using the inductor conductor 14 as an electromagnetic induction coil and generating an induced electromotive force at both ends of the inductor conductor 14. it can.
  • the inductor 14 is used as an antenna coil or an electromagnetic induction coil, for example, as shown in FIG. 1, the inductor 14 is bonded to the bonding wire 18 and the chip 10. If it is formed between the outer edge and the outer edge, a sufficiently large inductance can be obtained.
  • the present invention relates to a chip that faces along the outer edge of the chip surface, specifically, on the chip surface between the pad formed on the chip surface and the outer edge of the chip, or the outer region of the integrated circuit formation region Since the conductor is formed around the inner layer surface, the overall length of the conductor can be increased, and the inductance of the coil or the inductor formed on the chip can be sufficiently increased.
  • the present invention is used as an inductor or the like without affecting the electrical characteristics of the semiconductor device, since the pad and the package terminal are connected by the bonding wire so that the bonding and the wire do not contact the conductor.
  • Conductors can be integrated c

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

An integrated circuit is formed on a chip (10), and a plurality of bonding pads (12) are disposed on the outside of the chip (10). The bonding pads (12) are connected through bonding wires (18) with terminals (16) of the package of the chip (10). A conductor is formed on the chip surface between the bonding pads (12) and the side edges of the chip to provide a coil (14). Since it is extended along the border of the chip, the coil (14) can be large enough in size to have sufficient inductance.

Description

明 細 書 半導体装置 技術分野  Description Semiconductor device technology
本発明は、 インダクタ等として用いられる導体を集積回路の一部に形成した半 導体装置に関する。 背景技術  The present invention relates to a semiconductor device in which a conductor used as an inductor or the like is formed in a part of an integrated circuit. Background art
一般に、 インダク夕は重要な回路構成部品であり、 構成する回路によっては必 要不可欠な部品といえる。 例えば、 L C共振を利用した発振回路や送受信機に含 まれる同調回路は、 インダク夕を使用して初めて実現できる。  Generally, the inductor is an important circuit component, and it can be said that it is an indispensable component depending on the circuit to be composed. For example, an oscillator circuit using LC resonance and a tuning circuit included in a transceiver can be realized only by using an inductor.
ところで、 最近では回路の集積化が進んでおり、 例えばチップ表面に帯状の電 極を周回させてインダクタを形成することも可能である。 ところが、 チップ表面 に単に電極を周回させるだけでは大きなインダク夕ンスが得られない。 したがつ て、 このようなインダク夕を用いて発振回路や同調回路を構成すると、 発振周波 数や同調周波数が極めて高くなつて実用的でない。 このため、 従来は、 インダク 夕を含む回路をチップ上に集積化する場合には、 インダク夕のみは集積化せずに 外付け部品とし、 製品組み立て時等にィンダク夕とそれ以外の部品とを結線して いた。 発明の開示  By the way, the integration of circuits has been advanced recently. For example, it is possible to form an inductor by circling a strip-shaped electrode on the chip surface. However, simply turning the electrode around the chip surface does not provide a large inductance. Therefore, if an oscillation circuit or a tuning circuit is formed using such an inductor, the oscillation frequency or the tuning frequency becomes extremely high, which is not practical. For this reason, conventionally, when a circuit including an inductor is integrated on a chip, the inductor alone is not integrated but is used as an external component, and the inductor and other components are integrated during product assembly. It was connected. Disclosure of the invention
本発明は、 このような点に鑑みて創作されたものであり、 その目的はインダク 夕ンスの大きいィンダク夕をチップ上に形成し、 インダクタを含む回路全体を集 積化すること'ができる半導体装置を提供することにある。 図面の簡単な説明  The present invention has been made in view of such a point, and a purpose thereof is to form a semiconductor having a large inductance on a chip and to integrate the entire circuit including the inductor into a semiconductor. It is to provide a device. BRIEF DESCRIPTION OF THE FIGURES
第 1図は一実施形態のチップの平面構造図、 第 2図は第 1図に示したチップを パッケージに収めた状態を示す上面図、 第 3図は第 1図に示したチップをパッケ —ジに収めた状態を示す側面図、 第 4図はチップの内層面内にィンダク夕導体を 形成したチップの概略構造を示す図、 第 5図はィンダク夕導体付近の部分的な断 面構造を示す図、 第 6図はインダクタ導体の一部をボンディング 'パッ ドの内側 に形成したチップの概略構造を示す図である。 発明を実施するための最良の形態 FIG. 1 is a plan structural view of the chip of one embodiment, FIG. 2 is a top view showing a state where the chip shown in FIG. 1 is housed in a package, and FIG. 3 is a plan view of the chip shown in FIG. Figure 4 shows a schematic structure of a chip in which an inductor conductor is formed in the inner layer surface of the chip. Figure 5 shows a partial cross-sectional structure near the inductor conductor. FIG. 6 is a diagram showing a schematic structure of a chip in which a part of an inductor conductor is formed inside a bonding pad. BEST MODE FOR CARRYING OUT THE INVENTION
以下、 本発明の半導体装置を適用した一実施形態について、 図面を参照しなが ら具体的に説明する。  Hereinafter, an embodiment to which the semiconductor device of the present invention is applied will be specifically described with reference to the drawings.
第 1図は、 一実施形態のチップの平面構造図である。 同図において、 チップ 1 0には不図示の集積回路が形成されており、 この集積回路の外側のチップ 1 0上 にはボンディング · パヅド 1 2が複数設けられている。 ボンディング · パヅド 1 2の外側、 すなわちボンディング ·バッ ド 1 2とチップ 1 0の外縁との間のチッ プ 1 0上には、 所定ターン数のインダクタ導体 1 4が渦巻き形状に、 すなわちボ ンデイング ·パッ ド 1 2の周囲を周回するように形成されている。  FIG. 1 is a plan view of a chip according to an embodiment. In FIG. 1, an integrated circuit (not shown) is formed on a chip 10, and a plurality of bonding pads 12 are provided on the chip 10 outside the integrated circuit. On the chip 10 outside the bonding pad 12, that is, between the bonding pad 12 and the outer edge of the chip 10, a predetermined number of turns of the inductor conductor 14 is formed in a spiral shape, that is, a bonding state. It is formed so as to go around the pad 12.
上述したチップ 1 0の材料としては、 例えば n型シリコン基板やその他の半導 体材料 （例えばゲルマニウムやアモルファスシリコン等の非晶質材料） が用いら れ、 インダク夕導体 1 4の材料としては、 アルミニウムや金等の金属薄膜、 ある いはポリシリコン等の半導体材料が用いられる。 インダクタ導体 1 4は、 マスク. パターンが異なる他は従来の各種の半導体製造手法により形成することができる c なお、 インダク夕導体 1 4は、 チップ 1 0上に形成された集積回路の一部を構 成しており、 インダクタ導体 1 4と集積回路とはボンディンワイヤ等で所定の結 線がなされている。 As a material of the above-described chip 10, for example, an n-type silicon substrate or another semiconductor material (eg, an amorphous material such as germanium or amorphous silicon) is used. A metal thin film such as aluminum or gold, or a semiconductor material such as polysilicon is used. Inductor conductor 1 4 mask. C except that the pattern is different can be formed by semiconductor manufacturing techniques conventional various Incidentally, inductors evening conductor 1 4, a portion of an integrated circuit formed on the chip 1 0 A predetermined connection is made between the inductor conductor 14 and the integrated circuit using a bond wire or the like.
第 2図および第 3図は、 第 1図に示したチップ 1 0をパッケージに収めた状態 を示す図であり、 第 2図は上面図、 第 3図は側面図である。  2 and 3 are views showing a state where the chip 10 shown in FIG. 1 is housed in a package, FIG. 2 is a top view, and FIG. 3 is a side view.
第 2図およ'び第 3図に示すように、 チップ 1 0上のボンディング ·パッド 1 2 とパッケージ内に設けられるパッケージ端子 1 6とはボンディング ·ワイヤ 1 8 により結線される。 ボンディング ' ワイヤ 1 8は一般に、 第 3図に示すように凸 形状に曲げられた状態で取り付けられるため、 ボンディング · ワイヤ 1 8とイン ダク夕導体 1 4とが接触するおそれはない。 したがって、 第 1図のようにボンデ イング ·パッ ド 1 2の外側にィンダク夕導体 1 4を形成した場合であっても、 従 来と同様の手法でボンディングを行うことができる。 As shown in FIGS. 2 and 3, the bonding pads 12 on the chip 10 and the package terminals 16 provided in the package are connected by bonding wires 18. Since the bonding wire 18 is generally attached in a state of being bent into a convex shape as shown in FIG. 3, there is no possibility that the bonding wire 18 and the conductor 14 are in contact with each other. Therefore, as shown in Fig. 1, Even when the conductor 14 is formed outside the inking pad 12, bonding can be performed in the same manner as in the past.
このように、 本実施形態の半導体装置においては、 チップ表面の外縁近傍に渦 巻き形状のィンダク夕導体 1 4を形成するため、 ィンダク夕導体 1 4の直径を長 くすることができ、 十分な大きさのインダク夕ンスを得ることができる。 また、 チップ 1 0上に集積回路を形成する際には、 各種の能動素子や受動素子の配置等 を検討する必要があるが、 本実施形態ではチップ表面の外縁近傍にィンダクタ導 体 1 4を形成するため、 ィンダクタ導体 1 4を形成しても他の集積回路の配置に 影響を与えることがない。 したがって、 インダク夕導体 1 4と他の集積回路との 物理的な干渉等を考慮する必要がなく、 設計および製造工程が簡易化する。 また、 ボンディング ·パッ ド 1 2とパッケージ端子 1 6とは凸形状に曲げられ たボンディング · ワイヤ 1 8によって結線されるため、 ボンディング · ワイヤ 1 8がィンダク夕導体 1 4に接触するおそれがなく、 従来の製造工程をそのまま利 用してボンディングを行える。  As described above, in the semiconductor device of the present embodiment, since the spiral conductor 14 is formed in the vicinity of the outer edge of the chip surface, the diameter of the conductor 14 can be increased. The size of the inductance can be obtained. Further, when forming an integrated circuit on the chip 10, it is necessary to consider the arrangement of various active elements and passive elements, but in the present embodiment, the inductor conductor 14 is placed near the outer edge of the chip surface. Therefore, the formation of the inductor conductor 14 does not affect the arrangement of other integrated circuits. Therefore, there is no need to consider physical interference between the inductor conductor 14 and other integrated circuits, and the design and manufacturing processes are simplified. Also, since the bonding pad 12 and the package terminal 16 are connected by the bonding wire 18 bent in a convex shape, there is no possibility that the bonding wire 18 contacts the conductor 14. Bonding can be performed using the conventional manufacturing process as it is.
なお、 *発明は上記実施形態に限定されるものではなく、 本発明の要旨の範囲 内で種々の変形が可能である。  Note that the invention is not limited to the above embodiment, and various modifications are possible within the scope of the invention.
例えば、 上述した実施形態の半導体装置は、 ボンディング ·パッ ド 1 2とチヅ プ 1 0の外縁との間のチップ 1 0上にィンダク夕導体 1 4を形成したが、 チヅプ 1 0の内層面内にインダクタ導体 1 4を形成することもできる。  For example, in the semiconductor device according to the above-described embodiment, the conductor 14 is formed on the chip 10 between the bonding pad 12 and the outer edge of the chip 10. The inductor conductor 14 can also be formed on the substrate.
第 4図は、 チップ 1 0の内層面内にィンダク夕導体 1 4を形成したチヅプ 1 0 の概略構造を示す図である。 一般に、 ボンディング · パヅド 1 2のそれそれは、 ボンディング ·ワイヤ 1 8を接続するためにある程度の面積を必要とする。 した がって、 第 4図のようにボンディング · パヅ ド 1 2に対向するチップ 1 0の内層 面内にィンダクタ導体 1 4を形成すれば、 チップ表面にィンダク夕導体 1 4を形 成しなくて済み、 その分チップ表面への高密度実装が可能となる。 また、 インダ クタ導体 1 4を形成しても、 チップ面積を増やさずに済むため、 半導体装置を小 型化できる。  FIG. 4 is a view showing a schematic structure of a chip 10 in which an inductor conductor 14 is formed in an inner layer surface of the chip 10. In general, each of the bonding pads 12 requires some area to connect the bonding wires 18. Accordingly, if the inductor conductor 14 is formed in the inner layer surface of the chip 10 facing the bonding pad 12 as shown in FIG. 4, the inductor conductor 14 is formed on the chip surface. It is not necessary to do so, and high-density mounting on the chip surface becomes possible. Also, even if the inductor conductors 14 are formed, the chip area does not need to be increased, so that the semiconductor device can be downsized.
なお、 第 4図では、 ボンディング ·パッド 1 2に対向するチップ 1 0の内層面 内にィンダク夕導体 1 4を形成しているが、 チップ 1 0上の集積回路の形成領域 の外側領域に対向するチップ内層面内であればよく、 例えばボンディング 'パッ ド 1 2と集積回路との間に対向するチップ内層面内にインダク夕導体 1 4を形成 してもよい。 In FIG. 4, the conductor 14 is formed in the inner layer surface of the chip 10 facing the bonding pad 12, but the integrated circuit formation area on the chip 10 is formed. In this case, the conductor 14 may be formed in the chip inner layer surface facing the outer region of the chip, for example, in the chip inner layer surface facing the bonding pad 12 and the integrated circuit.
また、 上述した実施形態では、 ボンディング 'パッド 1 2の外側に 1本のィン ダク夕導体 1 4を形成しているが、 2本以上のィンダクタ導体 1 4を形成しても よい。 この場合には、 複数本のインダク夕導体 1 4を同心状に形成することによ り、 各インダク夕導体 1 4をトランス結合させることができるため、 トランスを 含む回路の全体を集積化することが可能となる。 また、 この場合には複数本のィ ンダク夕導体 1 4を 2層あるいはそれ以上の多層構造としてもよい。  Further, in the above-described embodiment, one inductor conductor 14 is formed outside the bonding pad 12, but two or more inductor conductors 14 may be formed. In this case, by forming the plurality of inductor conductors 14 concentrically, each of the inductor conductors 14 can be transformer-coupled, so that the entire circuit including the transformer can be integrated. Becomes possible. In this case, the plurality of conductors 14 may have a multilayer structure of two or more layers.
また、 2層構造とする場合は、 トランス結合させる場合の他に分布定数型素子 の一部として使用することもできる。 すなわち、 第 5図にインダク夕導体 1 4付 近の部分的な断面構造を示すように、 渦巻き形状に形成された第 1のィンダク夕 導体 1 4と全部あるいは一部が対向するように絶縁層を挟んで第 2のィンダク夕 導体 1 4 aを形成することにより、 2つのインダク夕導体 1 4、 1 4 a間に分布 定数的なキャパシ夕が形成された複合素子を構成することができる。 このような 複合素子の一部を構成するィンダク夕導体 1 4として、 ボンディング ·パッ ド 1 2とチップ 1 0の外縁との間、 あるいはチップ内層面に形成されたィンダク夕導 体 1 4等を用いることもできる。  In the case of a two-layer structure, it can be used as a part of a distributed constant type element in addition to the case of transformer coupling. That is, as shown in FIG. 5, a partial cross-sectional structure around the conductor 14 is shown. The insulating layer is formed so that all or a part of the conductor 14 is opposed to the first conductor 14 formed in a spiral shape. By forming the second inductor conductor 14a with the interposed therebetween, a composite element having a distributed constant capacity formed between the two inductor conductors 14 and 14a can be formed. As the conductor 14 constituting a part of such a composite device, a conductor 14 formed between the bonding pad 12 and the outer edge of the chip 10 or on the inner layer surface of the chip is used. It can also be used.
また、 上述した実施形態は、 インダク夕導体 1 4の全体を複数のボンディング •パッド 1 2とチップ 1 0の外縁との間に形成しているが、 ィンダク夕導体 1 4 の一部をボンディング ·パッド 1 2の内側に形成してもよい。  In the above-described embodiment, the entirety of the inductor conductor 14 is formed between the plurality of bonding pads 12 and the outer edge of the chip 10. It may be formed inside the pad 12.
第 6図は、 インダク夕導体 1 4の一部をボンディング ·パッド 1 2の内側に形 成したチップ 1 0の概略構造を示す図であり、 同図 （A ) はチップ表面の一部の 領域に 1本のインダク夕導体 1 4を配置した例、 同図 （B ) は 2本以上のインダ クタ導体 1 4を平行に配置した例を示す。  FIG. 6 is a diagram showing a schematic structure of the chip 10 in which a part of the inductor conductor 14 is formed inside the bonding pad 12. FIG. 6A shows a partial area of the chip surface. Fig. 2 (B) shows an example in which two or more inductor conductors 14 are arranged in parallel.
同図 （B ) のようにインダク夕導体 1 4を配置すると、 ボンディング ·パヅド 1 2とチップ 1 0の外縁との間の領域を有効利用できるとともに、 磁気的な結合 度合いの少ない複数のインダクタ導体 1 4を形成することができる。  By arranging the inductor conductors 14 as shown in FIG. 13B, the area between the bonding pad 12 and the outer edge of the chip 10 can be effectively used, and a plurality of inductor conductors having a low degree of magnetic coupling are provided. 14 can be formed.
また、 上述した実施形態では、 チヅプ 1 0上のインダク夕導体 1 4を、 チップ 1 0に形成された集積回路の一部を構成するインダク夕として使用する例を説明 したが、 電波を送受信する送受信回路を集積化した場合には、 インダク夕導体 1 4をアンテナコイルとして使用することができる。 また、 インダク夕導体 1 4を 電磁誘導コイルとして使用し、 ィンダク夕導体 1 4の両端に誘導起電力を発生さ せることにより、 チップ 1 0.に形成した集積回路に動作電圧を供給することもで きる。 In the above-described embodiment, the conductor 14 on the chip 10 is connected to the chip The example of using as an inductor constituting a part of the integrated circuit formed in 10 has been described, but when a transmitting and receiving circuit for transmitting and receiving radio waves is integrated, the inductor conductor 14 is used as an antenna coil. be able to. Also, the operating voltage can be supplied to the integrated circuit formed on the chip 10 by using the inductor conductor 14 as an electromagnetic induction coil and generating an induced electromotive force at both ends of the inductor conductor 14. it can.
このように、 インダク夕導体 1 4をアンテナコイルや電磁誘導コイルとして使 用した場合であっても、 例えば第 1図に示すようにィンダク夕導体 1 4をボンデ イング · ワイヤ 1 8とチップ 1 0の外縁との間に形成すれば、 十分な大きさのィ ンダク夕ンスを得ることができる。 産業上の利用可能性  In this way, even when the inductor 14 is used as an antenna coil or an electromagnetic induction coil, for example, as shown in FIG. 1, the inductor 14 is bonded to the bonding wire 18 and the chip 10. If it is formed between the outer edge and the outer edge, a sufficiently large inductance can be obtained. Industrial applicability
本発明は、 チップ表面の外縁に沿って、 具体的にはチップ表面に形成されたパ ッドとチップ外縁との間のチップ表面上、 あるいは集積回路の形成領域の外側領 域に対向するチップの内層面内に周回した導体を形成するため、 導体の全長を長 くすることができ、 チップ上に形成するコイルあるいはインダク夕のィンダク夕 ンスを十分に大きくすることができる。  The present invention relates to a chip that faces along the outer edge of the chip surface, specifically, on the chip surface between the pad formed on the chip surface and the outer edge of the chip, or the outer region of the integrated circuit formation region Since the conductor is formed around the inner layer surface, the overall length of the conductor can be increased, and the inductance of the coil or the inductor formed on the chip can be sufficiently increased.
また、 本発明は、 ボンディング， ワイヤが導体に接触しないようにパッドとパ ッケージ端子とをボンディング ·ワイヤで結線するため、 半導体装置の電気的特 性に影響を与えることなく、 ィンダクタ等として用いられる導体を集積化できる c  Further, the present invention is used as an inductor or the like without affecting the electrical characteristics of the semiconductor device, since the pad and the package terminal are connected by the bonding wire so that the bonding and the wire do not contact the conductor. Conductors can be integrated c

Claims

請 求 の 範 囲 The scope of the claims
1 . 集積回路が形成されたチップ表面の外縁に沿って周回した導体を形成するこ とを特徴とする半導体装置。  1. A semiconductor device characterized in that a conductor is formed around an outer edge of a chip surface on which an integrated circuit is formed.
2 . 集積回路が形成されたチップ表面に設けられた複数のパッドと前記チップの 外縁との間の前記チップ表面上に周回した導体を形成することを特徴とする半導 体装置。  2. A semiconductor device, wherein a conductor circulating on the chip surface is formed between a plurality of pads provided on the chip surface on which an integrated circuit is formed and an outer edge of the chip.
3 . チップ表面上の集積回路の形成領域の外側領域に対向する前記チップの内層 面内に周回した導体を形成することを特徴とする半導体装置。  3. A semiconductor device, wherein a conductor is formed in an inner layer of a chip facing a region outside a formation region of an integrated circuit on a surface of the chip.
4 . 前記チップが実装されるパッケージのパッケージ端子と前記パッドとを、 前 記導体に接触しないようにボンディング · ワイヤにより接続することを特徴とす る請求の範囲第 2項記載の半導体装置。  4. The semiconductor device according to claim 2, wherein a package terminal of a package on which the chip is mounted and the pad are connected by a bonding wire so as not to contact the conductor.
5 . 前記導体は、 前記集積回路の少なくとも一部を構成するインダク夕として用 いられることを特徴とする請求の範囲第 1項に記載の半導体装置。  5. The semiconductor device according to claim 1, wherein the conductor is used as an inductor constituting at least a part of the integrated circuit.
6 . 前記導体は、 前記集積回路の少なくとも一部を構成するインダクタとして用 いられることを特徴とする請求の範囲第 2項に記載の半導体装置。  6. The semiconductor device according to claim 2, wherein the conductor is used as an inductor constituting at least a part of the integrated circuit.
7 . 前記導体は、 前記集積回路の少なくとも一部を構成するインダク夕として用 いられることを特徴とする請求の範囲第 3項に記載の半導体装置。  7. The semiconductor device according to claim 3, wherein the conductor is used as an inductor constituting at least a part of the integrated circuit.
8 . 前記導体は、 前記集積回路に接続されるアンテナコイルとして用いられるこ とを特徴とする請求の範囲第 1項に記載の半導体装置。  8. The semiconductor device according to claim 1, wherein the conductor is used as an antenna coil connected to the integrated circuit.
9 . 前記導体は、 前記集積回路に接続されるアンテナコイルとして用いられるこ とを特徴とする請求の範囲第 2項に記載の半導体装置。  9. The semiconductor device according to claim 2, wherein the conductor is used as an antenna coil connected to the integrated circuit.
1 0 . 前記導体は、 前記集積回路に接続されるアンテナコイルとして用いられる ことを特徴とする請求の範囲第 3項に記載の半導体装置。  10. The semiconductor device according to claim 3, wherein the conductor is used as an antenna coil connected to the integrated circuit.
PCT/JP1996/001444 1995-06-08 1996-05-29 Semiconductor device WO1996042110A1 (en)

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JP2014060416A (en) * 2013-10-29 2014-04-03 Renesas Electronics Corp Semiconductor device
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JP2015164202A (en) * 2015-04-07 2015-09-10 ルネサスエレクトロニクス株式会社 semiconductor device
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Cited By (12)

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EP0862214A1 (en) * 1997-02-28 1998-09-02 TELEFONAKTIEBOLAGET L M ERICSSON (publ) An integrated circuit having a planar inductor
WO1998038679A1 (en) * 1997-02-28 1998-09-03 Telefonaktiebolaget Lm Ericsson (Publ) An integrated circuit having a planar inductor
EP1080492B1 (en) * 1999-03-12 2009-08-19 Robert Bosch Gmbh Device and method for determining the lateral undercut of a structured surface layer
JP2009141011A (en) * 2007-12-04 2009-06-25 Nec Electronics Corp Semiconductor device, method of manufacturing the same, and signal transmitting/receiving method using semiconductor device
US8704334B2 (en) 2007-12-04 2014-04-22 Renesas Electronics Corporation Semiconductor device, method of manufacturing the same, and signal transmitting/receiving method using the semiconductor device
US9685496B2 (en) 2007-12-04 2017-06-20 Renesas Electronics Corporation Semiconductor device, method of manufacturing the same, and signal transmitting/receiving method using the semiconductor device
US10115783B2 (en) 2007-12-04 2018-10-30 Renesas Electronics Corporation Semiconductor device, method of manufacturing the same, and signal transmitting/receiving method using the semiconductor device
US9922926B2 (en) 2009-03-13 2018-03-20 Renesas Electronics Corporation Semiconductor device for transmitting electrical signals between two circuits
JP2014086593A (en) * 2012-10-24 2014-05-12 Renesas Electronics Corp Semiconductor device
JP2014060416A (en) * 2013-10-29 2014-04-03 Renesas Electronics Corp Semiconductor device
JP2014064015A (en) * 2013-11-06 2014-04-10 Renesas Electronics Corp Semiconductor device
JP2015164202A (en) * 2015-04-07 2015-09-10 ルネサスエレクトロニクス株式会社 semiconductor device

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