JP4592542B2 - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which performs radio communications in a noncontact manner, and is capable of improving receiving signal strength more than usual. <P>SOLUTION: When a receiving current flows through an antenna 3, an eddy current is about to flow through a silicon substrate in a direction to produce a reverse magnetic field so as to cancel a magnetic flux produced by the antenna 3, that is, an eddy current flows in a direction opposite to the direction in which the antenna 3 is wound. Two or more electrodes 5A are arranged in a direction to cross the antenna 3 at right angles, so that a current path is blocked that the eddy current flows through. Therefore, the eddy current hardly flows through the electrodes 5A. An electrode 5B is provided so as to connect the electrodes 5A and a terminal 22 together, but a cut is provided to the electrode 5B so as to prevent the eddy current from flowing through the electrode 5B, too. Therefore, the eddy current is suppressed, and the loss of the antenna 3 can be reduced. By this setup, the Q value of the antenna 3 can be improved. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device capable of wireless communication between a plurality of semiconductor chips by using electromagnetic coupling (inductive coupling).

  As miniaturization technology advances in a complementary metal oxide semiconductor (CMOS) process, the operation speed and high-frequency characteristics of transistors formed on a silicon substrate are improved. In recent years, high-speed logic circuits and high-frequency circuits manufactured by a CMOS process have been realized.

  Further, a large-scale integrated circuit (VLSI) is realized in a system on chip (SOC) in which a logic circuit, a memory, a high-frequency / analog circuit, etc. are mixedly mounted on one semiconductor chip. . However, in such an integrated circuit, a plurality of circuits having different functions are formed in one semiconductor chip. Therefore, there is a problem that a small-scale design change is difficult. In addition, there is a problem that the yield is likely to be reduced as compared with the manufacture of a semiconductor device having a single function.

  As another means for realizing a semiconductor device having a high function, there is a method in which a plurality of circuits having different functions are respectively formed on a plurality of semiconductor substrates, and the plurality of semiconductor devices are mounted on one package. A package in which such a plurality of semiconductor devices are mounted is called a system in package (SIP). In recent years, it is required to reduce the area of the package while accommodating more semiconductor devices in the package. For this reason, a method of stacking a plurality of chips in the height direction has been developed. In addition, a package (3D-Multi Chip Package: MCP) for stacking chips has been developed.

  Wires, package pins, wiring on a printed circuit board, and the like are used for power supply to individual semiconductor devices and signal transmission between semiconductor devices. Therefore, a delay in signal transmission occurs due to the resistance and parasitic capacitance of these wirings. In particular, when the signal is transmitted at high speed or when the signal frequency is high, not only the capacitance of these wirings but also the influence of the inductance becomes noticeable. Furthermore, ESD (Electrostatic Discharge) measures are indispensable for pads connected to signal lines.

  In order to avoid such a problem, a method of forming an antenna in a semiconductor device has been proposed. According to this method, signal transmission between chips can be performed in a non-contact manner by using electromagnetic waves (for example, Non-Patent Document 1 and Non-Patent Document 2).

  Japanese Patent Laid-Open No. 2002-157559 (Patent Document 1) discloses a non-contact communication type information medium. In this information medium, the main surfaces of the two semiconductor devices face each other. In addition, antenna coils manufactured on these semiconductor devices are arranged insulated. Data communication is performed by electromagnetic coupling of the antenna coil.

  Further, FIG. 3 of Non-Patent Document 1 shows a simulation result that a high coupling coefficient can be obtained by reducing the distance between the inductors when the main surfaces of two semiconductor devices are opposed to each other. This result is the same as that disclosed in JP-A-2002-157559 (Patent Document 1).

FIG. 4 of Non-Patent Document 2 shows a circuit including an amplifier that amplifies a signal received by electromagnetic coupling between inductors.
JP2002-157559 (2nd page, [0010]) Mamoru Sasaki, 2 others, “Chip-to-chip wireless interconnect using resonance characteristics between spiral inductors”, [online], June 2004, Hiroshima University 21st Century COE Program, Terabit Information Nanoelectronics 1st Report 4 -I-2, [Search August 12, 2005], Internet <URL: http://www.rcis.hiroshima-u.ac.jp/21coe/J/4result/result2-1.html> D. Mizoguchi, Y .; B. Yusof, N .; Miura, T .; Sakurai, T .; Kuroda, “A 1.2 Gb / s / pin Wireless Superconnect Based on Inductive Inter-Chip Signaling (IIS),” ISSCC Dig. Tech. Papers, pp. 142-143, Feb. 2004.

  As described in Japanese Patent Application Laid-Open No. 2002-157559 (Patent Document 1) and Non-Patent Document 1, wireless communication is performed without contacting two semiconductor devices so that the main surfaces of the two semiconductor devices face each other. Two semiconductor devices are arranged. An antenna is formed on the surface of each semiconductor device. Two antennas are arranged so that the antennas are insulated from each other. By configuring the semiconductor device and the antenna in this way, signals can be transmitted using the electromagnetic coupling of the antenna.

  However, when a signal is applied to the coiled antenna, a magnetic flux is generated by a current flowing through the antenna. Magnetic flux is generated both above and below the antenna. Since no conductive material exists between the two semiconductor devices, no eddy current flows. On the other hand, if the two semiconductor devices are both semiconductor devices fabricated on a silicon substrate by a CMOS process, an eddy current flows in the silicon substrate. Loss of the inductor (antenna) occurs due to the eddy current. As a result of the loss, the Q factor (Quality Factor) of the antenna decreases, and the strength of the received signal decreases.

  Further, when an eddy current flows in the silicon substrate, a magnetic flux (demagnetizing field) opposite to the magnetic flux generated by the antenna is generated. The demagnetizing field reduces the mutual inductance between the two antennas. As the mutual inductance decreases, the received signal strength decreases.

  As described above, when the eddy current is generated, the strength of the received signal is reduced, and thus a communication error may occur. However, a method for suppressing the generation of eddy current has not been proposed in the prior art.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to make it possible to improve the strength of a received signal in a semiconductor device that performs wireless communication without contact. is there.

  In summary, the present invention is a semiconductor device comprising first and second semiconductor chips capable of wireless communication with each other. The first and second semiconductor chips are arranged so that their main surfaces face each other. Each of the first and second semiconductor chips includes a semiconductor substrate, an insulating film, an antenna, a plurality of first electrodes, and a plurality of second electrodes. A communication circuit is formed on the semiconductor substrate. The insulating film is formed on the semiconductor substrate. The antenna is formed in the insulating film so as to be wound on the main surface. The antenna has first and second terminals. The plurality of first electrodes are formed in the insulating film between the antenna and the semiconductor substrate, and are disposed so as to be orthogonal to the winding direction of the antenna when viewed from a direction perpendicular to the main surface. Each of the plurality of first electrodes is electrically connected to the first terminal. The plurality of second electrodes are formed on the main surface of the semiconductor substrate or between the semiconductor substrate and the plurality of first electrodes, and when viewed from a direction perpendicular to the main surface, Each overlaps. Each of the plurality of second electrodes is electrically connected to the second terminal.

  According to the semiconductor device of the present invention, when performing wireless communication without contact, the strength of the received signal can be improved as compared with the prior art.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

[Embodiment 1]
FIG. 1 is a cross-sectional view for explaining the semiconductor device of the first embodiment.

  With reference to FIG. 1, a semiconductor device 100 includes semiconductor chips 1, 2, a substrate 16, and a package 17.

  Each of the semiconductor chips 1 and 2 has a circuit (not shown) that realizes a communication function. The semiconductor chip 1 is attached to the substrate 16 of the package 17. The semiconductor chip 2 is stacked on the semiconductor chip 1. The semiconductor chips 1 and 2 are housed in a package 17.

  The semiconductor chip 1 is manufactured by, for example, a CMOS process. The semiconductor chip 1 includes an antenna 3, an upper electrode 5, a lower electrode 7, a silicon substrate 9, and an insulating film 11.

  The antenna 3 is provided on the metal wiring layer. This metal wiring layer is present in the insulating film 11. Insulating film 11 is formed on the main surface of silicon substrate 9. The antenna 3 is an antenna coil formed in a coil shape by winding a conductive wire once or a plurality of times. The antenna 3 is formed in the insulating film 11 so as to spiral along the main surface of the silicon substrate 9. The antenna 3 has first and second terminals.

  Upper electrode 5 is provided between antenna 3 and the main surface of silicon substrate 9. The material of the upper electrode 5 is polysilicon, but may be metal. A lower electrode 7 is formed immediately below the upper electrode 5. The lower electrode 7 is a diffusion layer formed on the main surface of the silicon substrate 9. For example, the conductivity type of this diffusion layer is N-type, and the conductivity type of silicon substrate 9 is P-type.

  The semiconductor chip 2 has the same configuration as the semiconductor chip 1. The semiconductor chip 2 includes an antenna 4, an upper electrode 6, a lower electrode 8, a silicon substrate 10, and an insulating film 12. The antenna 4 is provided on the metal wiring layer in the insulating film 12 in the same manner as the antenna 3.

  Although not shown in FIG. 1, the semiconductor chips 1 and 2 include circuits for processing transmitted or received signals such as logic circuits and analog circuits in addition to the communication function.

  The main surface of the semiconductor chip 1 and the main surface of the semiconductor chip 2 face each other. Further, the semiconductor chip 1 and the semiconductor chip 2 are electrically insulated. For this reason, the space between the semiconductor chip 1 and the semiconductor chip 2 is hollow. However, an insulating film may be provided between the semiconductor chip 1 and the semiconductor chip 2.

  For signal transmission from the semiconductor chip 1 to the semiconductor chip 2, a current flows through the antenna 3 when a signal is sent to the antenna 3. Since the antenna 3 is formed in a spiral shape, a magnetic field is generated in the vicinity of the antenna 3 when a current flows. If there is a conductor above the antenna 3, an eddy current flows through the conductor. The direction in which the eddy current flows is a direction in which a demagnetizing field that cancels the magnetic field generated in the antenna 3 is generated. However, there is no conductive material between the antenna 3 and the antenna 4. Therefore, no eddy current is generated in the space between the antenna 3 and the antenna 4.

  Power is supplied to the semiconductor chip 1 from the outside via a power supply terminal (not shown) of the package 17. Further, the semiconductor chip 1 transmits a signal to the outside through a signal terminal (not shown). On the other hand, power is supplied to the semiconductor chip 2 from the semiconductor chip 1 through the pads 13 and 14 and the ball bonder 15 connecting the pad 13 and the pad 14.

  Signal transmission from the semiconductor chip 1 to the semiconductor chip 2 is performed wirelessly and contactlessly using each communication function. A signal processed by the semiconductor chip 2 is wirelessly transmitted from the semiconductor chip 2 to the semiconductor chip 1 in a non-contact manner. There are no wires for transmitting signals between the semiconductor chip 1 and the semiconductor chip 2 or wiring on the printed circuit board. Therefore, variations in signal transmission speed due to wiring resistance and parasitic capacitance can be suppressed, and stable signal transmission is possible.

FIG. 2 is a perspective view for explaining the antennas 3 and 4 of FIG.
With reference to FIG. 2, an antenna 3 and a silicon substrate 9 of the semiconductor chip 1 are shown. Also shown are the antenna 4 and the silicon substrate 10 of the semiconductor chip 2. As described above, the antenna 3 is provided on the metal wiring layer. When the number of turns of the antenna exceeds 1, each metal wiring layer is connected by the lead wire 18 and the via plug 20 formed in the metal wiring layer below the antenna 3. This forms an antenna loop.

  Since antenna 4 has the same configuration as antenna 3, detailed description will not be repeated hereinafter. When the number of coil turns in the antenna 4 exceeds 1, each metal wiring layer is connected by the lead wire 19 and the via plug 21 formed in the lower metal wiring layer.

  The main surface of the semiconductor chip 1 and the main surface of the semiconductor chip 2 face each other. Therefore, the antenna 3 and the antenna 4 are also opposed. When a current flows through the antenna 3 according to the transmission signal, a magnetic flux is generated by the current. Since the magnetic flux penetrates the antenna 4, an induced current flows through the antenna 4. The direction of the induced current is a direction in which a magnetic flux opposite to the magnetic flux generated by the antenna 3 is generated. The induced current flowing through the antenna 4 becomes a received signal.

  Each of the antennas 3 and 4 has a quadrangular shape. The radius of the antenna 4 of the semiconductor chip 2 is equal to the radius of the antenna 3 of the semiconductor chip 1. Further, the winding direction of the antenna 4 is formed to be opposite to the winding direction of the antenna 3. For this reason, when the antenna 3 and the antenna 4 are opposed to each other when viewed along the positive to negative direction of the Z axis, the antenna 3 and the antenna 4 overlap each other.

  The four sides of the antenna 4 corresponding to the four sides of the antenna 3 face each other at the shortest distance (the distance between the antenna 3 and the antenna 4). As a result, a current path having the same shape as the current path of the antenna 3 exists in the antenna 4, and the distance between these current paths is the shortest. For example, the side 3 </ b> A of the antenna 3 corresponds to the side 4 </ b> A of the antenna 4. Side 3A and side 4A face each other at the shortest distance. Further, the side 4B of the antenna 4 corresponds to the side 3B of the antenna 3. Side 3B and side 4B face each other at the shortest distance. Therefore, the electromagnetic coupling between the antenna 3 and the antenna 4 becomes strong. Further, since the current path exists at the shortest distance, the capacity between the antennas can be increased. The shape of the antennas 3 and 4 is not limited to a quadrangle, and may be a circular spiral.

  The stronger the electromagnetic coupling, the greater the induced current flowing through the antenna 4. By reversing the winding directions of the antennas 3 and 4, the strength of the received signal can be increased when wireless communication is performed with the antennas 3 and 4 facing each other. In addition, when the winding direction of the antenna 4 is the same as the winding direction of the antenna 3, when the antenna 3 and the antenna 4 are opposed to each other, the electromagnetic coupling is weakened. The reason is that the distance between a certain side of the antenna 3 and the side of the antenna 4 corresponding to the side is not shortest.

  The distance between the semiconductor chip 1 and the semiconductor chip 2 is determined only by the thickness of the ball bonder 15. The thickness of the ball bonder 15 is, for example, about 20 to 30 μm. Therefore, the antenna 3 and the antenna 4 can be arranged close to each other. Preferably, the distance between the antenna 3 and the antenna 4 is equal to or less than the radius of each of the antenna 3 and the antenna 4. By setting the distance between the antenna 3 and the antenna 4 to be equal to or less than the radius of each of the antenna 3 and the antenna 4, the coupling coefficient of the antenna 3 and the antenna 4 becomes 0.1 or more. If the value of the coupling coefficient is 0.1 or more, the strength (voltage magnitude) of the received signal can be set to a strength (for example, about several hundred mV) that causes no practical problem.

FIG. 3 is a diagram for explaining the relationship between the distance between the antennas 3 and 4 and the coupling coefficient.
With reference to FIG. 3, the change of the coupling coefficient with respect to the distance of the antennas 3 and 4 when the radius of the antennas 3 and 4 is 100 μm is shown. As described above, it is preferable that the coupling coefficient of the antenna 3 and the antenna 4 is 0.1 or more from the viewpoint of the strength of the received signal. When the distance between the antennas is 190 μm, the coupling coefficient is 0.1.

  As shown in FIG. 3, the coupling coefficient increases as the distance between the antennas decreases. When the distance between the antennas is equal to the radius of the antenna, that is, at 100 μm, the coupling coefficient is 0.35. In consideration of assembly accuracy and design margin, a coupling coefficient of 0.1 or more can be ensured if the distance between the antennas is equal to or less than the radius of the antenna. Since the electromagnetic coupling becomes stronger as the coupling coefficient is larger, the strength of the received signal becomes stronger. Therefore, as long as the antenna 3 and the antenna 4 do not contact, the distance between antennas is so good that it is short.

FIG. 4 is a perspective view of the antenna 3 of FIG.
FIG. 5 is a plan view for explaining the upper electrode 5 and the lower electrode 7 of FIG.

  4 and 5, the distance from the point P1 located at the center of the antenna 3 to the line width center of the outermost line is 100 μm. This distance corresponds to the “radius of the antenna” in the present invention. The line width of the antenna 3 is 10 μm, and the line interval is 2 μm. The number of turns of the antenna 3 is two.

  The main body of the antenna 3 is provided on the uppermost metal wiring layer. The greater the distance between the main body of the antenna 3 and the silicon substrate 9, the weaker the magnetic field strength in the silicon substrate 9. Therefore, eddy current is less likely to occur in the silicon substrate 9 when a current flows through the antenna 3. Thereby, the loss of the antenna 3 is reduced. Therefore, the Q value of the antenna 3 is improved.

  Further, the lead line 18 is provided in a metal wiring layer one layer lower than the uppermost metal wiring layer. Increasing the distance between the surface of the silicon substrate 9 and the lead wire 18 can also suppress the generation of eddy currents in the silicon substrate 9.

  An upper electrode 5 is formed immediately below the antenna 3. The upper electrode 5 includes a plurality of electrodes 5A and an electrode 5B. The material of the plurality of electrodes 5A and 5B is polysilicon. Each of the plurality of electrodes 5A has a strip shape. Each of the plurality of electrodes 5A is orthogonal to any one of the four sides of the antenna 3.

  An electrode 5B is provided so as to surround the plurality of electrodes 5A. The diameter of the electrode 5B is larger than the diameter of the antenna 3. Furthermore, the electrode 5B is provided with a cut at at least one location.

  The antenna 3 has a terminal 22. The upper electrode 5 is connected to the terminal 22 via the via plug 24. Therefore, each of the plurality of electrodes 5A is connected to the terminal 22 via the electrode 5B.

  A lower electrode 7, that is, a diffusion layer is formed in a region immediately below the upper electrode 5 on the main surface of the silicon substrate 9. The lower electrode 7 includes a plurality of electrodes 7A and an electrode 7B. The plurality of electrodes 7A overlap with the plurality of electrodes 5A when viewed from a direction perpendicular to the main surface of the silicon substrate 9 (a direction perpendicular to the paper surface). The electrode 7B is provided so as to surround the plurality of electrodes 7A, and is provided with a cut at least at one place. The lower electrode 7 is connected to another terminal 23 of the antenna 3 by a via plug 25.

  When a reception current flows through the antenna 3, an eddy current tends to flow in the silicon substrate in a direction that generates a demagnetizing field that cancels the magnetic flux generated by the antenna 3, that is, in a direction opposite to the winding direction of the antenna 3. Since the plurality of electrodes 5A are arranged in a direction orthogonal to the antenna 3, the current path through which the eddy current flows is cut off. For this reason, an eddy current hardly occurs in the plurality of electrodes 5A. An electrode 5B is provided to connect the plurality of electrodes 5A and the terminal 22. The electrode 5B is cut so that eddy current does not flow to the electrode 5B. Therefore, it is possible to suppress the generation of eddy current in the upper electrode 5 when a current flows through the antenna 3. As a result, the loss of the antenna 3 is reduced, so that the Q value of the antenna 3 is improved.

  The lower electrode 7 has the same shape as the upper electrode 5. Also in the lower electrode 7, eddy current is suppressed by the same action as the upper electrode 5. Therefore, it is possible to suppress the generation of eddy current in the lower electrode 7, that is, the silicon substrate 9.

The reason why the Q value of the antenna is improved will be described in more detail.
In the absence of the upper and lower electrodes, an eddy current is generated in the silicon substrate in a direction that cancels the magnetic field generated by the current flowing through the antenna. This causes a loss in the substrate, and the Q value of the antenna is lowered. In the first place, since the silicon substrate has conductivity, a conduction current flows in the substrate. For example, if the substrate is a gallium arsenide (GaAs) substrate, the conductivity is very small. Therefore, almost no eddy current is generated in the substrate, and the Q value does not decrease.

  Therefore, when a case where a rectangular metal plate is inserted between the antenna and the silicon substrate is considered, eddy current generated by the current flowing through the antenna flows in the metal plate. Loss is caused by the current flowing in the metal plate, and the Q value is lowered. However, the influence of the silicon substrate (parasitic capacitance and parasitic resistance) is not visible due to the metal plate. In other words, the antenna has no silicon substrate, and only the relationship with the metal plate needs to be noted.

  Next, consider a case where a strip-shaped metal plate orthogonal to each side of the antenna is inserted between the antenna and the silicon substrate (a state close to this embodiment). At this time, an eddy current tends to flow through the metal plate. However, since the metal plate is disposed orthogonal to the antenna, no eddy current actually occurs. Since the silicon substrate can be seen from the gap between the strip-shaped metal plates, the influence of the silicon substrate cannot be completely prevented, but the influence of the silicon substrate can be reduced. As a result, a decrease in the Q value can be suppressed.

  Therefore, even if the lower electrode is not in the silicon substrate, if the upper electrode and the lower electrode have a strip shape and are arranged orthogonal to the antenna, eddy currents that flow through the silicon substrate can be suppressed. Although a large suppression effect is obtained by the upper electrode, the suppression effect is further increased by the lower electrode provided on the silicon substrate.

  In addition, if a cut is formed in at least one of the electrodes 5B and 7B, eddy current can be suppressed, but it is preferable that a cut is formed in both the electrodes 5B and 7B. Further, for example, when a cut is formed at two locations on the electrode 5B, it is preferable that a cut is formed in the middle of the side farthest from the terminals 22 and 23 and in the middle of the side closest to the terminals 22 and 23. Moreover, when a cut is formed in four places of the electrode 5B, it is preferable that a cut is formed in the middle of each side of the electrode 5B. Thereby, the influence of the magnetic field generated by the antenna 3 in each region of the electrode divided by the cut can be made almost equal.

FIG. 6 is a cross-sectional view taken along the line VI-VI in FIG.
Referring to FIG. 6, a capacitive element 27 is configured by the upper electrode 5, the oxide film 26 formed immediately below the upper electrode 5, and the lower electrode 7 that is a diffusion layer. Oxide film 26 is an oxide film formed by the same manufacturing process as the gate oxide film of a MOS transistor, for example.

  The structure of the capacitive element included in the semiconductor chip 2 is the same as the structure of the capacitive element included in the semiconductor chip 1. That is, the configuration of the upper electrode 6 is the same as the configuration of the upper electrode 5 shown in FIG. The configuration of the lower electrode 8 is the same as that of the lower electrode 7 shown in FIG. Therefore, when a reception current flows through the antenna 4, the generation of eddy current can be suppressed in the upper electrode 6 and the lower electrode 8 (silicon substrate 10).

  The antenna 4 is formed on the uppermost metal wiring layer in the semiconductor chip 2. Similarly to the semiconductor chip 1, the generation of eddy currents in the silicon substrate can be suppressed by increasing the distance between the antenna 4 and the silicon substrate 10.

  Next, signal transmission from the semiconductor chip 1 to the semiconductor chip 2 will be described. In the signal transmission from the semiconductor chip 2 to the semiconductor chip 1, the following operation is performed.

FIG. 7 is an equivalent circuit diagram of the signal transmission circuit of the semiconductor device 100 of FIG.
Referring to FIG. 7, the communication circuit (transmission circuit SND) formed on silicon substrate 9 outputs signal S1. At this time, a current corresponding to the signal S1 flows through the antenna 3 on the transmission side. When a current flows through the antenna 3, magnetic flux is generated on both sides of the antenna 3 on the silicon substrate 9 side and on the antenna 4 side of the antenna 3.

  An eddy current tends to be generated in the upper electrode 5 and the silicon substrate 9 by the magnetic flux generated on the silicon substrate 9 side. However, the generation of eddy current is suppressed by the upper electrode 5 and the lower electrode 7 having the configuration shown in FIG. On the other hand, since the magnetic flux passes through the antenna 4, a current that cancels the magnetic flux flows through the antenna 4. That is, an induction current is generated in the antenna 4 due to electromagnetic coupling between the antenna 3 and the antenna 4.

  In FIG. 7, the inductor 29 indicates the inductor component of the antenna 3. Inductor 30 represents the inductor component of antenna 4. The magnitude of the current flowing through the antenna 4 is determined by the mutual inductance between the inductor 29 and the inductor 30. In other words, the magnitude of the received current is determined by the coupling coefficient between the inductor 29 and the inductor 30.

  For example, assume that the radius of the antenna is 100 μm and the distance between the antennas is 50 μm. As shown in FIG. 3, since the distance between the antennas is smaller than the radius of the antenna, the magnitude of the coupling coefficient is 0.1 or more. Magnetic flux is generated below the antenna 4 (on the antenna 3 side) by the current flowing through the antenna 4.

  At this time, an eddy current tends to be generated in the upper electrode 6 and the silicon substrate 10 by the magnetic flux generated on the silicon substrate 10 side. However, an upper electrode 6 and a lower electrode 8 having the same configuration as that shown in FIG. Therefore, no eddy current occurs in the upper electrode 6 and the lower electrode 8 (that is, the silicon substrate 10). As a result, the loss of the inductor 30 is reduced, so that the Q value of the antenna 4 is improved.

  The current flowing through the antenna 4 corresponds to the received signal. The current flowing through the antenna 4 by the load resistor 33 is converted into a voltage. The capacitive element 32 is connected to both terminals of the antenna 4. The capacitive element 32 is disposed immediately below the antenna 4. Capacitance element 32 includes upper electrode 6 and lower electrode 8. A voltage between the terminals of the capacitive element 32 (reception voltage u2) is expressed by Expression (1).

  Here, L1 and L2 are the self-inductances of the inductors 29 and 30, respectively. k is a coupling coefficient between the antenna 3 and the antenna 4. i1 is a value of a current (transmission current) flowing through the antenna 3 by the signal S1. R2 is the resistance value of the resistance component (resistor 31) of the antenna 4. RL is the resistance value of the load resistor 33. C2 is a capacitance value of the capacitive element 32. Ω is the angular frequency of the transmission current.

  Further, by connecting the capacitive element 32 to the antenna 4, the reception voltage can be made higher than when the capacitive element 32 is not provided.

FIG. 8 is a diagram showing the frequency dependence of the reception voltage u2 shown in FIG.
Referring to FIG. 8, the horizontal axis represents the frequency of the reception signal, and the vertical axis represents the reception voltage u2. The radii of the antenna 3 and the antenna 4 are both 100 μm, and the distance between the antennas is 50 μm. The number of turns of the antenna 3 and the antenna 4 is two. The magnitude of the transmission current flowing through the antenna 3 is 1 mA. The resistance value of the load resistor 33 is 2 kΩ.

  A curve A1 indicated by a solid line in FIG. 8 indicates the frequency dependence of the reception voltage u2 when the capacitive element 32 is connected to the antenna 4. For comparison, the frequency dependence of the reception voltage u2 when the capacitor 32 is not provided is indicated by a broken line A2.

  Resonance is generated by the inductor 30 and the capacitive element 32. In the first embodiment, the resonance frequency is about 900 MHz. As shown in FIG. 7, the reception voltage becomes maximum at around 900 MHz.

  As described above, in the first embodiment, the SN ratio (Signal to Noise Ratio) of the received signal can be improved by providing the capacitive element connected between the two terminals of the antenna immediately below the antenna 4. An amplifier is connected to the subsequent stage of the antenna 4. By increasing the reception voltage, the load on the amplifier can be reduced. Since the gain of the amplifier may be small, distortion is reduced. Therefore, communication errors are less likely to occur.

  Even if the intensity of the transmission signal is small, the amplitude of the signal can be increased by using resonance on the reception side. Therefore, transmission power can be reduced. Thereby, the power consumption of the whole semiconductor device can be reduced.

  The capacitive element 32 is an element having a large area like the antenna 4. Therefore, when the antenna 4 and the capacitive element 32 are arranged side by side, the area of the semiconductor chip 2 increases. The size of the antenna is substantially determined by the frequency band for performing wireless communication and the size of the coupling coefficient. Due to such restrictions, it is very difficult to make the antenna small.

  In the first embodiment, a capacitive element is arranged immediately below the antenna. This can prevent an increase in the area of the semiconductor chip. Therefore, the area of the entire semiconductor device 100 can be reduced.

  In the above description, the material of the semiconductor substrate is silicon, but the material of the semiconductor substrate is not limited to silicon and may be other materials (for example, gallium arsenide).

  As described above, according to the first embodiment, the capacitive element is arranged immediately below the antenna (on the semiconductor substrate side). The upper electrode and the lower electrode of the capacitive element include a plurality of strip electrodes arranged so as to be orthogonal to the winding direction of the antenna. The upper electrode and the lower electrode both include electrodes that surround a plurality of strip-shaped electrodes and are partially cut. As a result, the generation of eddy current can be suppressed when a current flows through the antenna.

  In particular, in the first embodiment, since the lower electrode is formed on the silicon substrate, the generation of eddy currents in the silicon substrate can be suppressed. As a result, the Q value of the antenna can be improved, so that the strength of the received signal can be improved.

  Further, according to the first embodiment, the distance between the antenna and the silicon substrate is increased by forming the antenna in the uppermost metal wiring layer among the multilayer metal wiring layers. As a result, the generation of eddy currents in the silicon substrate can be suppressed when a current flows through the antenna.

[Embodiment 2]
FIG. 9 is a cross-sectional view for explaining the semiconductor device of the second embodiment.

  Referring to FIG. 9, semiconductor device 100A has the same configuration as semiconductor device 100 of FIG. However, the semiconductor device 100 </ b> A differs from the semiconductor device 100 in the configuration of the capacitive elements of the semiconductor chips 1 and 2. Since the configuration of other parts of semiconductor device 100A is similar to that of semiconductor device 100, the following description will not be repeated.

  In the second embodiment, the lower electrode 7 is provided inside the insulating film 11. Similarly, in the semiconductor chip 2, the lower electrode 8 is provided inside the insulating film 12. In the first embodiment, the lower electrodes 7 and 8 are both constituted by diffusion layers. In this respect, the second embodiment is different from the first embodiment.

FIG. 10 is a cross-sectional view illustrating the configuration of the capacitive element of the semiconductor chip 1.
Referring to FIG. 10, an insulating film 34 is formed on the silicon substrate 9. The insulating film 34 is a field oxide film used for circuit element isolation, for example. The insulating film 34 may be formed on the surface of the silicon substrate 9 by chemical vapor deposition. The insulating film 34 may be a silicon nitride film, for example.

  A lower electrode 7 is formed on the insulating film 34. A dielectric film 36 is formed on the lower electrode 7. Dielectric film 36 is, for example, an oxide film. An upper electrode 5 is formed on the dielectric film 36. As in the first embodiment, the material of the upper electrode 5 and the lower electrode 7 is, for example, polysilicon. The upper electrode 5, the dielectric film 36, and the lower electrode 7 constitute a capacitive element.

  The capacitive element of the semiconductor chip 2 has the same configuration as the capacitive element shown in FIG. When the silicon substrate 9, the upper electrode 5, and the lower electrode 7 are replaced with the silicon substrate 10, the upper electrode 6, and the lower electrode 8 in the capacitive element shown in FIG. 9, the capacitive element of the semiconductor chip 2 is obtained. Therefore, the description of the configuration of the capacitive element of the semiconductor chip 2 will not be repeated hereinafter.

  In the first embodiment, a diffusion layer (N-type well) is used as the lower electrode 7. When a reverse bias voltage is applied between the diffusion layer and the silicon substrate, a leakage current may flow from the diffusion layer toward the silicon substrate. Since a loss occurs due to the leakage current flowing, the Q value of the capacitance decreases. In the second embodiment, since the lower electrode 7 is formed on the insulating film 34, the leakage current from the lower electrode 7 can be reduced. Therefore, the Q value of the capacity can be increased. As a result, a reception voltage having a steep peak at the resonance frequency can be obtained.

  Although the lower electrode 7 is not formed on the silicon substrate 9, since the upper electrode 5 and the lower electrode 7 exist between the antenna 3 and the silicon substrate 9, most of the silicon substrate 9 is shielded from the antenna 3. ing. Therefore, the influence of the silicon substrate 9 and the parasitic resistance is reduced by the same action as in the first embodiment. As a result, even if the lower electrode 7 is not formed on the silicon substrate 9, the eddy current in the silicon substrate 9 can be suppressed.

FIG. 11 is a plan view for explaining the capacitor in the second embodiment in more detail.
Referring to FIG. 11, the configuration of upper electrode 5 is the same as that of the first embodiment. A lower electrode 7 is present immediately below the upper electrode 5 with a dielectric film 36 (not shown) interposed therebetween. The lower electrode 7 has a region larger than the diameter of the antenna 3. The lower electrode 7 includes a plurality of electrodes 7A and electrodes 7B. The plurality of electrodes 7A are partially cut and connected by an electrode 7B surrounding the plurality of electrodes 7A. The lower electrode 7 is connected to the terminal 23 of the antenna 3 through the via plug 25. On the other hand, the upper electrode 5 is connected to the terminal 22 of the antenna 3 through the via plug 24.

  Further, a plurality of switches 37 are provided corresponding to the plurality of electrodes 5A, respectively. The plurality of switches 37 are, for example, MOS transistors formed on the silicon substrate 9. Each of the plurality of electrodes 5A is connected to the terminal 22 by a corresponding switch 37. Each of the plurality of switches 37 is controlled by a control circuit CTL formed on the silicon substrate 9. The control circuit CTL turns each of the plurality of switches 37 on and off so that the voltage generated across the load resistor 33A connected to the antenna is maximized. In order to prevent the figure from becoming complicated, FIG. 11 shows two switches 37 respectively connected to the two electrodes 5A.

  Similar to the first embodiment, in the second embodiment, strip-shaped electrodes that are orthogonal to the winding direction of the antenna are arranged directly below the antenna. This suppresses the generation of eddy currents in both the upper electrode and the lower electrode. Therefore, the Q value can be increased by reducing the loss of the antenna. Further, by using resonance due to the inductance and capacitance of the antenna, a high reception voltage can be obtained as in the first embodiment.

  In the above description, the material of the upper electrode and the lower electrode constituting the capacitive element is assumed to be polysilicon. However, the upper electrode and the lower electrode may be provided in different metal wiring layers. In this case, a capacitor similar to the structure shown in FIG. 11 can be formed. That is, in the second embodiment, as a capacitive element, an MIM (Metal-Insulator-Metal) capacitor in which an upper electrode and a lower electrode are made of a metal wiring layer, or an MIS (Metal-Insulator-Silicon made of only an upper electrode in a metal wiring layer) ) The capacity can be selected.

  A capacitor using an insulating film between wiring layers, such as an MIM capacitor or an MIS capacitor, has a smaller leakage current than a capacitor using a diffusion layer such as an N-type well as an electrode. Therefore, energy loss is also reduced. As a result, the Q value of the antenna is increased, so that a reception voltage having a steep peak at the resonance frequency can be obtained. Therefore, the strength of the received signal can be increased, and communication errors can be prevented.

  In the second embodiment, the control circuit CTL can change the capacitance value between the two terminals of the antenna by turning on or off each of the plurality of switches 37. Therefore, it becomes possible to adjust the resonance frequency. In addition, since the fine adjustment for matching the impedance between the antennas is possible, the reception sensitivity is increased. As a result, communication errors are less likely to occur.

  Even if the lower electrode is formed of a diffusion layer as in the first embodiment, the capacitance value can be adjusted if the upper electrode is the same as the upper electrode 5 shown in FIG. In this case, since the lower electrode is formed in the diffusion layer, the effect of suppressing the eddy current flowing in the silicon substrate is increased as compared with the case of only the upper electrode.

  As described above, according to the second embodiment, the insulating film is formed on the surface of the semiconductor substrate, and the capacitive element is formed on the insulating film. As a result, a received signal having a higher intensity at the resonance frequency can be obtained. Further, according to the second embodiment, the resonance frequency can be adjusted by changing the capacitance value of the capacitive element, so that the intensity of the received signal can be set optimally. Therefore, according to the second embodiment, communication errors are less likely to occur.

[Embodiment 3]
The semiconductor device of Embodiment 3 can perform wireless communication between three or more semiconductor chips. In the first and second embodiments, wireless communication is performed between two semiconductor chips. In this respect, the third embodiment is different from the first embodiment or the second embodiment.

FIG. 12 is a cross-sectional view for explaining the semiconductor device of the third embodiment.
Referring to FIG. 12, semiconductor device 100B is different from semiconductor device 100 of FIG. 1 in that it further includes a semiconductor chip 39, but the configuration of the other parts is the same as that of semiconductor device 100, and thus the description thereof will not be repeated. . The semiconductor chips 1, 2 and 39 are housed in the package 17.

  The semiconductor chip 39 is manufactured by a CMOS process, like each of the semiconductor chips 1 and 2. The semiconductor chip 39 has the same configuration as each of the semiconductor chips 1 and 2. Specifically, the semiconductor chip 39 includes an antenna 40, an insulating film 41, and a silicon substrate 42. The antenna 40 is formed in the insulating film 41. The semiconductor chip 39 is placed on the semiconductor chip 1 with the silicon substrate 42 facing down. The semiconductor chip 39 may be directly placed on the semiconductor chip 1, or a thin insulating film may be inserted between the semiconductor chip 1 and the semiconductor chip 39. The semiconductor chip 1 is supplied with power through the wire 38 and the pad 13. Power is supplied to the semiconductor chip 39 by a wire (not shown).

  The semiconductor chip 2 is mounted such that its main surface faces the main surface of the semiconductor chip 39. The space between the semiconductor chip 2 and the semiconductor chip 39 is hollow for electrical insulation. An insulating film may be provided between the semiconductor chip 2 and the semiconductor chip 39. Power is supplied to the semiconductor chip 2 through the pads 43 of the semiconductor chip 39, the ball bonder 15 connected to the pads 43, and the pads 14 of the semiconductor chip 2 connected to the ball bonder 15.

  Hereinafter, signal transmission from the semiconductor chip 1 to the semiconductor chip 2 performed via the semiconductor chip 39 will be described. However, in the case of signal transmission from the semiconductor chip 2 to the semiconductor chip 1 performed via the semiconductor chip 39, the same operation as described below is performed.

  First, signal transmission from the semiconductor chip 1 to the semiconductor chip 39 will be described. The shapes of the antenna 3 and the antenna 40 are both square. The radii of the antenna 3 and the antenna 40 are both 100 μm. The number of turns of the antenna 3 and the antenna 40 is 2, and they are wound in the same direction. When the antenna 3 and the antenna 40 are viewed from above the main surface of the semiconductor chip 1, the antenna 40 and the antenna 3 are arranged to overlap each other.

  The four sides of the antenna 40 are located on the corresponding four sides of the antenna 3 at the shortest distance. Therefore, the coupling coefficient of the antenna 3 and the antenna 40 is increased. Since the coupling coefficient is large, an induced current flowing through the antenna 40 due to electromagnetic coupling increases when a signal is transmitted from the semiconductor chip 1 to the semiconductor chip 39. Therefore, the strength of the received signal can be increased.

  A silicon substrate 42 exists between the antenna 3 and the antenna 40. When a transmission signal is applied to the antenna 3 of the semiconductor chip 1, an induced current flows through the antenna 40 due to electromagnetic coupling between the antennas. Since the silicon substrate 42 exists between the antenna 3 and the antenna 40, an eddy current is generated in the silicon substrate 42. Therefore, loss occurs in the silicon substrate 42. As in the first embodiment, the generation of eddy current is suppressed by the upper electrode 5 and the lower electrode 7 in the silicon substrate 9.

  In order to bring the antenna 3 and the antenna 40 closer, the silicon substrate 42 is thinned. As shown in FIG. 3, the coupling coefficient increases as the distance between the antennas decreases. Therefore, even if a demagnetizing field is generated by the eddy current generated in the silicon substrate 42 and the coupling coefficient is lowered, a coupling coefficient of 0.1 or more can be secured.

  However, the thickness of the silicon substrate 42 should be as thin as possible. Specifically, the thickness is preferably set so that the distance between the antenna 3 and the antenna 40 is within a radius of the antenna. For example, when both the radius of the antenna 3 and the radius of the antenna 40 are 100 μm, the thickness of the silicon substrate 42 is set to 50 μm or less.

  Two terminals of the antenna 40 are respectively connected to both ends of a capacitive element (not shown) of the semiconductor chip 39. At the resonance frequency determined by the inductance of the antenna 40 and the capacitance value of the capacitive element, the intensity of the received current generated in the antenna 40 increases. Therefore, even if the intensity of the signal transmitted from the semiconductor chip 1 is small, the semiconductor chip 39 can obtain a received signal having a large intensity.

Next, signal transmission from the semiconductor chip 39 to the semiconductor chip 2 will be described.
The main surfaces of the semiconductor chip 39 and the semiconductor chip 2 are arranged to face each other. Therefore, the antenna 40 and the antenna 4 face each other. The antenna 40 and the antenna 4 have the same radius and the same number of turns. Further, the winding directions of the antenna 40 and the antenna 4 are opposite to each other. Thus, when the antenna 4 and the antenna 40 are viewed from above the main surface of the semiconductor chip 39, the antenna 4 and the antenna 40 overlap each other. Therefore, the electromagnetic coupling between the antenna 4 and the antenna 40 becomes strong.

  When a transmission signal is applied to the antenna 40, a reception current flows through the antenna 4 due to electromagnetic coupling between the antennas. The received current is converted into a voltage by a load resistor (load resistor 33 in FIG. 7). As described in the first embodiment, the reception voltage becomes the highest at the resonance frequency determined by the capacitance immediately below the antenna 4 and the inductance of the antenna 4.

  When a transmission signal is applied to the antenna 40, magnetic flux is generated on both sides of the semiconductor chip 2 side and the semiconductor chip 1 side with respect to the antenna 40. Magnetic flux generated on the semiconductor chip 2 side passes through the antenna 4, and magnetic flux generated on the semiconductor chip 1 side passes through the antenna 3. Here, by making the capacitance value of the capacitive element of the semiconductor chip 1 different from the capacitance value of the capacitive element of the semiconductor chip 2, the resonance frequencies of the semiconductor chip 1 and the semiconductor chip 2 can be made different from each other. Therefore, it is possible to prevent interference from occurring in the semiconductor chip 1 during signal transmission from the semiconductor chip 39 to the semiconductor chip 2.

  Similarly to the first embodiment, in the semiconductor chip 2, the upper electrode 6 and the lower electrode 8 can suppress the generation of eddy current in the silicon substrate 10.

  Similarly to Embodiment 2, in Embodiment 3, a capacitive element having the configuration shown in FIG. 11 may be connected to the antenna. Whether or not each of the plurality of electrodes 5A is connected to the terminal 22 by the switch 37 is controlled. Thereby, the capacitance value of the capacitive element becomes variable. Therefore, the resonance frequency can be made different between the semiconductor chip 1 and the semiconductor chip 2. Therefore, interference in the semiconductor chip 1 can be prevented.

  However, in signal transmission from the semiconductor chip 1 to the semiconductor chip 39, the received signal is weakened because the distance between the antennas is long and the silicon substrate 42 exists between the antennas. Therefore, in order to directly transmit a signal from the semiconductor chip 1 to the semiconductor chip 2, transmission power larger than those in the first and second embodiments is required.

  As described above, according to the third embodiment, communication can be performed between three or more semiconductor chips. Moreover, according to Embodiment 3, it becomes possible to prevent interference.

[Embodiment 4]
FIG. 13 is a cross-sectional view for explaining the semiconductor device of the fourth embodiment.

  Referring to FIG. 13, semiconductor device 100 </ b> C is different from semiconductor device 100 shown in FIG. 1 in that it includes packages 44 and 45 instead of package 17, but the configuration of other parts is the same as that of semiconductor device 100. The subsequent description will not be repeated.

  In the fourth embodiment, the semiconductor chip 1 and the semiconductor chip 2 are housed in packages 44 and 45, respectively. Therefore, in the fourth embodiment, wireless communication is performed between the semiconductor chip 1 and the semiconductor chip 2 via the packages 44 and 45. The semiconductor chips 1 and 2 are housed in packages 44 and 45, respectively, so that the main surfaces can face each other during communication.

  Thus, by mounting two semiconductor chips in separate packages, the semiconductor device of the fourth embodiment can be applied to the field of RFID (Radio Frequency Identification). For example, the semiconductor chip 1 is provided in an IC card and transmits a signal according to a signal sent from a card reader / writer. The semiconductor chip 2 is provided in a card reader / writer and sends a signal to the semiconductor chip 1. Further, the semiconductor chip 2 reads or rewrites information recorded on the IC card based on a signal sent from the semiconductor chip 1.

  Hereinafter, signal transmission from the semiconductor chip 1 to the semiconductor chip 2 will be described. However, the same operation is performed in the case of signal transmission from the semiconductor chip 2 to the semiconductor chip 1.

  Power supply to the semiconductor chip 1 and signal transmission from the outside (excluding the semiconductor chip 2) to the semiconductor chip 1 are performed via pins (not shown) of the substrate 46 that supports the semiconductor chip 1. Electric power is supplied to the semiconductor chip 2 via pins (not shown) of the substrate 47.

  As shown in FIG. 5, immediately below the antenna 3, there are a plurality of electrodes 5A orthogonal to the winding direction of the antenna, and a lower electrode 7 facing the plurality of electrodes 5A. Therefore, the generation of eddy current in the silicon substrate 9 is suppressed, and the antenna loss is reduced. Therefore, the Q value of the antenna 3 is improved. When magnetic flux generated upward from the antenna 3 penetrates the antenna 4, an induced current flows through the antenna 4 in a direction that cancels the magnetic field generated in the vicinity of the antenna 4. The current flowing through the antenna 4 becomes a received signal.

  An upper electrode 6 and a lower electrode 8 having the same shapes as the upper electrode 5 and the lower electrode 7 shown in FIG. Therefore, the semiconductor chip 2 can also reduce loss and improve the Q value of the antenna. The magnitude of the current flowing through the antenna 4 mainly depends on the magnitude of electromagnetic coupling between the antenna 3 and the antenna 4, that is, the value of the coupling coefficient.

  As in the first embodiment, in order to set the coupling coefficient to 0.1 or more, it is preferable that the distance between antennas is about the radius of the antenna. However, the distance between the antennas varies depending on the distance between the packages 44 and 45, the thickness of the packages 44 and 45, the loop size of the wires 48 and 49, and the like. Therefore, the distance between antennas may be larger than the length of the antenna radius during communication.

  In this case, as shown in FIG. 8, the reception voltage can be maximized at the resonance frequency by appropriately setting the capacitance value of the capacitive element formed immediately below the antenna 4. Therefore, the strength of the received signal can be increased even if the distance between the antennas is some distance away. As a result, in the semiconductor chip 2, a signal having a desired intensity can be obtained via an amplifier (not shown) at the subsequent stage of the antenna 4.

  Also in the fourth embodiment, a capacitive element having the configuration shown in FIG. 11 may be connected to each of antennas 3 and 4. In this case, the capacitance value can be changed by controlling each of the plurality of switches 37. As a result, since the resonance frequency can be changed, a signal having an optimum intensity can be received.

  As described above, according to the fourth embodiment, even when two semiconductor chips that perform wireless communication with each other are mounted in two different packages, the Q value of the antenna can be improved.

  In the above description, it is assumed that two semiconductor chips having the same configuration are housed in two packages, respectively. However, it is conceivable that the semiconductor chip mounted on the IC card as described above and the semiconductor chip mounted on the card reader / writer have different configurations of the antenna and the capacitive element connected to the antenna. Even in such a case, the semiconductor device mounted on either the IC card or the card reader / writer can suppress the generation of eddy currents by having the following configuration.

  The configuration of the upper electrode and the lower electrode of the capacitive element arranged immediately below the antenna is the configuration shown in FIG. In other words, both the upper electrode and the lower electrode include a plurality of strip electrodes arranged so as to be orthogonal to the winding direction of the antenna. Further, at least one (preferably both) of the upper electrode and the lower electrode includes an electrode surrounding a plurality of strip-shaped electrodes and having a cut at least at one place. As shown in FIG. 2, the antenna is formed on the uppermost metal layer of the multilayer metal wiring layer. Further, when the lower electrode is a diffusion layer formed on the main surface of the silicon substrate, it is possible to suppress the generation of eddy current inside the silicon substrate.

  Further, the upper electrode of the capacitor may be the same as the configuration shown in FIG. As a result, the number of strip electrodes connected to the antenna terminal is changed by the control of the switch, and the capacitance value is changed. Thus, the resonance frequency can be changed and the signal intensity can be adjusted.

  Further, as shown in FIG. 10, the lower electrode may be formed on an insulating film provided on the silicon substrate. In this case, since the leakage current is reduced, the voltage of the received signal can be set to have a steep peak at the resonance frequency.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

4 is a cross-sectional view for illustrating the semiconductor device of First Embodiment; FIG. It is a perspective view explaining the antennas 3 and 4 of FIG. It is a figure explaining the relationship between the distance of the antennas 3 and 4, and a coupling coefficient. It is a perspective view of the antenna 3 of FIG. It is a top view explaining the upper electrode 5 and the lower electrode 7 of FIG. It is sectional drawing between VI-VI of FIG. FIG. 2 is an equivalent circuit diagram of a signal transmission circuit of the semiconductor device 100 of FIG. 1. It is a figure which shows the frequency dependence of the receiving voltage u2 shown in FIG. FIG. 10 is a cross-sectional view for illustrating the semiconductor device of the second embodiment. 2 is a cross-sectional view illustrating a configuration of a capacitive element of a semiconductor chip 1. FIG. 6 is a plan view for explaining in more detail the capacitive element according to Embodiment 2. FIG. FIG. 10 is a cross-sectional view for explaining the semiconductor device of the third embodiment. FIG. 10 is a cross-sectional view for explaining the semiconductor device of the fourth embodiment.

Explanation of symbols

  1, 2, 39 Semiconductor chip, 3, 4, 40 Antenna, 3A, 3B, 4A, 4B side, 5, 6 Upper electrode, 5A, 5B, 7A, 7B electrode, 7, 8 Lower electrode, 9, 10, 42 Silicon substrate, 11, 12, 34, 35, 41 Insulating film, 13, 14, 43 Pad, 15 Ball bonder, 16, 46, 47 Substrate, 17, 44, 45 Package, 18, 19 Lead line, 20, 21, 24, 25 Via plug, 22, 23 terminal, 26 Oxide film, 27, 32 Capacitor element, 29, 30 Inductor, 31 Resistance, 33, 33A Load resistance, 36 Dielectric film, 37 Switch, 38, 48, 49 Wire, 100 , 100A to 100C Semiconductor device, CTL control circuit, P1 point, SND transmission circuit.

Claims (9)

Comprising first and second semiconductor chips capable of wireless communication with each other;
The first and second semiconductor chips are arranged such that their main surfaces face each other,
Each of the first and second semiconductor chips includes:
A semiconductor substrate on which a communication circuit is formed;
An insulating film formed on the semiconductor substrate;
An antenna formed in the insulating film so as to be wound on the main surface and having first and second terminals;
The insulating film is formed between the antenna and the semiconductor substrate, and is disposed so as to be orthogonal to the winding direction of the antenna when viewed from a direction perpendicular to the main surface. A plurality of first electrodes electrically connected to the terminals;
A plurality of layers formed on the main surface of the semiconductor substrate or between the semiconductor substrate and the plurality of first electrodes and respectively overlapping the plurality of first electrodes when viewed from a direction perpendicular to the main surface. A second electrode of
Each of the plurality of second electrodes is a semiconductor device electrically connected to the second terminal.   2. The device according to claim 1, further comprising a third electrode that is provided so as to surround any one of the plurality of first electrodes and the plurality of second electrodes, and in which at least one cut is formed. Semiconductor device. The radius of the antenna included in the first semiconductor chip and the radius of the antenna included in the second semiconductor chip are the same size,
The distance between the first semiconductor chip and the second semiconductor chip is such that the distance between the antennas included in each of the first and second semiconductor chips is less than or equal to the radius of the antenna. The semiconductor device according to claim 2, wherein the semiconductor device is set. Each of the first and second semiconductor chips includes:
Further comprising a multilayer metal wiring layer,
The semiconductor device according to claim 2, wherein the antenna is provided in an uppermost metal wiring layer of the multilayer metal wiring layers. The third electrode is provided corresponding to the plurality of second electrodes,
The semiconductor device includes:
A plurality of switches provided corresponding to the plurality of first electrodes, respectively, for switching whether or not the corresponding first electrode is connected to the first terminal;
The semiconductor device according to claim 2, further comprising: a control circuit that controls each of the plurality of switches according to a voltage between the first and second terminals.   The semiconductor device according to claim 2, wherein the plurality of second electrodes are diffusion layers formed on the semiconductor substrate.   The semiconductor device according to claim 2, wherein the plurality of second electrodes are formed in the insulating film.   The semiconductor device according to claim 1, further comprising a package that houses the first and second semiconductor chips. The semiconductor device includes:
A first package for housing the first semiconductor chip;
The semiconductor device according to claim 1, further comprising: a second package that houses the second semiconductor chip.

Images