WO1996032676A1 - Procede et dispositif de calcul de sommes de produits - Google Patents

Procede et dispositif de calcul de sommes de produits Download PDF

Info

Publication number
WO1996032676A1
WO1996032676A1 PCT/RU1996/000088 RU9600088W WO9632676A1 WO 1996032676 A1 WO1996032676 A1 WO 1996032676A1 RU 9600088 W RU9600088 W RU 9600088W WO 9632676 A1 WO9632676 A1 WO 9632676A1
Authority
WO
WIPO (PCT)
Prior art keywords
calculating
products
sums
output
προizvedeny
Prior art date
Application number
PCT/RU1996/000088
Other languages
English (en)
Russian (ru)
Inventor
Alexandr Jurievich Boltunov
Original Assignee
Strakhov, Sergei Vitalievich
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Strakhov, Sergei Vitalievich filed Critical Strakhov, Sergei Vitalievich
Priority to AU57066/96A priority Critical patent/AU5706696A/en
Priority to US08/945,283 priority patent/US6058411A/en
Publication of WO1996032676A1 publication Critical patent/WO1996032676A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products

Definitions

  • the device calculates the sums of partial products of the form a * b), i.e. realizes the principle:
  • the device does not constitute partial products & ⁇ * ⁇ and therefore cannot be completed as a functional unit for multiplication. It is well-known for calculating amounts of industrial products, which works in two modes: calculating the products of 16 single numbers, calculating the sum of two products of 8 single numbers.
  • the devices described above are the intended components of the LSI ⁇ 1815 ⁇ 1 and 151815I ⁇ 1 from the fast microcircuit LSI series ⁇ 1815 for the digital signal.
  • the objective of the invention is to increase the performance and speed, while reducing the hardware and the overall acceleration of the system, while increasing the speed
  • the task posed is solved in such a way that the means for calculating the sums of the products, as agreed on by the invention, include: to the result (to - 2, 3, ...,) 1 value of the electrical signal, ... 1 to the transmission channels, quantitatively (t -1, 2, 7), with the system of dividing by ⁇ ( ⁇ - 2,
  • G ⁇ elemen ⁇ v ⁇ e ⁇ v ⁇ go ⁇ i ⁇ a (r ⁇ - 1, 2, 10), ⁇ azhdy elemen ⁇ ⁇ e ⁇ v ⁇ go ⁇ i ⁇ a from among Sh ⁇ , s ⁇ vmes ⁇ n ⁇ with elemen ⁇ ami v ⁇ go ⁇ i ⁇ a ⁇ b ⁇ azue ⁇ ⁇ anal ⁇ e ⁇ edachi s ⁇ s ⁇ em ⁇ y dividing by ⁇ , ⁇ ichem ⁇ un ⁇ tsiyu s ⁇ emy dividing by ⁇ , vy ⁇ lnyae ⁇ elemen ⁇ ⁇ e ⁇ v ⁇ go ⁇ i ⁇ a, elemen ⁇ v ⁇ go ⁇ i ⁇ a vy ⁇ lnyae ⁇ ⁇ un ⁇ tsiyu ⁇ dn ⁇ az ⁇ yadn ⁇ go za ⁇ minayusche- g ⁇ us ⁇ ys ⁇ va if the following elemen ⁇ m ⁇ anala ⁇ e ⁇ edachi y
  • the development is the solution: the elements of the first and second types have an input of synchronization.
  • the availability of synchronization makes it possible to increase the reliability and speed of operation of the device as a whole.
  • the mode of operation and synchronization ensures the connection between the channels, such as by specifying the operating mode.
  • the device for calculating the amounts of product information is multiplied by the principle: I- ⁇
  • the essence of the distinguishing features is that the data processing is carried out in parallel to all discharges.
  • ⁇ 0 ⁇ 0 between the polynomial coefficients and the discrete values of the signal parameter: ⁇ - -8 ⁇ (0) - 21. [3] W / 4) - 16 ⁇ 2 / 4) + 2 [6] ⁇ )
  • the device can calculate one or several amounts of products expressed in different phrases, for example:
  • the device can perform functions of specialized processes, such as filtering, compression, diagnostics of discharges, and discharges of power.
  • Figures 1 and 2 illustrate the elements of the corresponding primary and second types for working with binary numbers, in FIG. 3 ⁇ eds ⁇ avlena s ⁇ u ⁇ u ⁇ naya s ⁇ ema us ⁇ ys ⁇ va ⁇ imeni ⁇ eln ⁇ for ⁇ a ⁇ alleln ⁇ go summi ⁇ vaniya to ⁇ m ⁇ - ⁇ az ⁇ yadny ⁇ slagaemy ⁇ on ⁇ ig. 4
  • FIG. 5 is shown a change in the state of the elements in operation of the devices shown in FIG. 4 on the basis of finite numbers, on fig.
  • FIG. 6 a structural diagram of the device is used, which is useful for calculating the sums of partial products of a single pair of Sh ⁇ - single digits, in fig. 7
  • the diagram of the device for calculating the sums of partial products of 8-digit binary numbers is presented.
  • 8 is shown a change in the state of the elements when using the device shown in FIG. 7 on the basis of finite numbers, on fig. 9
  • the structure of the device is presented that is suitable for multiplying a single pair of ⁇ -digit numbers by Sprint ⁇ .
  • FIG. 11 The structured scheme of the formation of binary partial products is presented, in FIG. 11
  • ch ⁇ by numbers were ⁇ eds ⁇ avleny as to s ⁇ v ⁇ u ⁇ n ⁇ s ⁇ ey 1 values ele ⁇ iches ⁇ go dis ⁇ e ⁇ n ⁇ g ⁇ ⁇ a ⁇ ame ⁇ a sigiala, ⁇ ichem signal itself m ⁇ zhe ⁇ by ⁇ ⁇ a ⁇ anal ⁇ govym, ⁇ a ⁇ and dis ⁇ e ⁇ nym, e ⁇ i s ⁇ v ⁇ u ⁇ n ⁇ s ⁇ i ⁇ dayu ⁇ in ⁇ analy ⁇ e ⁇ edachi, ⁇ liches ⁇ v ⁇ ⁇ y ⁇ br, s ⁇ s ⁇ em ⁇ y dividing by ⁇ , the number ⁇ corresponds to the number system, the numbers are also presented, the number system also takes into account all the combinations of the signal value 1 / the value It goes into the transmission channel corresponding to its weight, if
  • the devices for calculating the sums of the products are used for the total summing up, including the elements of the first type 14, the elements of the second type 15 are not connected. 3.
  • devices For binary numbers, devices include elements of type 16, elements of type 17 (Fig. 4). Item 17 is the item shown in FIG. 1, item 16 is the item shown in FIG. 2.
  • the device operates the following way. Pus ⁇ ne ⁇ b ⁇ dim ⁇ sl ⁇ zhi ⁇ 8-bi- ⁇ vy ⁇ numbers (10101010) 2 - (170) w, (01010101) 2 - (85) w, (01010111) 2 - (87) w,
  • ⁇ ⁇ bschem case summi ⁇ vanie ⁇ izv ⁇ di ⁇ sya 2 * to ⁇ a ⁇ v here to chisl ⁇ slagaemy ⁇ and v ⁇ emya ⁇ a ⁇ a not ⁇ evyshae ⁇ v ⁇ emeni ⁇ e ⁇ e ⁇ lyucheniya ⁇ i ⁇ v ⁇ go l ⁇ giches ⁇ go elemen ⁇ a for vyb ⁇ ann ⁇ y ⁇ e ⁇ n ⁇ l ⁇ gii izgo ⁇ vleniya, e ⁇ ⁇ busl ⁇ vlen ⁇ ⁇ em, ch ⁇ us ⁇ ys ⁇ v ⁇ imee ⁇ ⁇ egulya ⁇ nuyu ⁇ dn ⁇ dnuyu s ⁇ u ⁇ u ⁇ u.
  • the device costs are equal to 67 units, if you take into account the functions of the elements close to the functions of the units. 10
  • the device for calculating the amounts of partial products is used for calculating the amounts of partial parts of the product shown in FIG. 6, the device includes elements of the first type 14, elements of the second type 15. It is suitable for binary numbers, which are presented in the form of a distributed binary voltage level. 7, the device includes the elements of the second type 16, the elements of the first type 17.
  • the device operates the following way. Be sure to multiply the pair of 8-bit ⁇ numbers (10011001) 2 - (153) th, (00100101) 2 - (37) th (153 * 37 - 5661). Partial works are binary numbers: 10011001, 0: 0, 10011001, 0: 0, 0: 0, 10011001, 0: 0, 0: 0. Downloading partly produced materials occurs at the material weights, according to their weights, the partial products that have the smallest weight are used at the very top of the material (
  • the func- tional analogue performs the same operation for two pairs for 1.9 ⁇ s and the unit costs: 184 units, 60 single-load cycles, or a quick load of 16 seconds P ⁇ edlagaem ⁇ e us ⁇ ys ⁇ v ⁇ vychislyae ⁇ amount chas ⁇ ichny ⁇ ⁇ izvedeny 2 * t ⁇ ⁇ a ⁇ v, where m ⁇ ⁇ az ⁇ yadn ⁇ s ⁇ chas ⁇ ichny ⁇ ⁇ izvedeny, v ⁇ zm ⁇ zhn ⁇ e v ⁇ emya zade ⁇ - zh ⁇ i 0.16 ns.
  • the unit is involved in the suppression of signal changes to external outputs.
  • the device includes a multiplication block 29, cumulative total of 30, an output data bus 31, a total data bus 32, a memory block 33, an input signal signal 34, free of charge, 36, free of charge, 36 .
  • the instructions for multiplying can be removed from the outside, from the CPU, from the memory unit, from the output bus 24, from the output bus 31, the receiver can be removed to receive data, 31 In this way, the device can calculate the sums of products of different configurations.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
  • Nitrogen And Oxygen Or Sulfur-Condensed Heterocyclic Ring Systems (AREA)

Abstract

Cette invention concerne le domaine de l'informatique et de la micro-électronique, et est destiné à la fabrication de circuits intégrés rapides et d'ensembles de circuits intégrés pour le traitement numérique de signaux, pour le calcul de sommes de produits, pour la multiplication et pour l'addition. Ce procédé consiste essentiellement à envoyer envoyer l'ensemble des valeurs d'un paramètre électrique de signal dans des canaux de transmission dont le nombre m correspond au déchargement des termes. Un système de calcul, auquel correspond le nombre n, permet de définir le nombre de toutes les combinaisons possibles de l'ensemble des valeurs 1/m du paramètre électrique du signal, lesdites valeurs étant envoyées dans un canal de transmission en fonction de leur poids. L'ensemble des valeurs 1/m du paramètre électrique du signal est envoyé dans un circuit de division par n tandis que s'effectue la transmission depuis le canal de transmission précédent vers l'entrée du canal de transmission suivant. Les résultats sont obtenus aux sorties des (m+1) canaux de transmission sous forme d'une suite de l'ensemble de valeurs du paramètre électrique. Ce dispositif comprend p unités se composant chacune d'éléments du premier type montés en série et remplissant la fonction de division par n, ainsi que des éléments du second type remplissant la fonction de mémoire à décharge unique.
PCT/RU1996/000088 1995-04-12 1996-04-11 Procede et dispositif de calcul de sommes de produits WO1996032676A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU57066/96A AU5706696A (en) 1995-04-12 1996-04-11 Method and device for computing product sums
US08/945,283 US6058411A (en) 1995-04-12 1996-04-11 Method and device for computing product sums

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
UZ9500374 1995-04-12
UZINDR9500374.1 1995-04-12
UZ9500383 1995-04-14
UZINAR9500383.2 1995-04-14
UZINAR9500393.2 1995-04-18
UZ9500393 1995-04-18
UZINAR9500446.2 1995-05-01
UZ9500446 1995-05-01

Publications (1)

Publication Number Publication Date
WO1996032676A1 true WO1996032676A1 (fr) 1996-10-17

Family

ID=27506056

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/RU1996/000088 WO1996032676A1 (fr) 1995-04-12 1996-04-11 Procede et dispositif de calcul de sommes de produits

Country Status (3)

Country Link
US (1) US6058411A (fr)
AU (1) AU5706696A (fr)
WO (1) WO1996032676A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69935361T2 (de) * 1998-02-17 2007-11-29 Anadec Gmbh Verfahren und elektronische Schaltung zur Datenverarbeitung, insbesondere für die Berechnung von Wahrscheinlichkeitsverteilungen
RU2522852C1 (ru) * 2013-04-09 2014-07-20 Открытое акционерное общество "Научно-исследовательский институт "Субмикрон" Бортовой спецвычислитель

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4215419A (en) * 1977-06-09 1980-07-29 Stanislaw Majerski Method for binary multiplication of a number by a sum of two numbers and a digital system for implementation thereof
EP0078101A2 (fr) * 1981-10-27 1983-05-04 Itt Industries, Inc. Multiplieur pour former une somme de produits
SU1117635A1 (ru) * 1983-01-07 1984-10-07 Харьковский Ордена Ленина Политехнический Институт Им.В.И.Ленина Вычислительное устройство
SU1291975A1 (ru) * 1985-09-11 1987-02-23 Минский радиотехнический институт Устройство дл умножени
SU1302272A1 (ru) * 1985-04-24 1987-04-07 Институт кибернетики им.В.М.Глушкова Устройство дл суммировани частичных произведений
EP0476558A2 (fr) * 1990-09-19 1992-03-25 Nec Corporation Additionneur de produits

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5305250A (en) * 1989-05-05 1994-04-19 Board Of Trustees Operating Michigan State University Analog continuous-time MOS vector multiplier circuit and a programmable MOS realization for feedback neural networks
DE4218769A1 (de) * 1992-06-06 1993-12-09 Philips Patentverwaltung Verfahren und Anordnung zum Bilden der Summe einer Kette von Produkten

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4215419A (en) * 1977-06-09 1980-07-29 Stanislaw Majerski Method for binary multiplication of a number by a sum of two numbers and a digital system for implementation thereof
EP0078101A2 (fr) * 1981-10-27 1983-05-04 Itt Industries, Inc. Multiplieur pour former une somme de produits
SU1117635A1 (ru) * 1983-01-07 1984-10-07 Харьковский Ордена Ленина Политехнический Институт Им.В.И.Ленина Вычислительное устройство
SU1302272A1 (ru) * 1985-04-24 1987-04-07 Институт кибернетики им.В.М.Глушкова Устройство дл суммировани частичных произведений
SU1291975A1 (ru) * 1985-09-11 1987-02-23 Минский радиотехнический институт Устройство дл умножени
EP0476558A2 (fr) * 1990-09-19 1992-03-25 Nec Corporation Additionneur de produits

Also Published As

Publication number Publication date
US6058411A (en) 2000-05-02
AU5706696A (en) 1996-10-30

Similar Documents

Publication Publication Date Title
US4135249A (en) Signed double precision multiplication logic
WO1998022871A1 (fr) Pre-additionneur integre pour un multiplicateur
FR2585859A1 (fr) Unite de commande d'operations de masques vectoriels.
US20040225705A1 (en) Method and device for performing operations involving multiplication of selectively partitioned binary inputs using booth encoding
JPH0370411B2 (fr)
US6603812B1 (en) Hardware implementation of a decimating finite impulse response filter
EP0442356A2 (fr) Additionneur de colonne à délai pesé et son procédé de construction
US5408422A (en) Multiplication circuit capable of directly multiplying digital data with analog data
WO1996032676A1 (fr) Procede et dispositif de calcul de sommes de produits
CN108958704B (zh) 一种数据处理装置及方法
US7024445B2 (en) Method and apparatus for use in booth-encoded multiplication
US5638309A (en) Pseudo-random pattern generating circuit
US5477479A (en) Multiplying system having multi-stages for processing a digital signal based on the Booth's algorithm
NL8700216A (nl) Werkwijze voor het testen van een gemodificeerde boothmultiplicator, gemodificeerde boothmultiplicator, geschikt om volgens deze werkwijze te worden getest, en geintegreerde schakeling, voorzien van een dergelijke gemodificeerde boothmultiplicator.
US5781462A (en) Multiplier circuitry with improved storage and transfer of booth control coefficients
JPS5981761A (ja) シストリツク計算配列
EP0344226B1 (fr) Systeme additionneur rapide
JPS60114020A (ja) 非巡回型デジタルフィルタ回路
US5424967A (en) Shift and rounding circuit and method
KR0147942B1 (ko) 승산기에서의 부스 레코딩회로
EP0122843B1 (fr) Intégrateur modulaire
US5889691A (en) Apparatus and method for a multiplier unit with high component utilization
JP3433487B2 (ja) ２進１０進変換器
JP2643165B2 (ja) 演算回路
JP2894749B2 (ja) 並列乗算器

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AL AM AT AU AZ BB BG BR BY CA CH CN CZ DE DK EE ES FI GB GE HU IS JP KE KG KP KR KZ LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK TJ TR TT UA UG US UZ VN AM AZ BY KG KZ MD RU TJ TM

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): KE LS MW SD SZ UG AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN ML

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 08945283

Country of ref document: US

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: CA