WO1996025732A1 - Verfahren zur darstellung von in nicht äquidistanter form übertragenen bildsignalen auf einem datensichtgerät, das nur äquidistante bildsignale anzeigt - Google Patents

Verfahren zur darstellung von in nicht äquidistanter form übertragenen bildsignalen auf einem datensichtgerät, das nur äquidistante bildsignale anzeigt Download PDF

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Publication number
WO1996025732A1
WO1996025732A1 PCT/DE1996/000191 DE9600191W WO9625732A1 WO 1996025732 A1 WO1996025732 A1 WO 1996025732A1 DE 9600191 W DE9600191 W DE 9600191W WO 9625732 A1 WO9625732 A1 WO 9625732A1
Authority
WO
WIPO (PCT)
Prior art keywords
image
equidistant
display device
decoder circuit
images
Prior art date
Application number
PCT/DE1996/000191
Other languages
German (de)
English (en)
French (fr)
Inventor
Wolfgang Ecker
Original Assignee
Siemens Aktiengesellschaft
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO1996025732A1 publication Critical patent/WO1996025732A1/de

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00Television systems
    • H04N7/24Systems for the transmission of television signals using pulse code modulation
    • H04N7/52Systems for transmission of a pulse code modulated video signal with one or more other pulse code modulated signals, e.g. an audio signal or a synchronizing signal
    • H04N7/54Systems for transmission of a pulse code modulated video signal with one or more other pulse code modulated signals, e.g. an audio signal or a synchronizing signal the signals being synchronous
    • H04N7/56Synchronising systems therefor
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39Control of the bit-mapped memory
    • G09G5/395Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41Structure of client; Structure of client peripherals
    • H04N21/414Specialised client platforms, e.g. receiver in car or embedded in a mobile appliance
    • H04N21/4143Specialised client platforms, e.g. receiver in car or embedded in a mobile appliance embedded in a Personal Computer [PC]
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41Structure of client; Structure of client peripherals
    • H04N21/426Internal components of the client ; Characteristics thereof
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/4302Content synchronisation processes, e.g. decoder synchronisation
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00Aspects of display data processing
    • G09G2340/12Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00Details of television systems
    • H04N5/04Synchronising

Definitions

  • Data e.g. Image signals are today compressed according to different standards (e.g. MPEG1 or MPEG2) before transmission, then transmitted and then processed again so that they can be displayed by a data display device.
  • the problem here is that the transmitted image signals are not equidistant, but the data display device can only display equidistant image signals.
  • An equidistant image signal is a signal in which the same amount of data is transmitted for each pixel and in which the same time is used for the transmission of the data required for each pixel.
  • An example of an equidistant image signal is the PAL method used today for the transmission of television images or the RGB2 control of a data display device.
  • a non-equi-distant image signal is a signal in which a different amount of data is transmitted for each pixel.
  • pixels are combined and their data are transmitted together. Even the transmission of combined image signals does not always take the same time.
  • a non-equidistant image signal is based on an equidistant image signal, which must be derived from the non-equidistant image signal for the purpose of displaying or processing the image signal.
  • An example of a non-equidistant image signal are signals that have been compressed according to the MPEG standard.
  • the problem on which the invention is based is to specify a further method according to which the equidistant image signals extracted from the non-equidistant image signals are synchronized with the properties of the data display device, in particular its timing, without using a FIFO memory or a second video memory.
  • Data display device that is to say its display unit or monitor, which offers decompressed image signals such that they can be displayed on the monitor with the time behavior of the data display device.
  • the image memory present in the decoder circuit for decoding the non-equidistant image signal, in which the equidistant image signal is stored, is used.
  • the decoder circuit is sent synchronization signals from the data display device, which indicate which image signal is to be displayed on the monitor and which cause the image signal to be transmitted to the data display device in accordance with the frequency of the data display device.
  • the data display device controls the circuit by means of a synchronization mechanism, which generates an equidistant image signal from the non-equidistant image signal, in such a way that that circuit is able to do that Generate equidistant image signal synchronized with the operation of the monitor.
  • FIG. 1 shows a block diagram of an arrangement by means of which incoming non-equidistant image signals are converted into equidistant image signals and is synchronized with the mode of operation of the monitor of the data display device
  • Figures 2 and 3 show a detailed representation of the arrangement provided that the transmission of the image signals takes place according to the MPEG standard
  • Figure 4 shows another embodiment of the arrangement.
  • the arrangement is supplied with, for example, MPEG video signals MD and decoded in a known decoder circuit DEC.
  • the decoder circuit DEC also contains an image memory which at least also contains the current image to be displayed on a monitor MO, in addition to other images which are required in order to recover the current image. Methods for decoding these image signals are known; they result, for example, for the MPEG standard from VLSI implementation of MPEG decoders on pages 165 to 171.
  • the decoder circuit DEC generates, from the MPEG video signals MD, equidistant image signals B which are stored in the image memory or video memory VSP of the Data display device can be cached or passed on directly to the screen.
  • the image signals must be fed from the image memory VSP to the monitor MO in an equidistant form and in accordance with its time behavior, in FIG. 1 as image signals RGB2.
  • This takes advantage of the fact that the images generated there must be stored in the decoder circuitry DEC, since this is necessary in order to decompress the images compressed according to the standard and to produce them in equidistant form.
  • the result is that only by the Synchronisa ⁇ tion via the monitor control MST the image signals are offered to the monitor MO in such a way that the latter can also display the images without the need for additional memories.
  • FIGS. 2 and 3 differs from FIG. 1 in some respects.
  • the image signals M-D compressed according to the MPEG standard are decoded according to the MPEG standard in an arrangement FD, inversely quantized in an arrangement Q and inversely transformed DCT.
  • the pixels are generated in an arrangement BG and stored in the image memory BSP. From the images stored in the image memory BSP, the images are generated in an equi-distant form in accordance with the MPEG standard with the aid of an arrangement MP.
  • the interpolator IP which is in any case present in a decoder circuit, is used and is synchronized accordingly. This can e.g. via a video generator VG present at the data display device, which sends side synchronization signals S1 to the interpolator IP, which indicate when a new image section from the decoder circuit DEC must be given to the video generator VG.
  • Which image section is to be displayed on the monitor MO can be determined, for example, via a computer bus BUS. Every time a pixel B of the MPEG image on the monitor MO to be displayed, the video generator VG continues to send a pixel synchronization pulse S2 to the interpolator IP. This pixel synchronization pulse S2 indicates to the interpolator IP that it must transmit another pixel B to the video generator VG.
  • the image sections to be displayed on the monitor MO can be addressed in the image memory BSP of the decoder circuit and the time at which the individual pixels are transmitted to the video generator VG can also be determined.
  • the pixel synchronization pulses S2 that regulate the time behavior are then selected such that the transmission of the pixels is adapted to the time behavior of the data display device. This means that the adaptation to the behavior of the data display device takes place with the aid of synchronization, e.g. by the video generator VG using the image memory available in the decoder circuit, in which the current image to be displayed is always stored.
  • FIG. 3 also contains further arrangements which are not required for the method according to the invention, but which are present in a data display device which must display images which e.g. be delivered by a computer.
  • This includes an image memory VSP1, which is connected to the computer bus BUS, which leads to a computer.
  • a pixel generator BPG is provided, which generates the pixels from the signals supplied by the computer, which are stored in the pixel memory VSP1 so that they can be displayed on the monitor MO.
  • These units BPG and VSPl are, however, not required in the exemplary embodiment in FIG. 2 in order to generate the MPEG signals M-D as pictures after their decoding on the monitor MO.
  • pixels and image signals are denoted by B, addresses by A.
  • the arrangements IP, BSP, MP, BG, Q, FD, which form the decoder circuit, are known from the literature and can be found, for example, in the literature cited above.
  • the arrangements BPG, VSPl and VG are usually present in the data display devices.
  • the invention consists in that, by utilizing the existing arrangements or modules solely by means of a sensible synchronization, image signals which are not in a form which the monitor can process are offered to the monitor in such a way that they are displayed can.
  • the video signals RGB2 are applied to the monitor by the decoder DEC or video generator VG via a multiplexer Mux.
  • FIG. 1 The advantage of FIG. 1 is that, compared to FIGS. 2 to 4, no additional synchronization to the multiplexer MUX or video generator has to be established. The synchronization is necessary to indicate whether pixels from the pixel generator or from the video data stream are displayed on the monitor.

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Compression Of Band Width Or Redundancy In Fax (AREA)
  • Controls And Circuits For Display Device (AREA)
PCT/DE1996/000191 1995-02-16 1996-02-07 Verfahren zur darstellung von in nicht äquidistanter form übertragenen bildsignalen auf einem datensichtgerät, das nur äquidistante bildsignale anzeigt WO1996025732A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19505290.0 1995-02-16
DE19505290 1995-02-16

Publications (1)

Publication Number Publication Date
WO1996025732A1 true WO1996025732A1 (de) 1996-08-22

Family

ID=7754182

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Application Number Title Priority Date Filing Date
PCT/DE1996/000191 WO1996025732A1 (de) 1995-02-16 1996-02-07 Verfahren zur darstellung von in nicht äquidistanter form übertragenen bildsignalen auf einem datensichtgerät, das nur äquidistante bildsignale anzeigt

Country Status (3)

Country Link
AR (1) AR000973A1 (enrdf_load_stackoverflow)
TW (1) TW295766B (enrdf_load_stackoverflow)
WO (1) WO1996025732A1 (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0847038A3 (en) * 1996-12-09 1999-11-03 STMicroelectronics, Inc. Rendering an audio-visual stream synchronized by a software clock in a personal computer

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5027212A (en) * 1989-12-06 1991-06-25 Videologic Limited Computer based video/graphics display system
EP0572024A2 (en) * 1992-05-27 1993-12-01 Kabushiki Kaisha Toshiba Multimedia display control system for storing image data in frame buffer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5027212A (en) * 1989-12-06 1991-06-25 Videologic Limited Computer based video/graphics display system
EP0572024A2 (en) * 1992-05-27 1993-12-01 Kabushiki Kaisha Toshiba Multimedia display control system for storing image data in frame buffer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0847038A3 (en) * 1996-12-09 1999-11-03 STMicroelectronics, Inc. Rendering an audio-visual stream synchronized by a software clock in a personal computer

Also Published As

Publication number Publication date
TW295766B (enrdf_load_stackoverflow) 1997-01-11
AR000973A1 (es) 1997-08-27

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