WO1996025732A1 - Method of displaying video signals transmitted in a non-equidistant form on a video terminal which only displays equidistant video signals - Google Patents

Method of displaying video signals transmitted in a non-equidistant form on a video terminal which only displays equidistant video signals Download PDF

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Publication number
WO1996025732A1
WO1996025732A1 PCT/DE1996/000191 DE9600191W WO9625732A1 WO 1996025732 A1 WO1996025732 A1 WO 1996025732A1 DE 9600191 W DE9600191 W DE 9600191W WO 9625732 A1 WO9625732 A1 WO 9625732A1
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WO
WIPO (PCT)
Prior art keywords
image
equidistant
display device
decoder circuit
images
Prior art date
Application number
PCT/DE1996/000191
Other languages
German (de)
French (fr)
Inventor
Wolfgang Ecker
Original Assignee
Siemens Aktiengesellschaft
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Filing date
Publication date
Application filed by Siemens Aktiengesellschaft filed Critical Siemens Aktiengesellschaft
Publication of WO1996025732A1 publication Critical patent/WO1996025732A1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/24—Systems for the transmission of television signals using pulse code modulation
    • H04N7/52—Systems for transmission of a pulse code modulated video signal with one or more other pulse code modulated signals, e.g. an audio signal or a synchronizing signal
    • H04N7/54—Systems for transmission of a pulse code modulated video signal with one or more other pulse code modulated signals, e.g. an audio signal or a synchronizing signal the signals being synchronous
    • H04N7/56—Synchronising systems therefor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
    • H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41—Structure of client; Structure of client peripherals
    • H04N21/414—Specialised client platforms, e.g. receiver in car or embedded in a mobile appliance
    • H04N21/4143—Specialised client platforms, e.g. receiver in car or embedded in a mobile appliance embedded in a Personal Computer [PC]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41—Structure of client; Structure of client peripherals
    • H04N21/426—Internal components of the client ; Characteristics thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/12—Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising

Definitions

  • Data e.g. Image signals are today compressed according to different standards (e.g. MPEG1 or MPEG2) before transmission, then transmitted and then processed again so that they can be displayed by a data display device.
  • the problem here is that the transmitted image signals are not equidistant, but the data display device can only display equidistant image signals.
  • An equidistant image signal is a signal in which the same amount of data is transmitted for each pixel and in which the same time is used for the transmission of the data required for each pixel.
  • An example of an equidistant image signal is the PAL method used today for the transmission of television images or the RGB2 control of a data display device.
  • a non-equi-distant image signal is a signal in which a different amount of data is transmitted for each pixel.
  • pixels are combined and their data are transmitted together. Even the transmission of combined image signals does not always take the same time.
  • a non-equidistant image signal is based on an equidistant image signal, which must be derived from the non-equidistant image signal for the purpose of displaying or processing the image signal.
  • An example of a non-equidistant image signal are signals that have been compressed according to the MPEG standard.
  • the problem on which the invention is based is to specify a further method according to which the equidistant image signals extracted from the non-equidistant image signals are synchronized with the properties of the data display device, in particular its timing, without using a FIFO memory or a second video memory.
  • Data display device that is to say its display unit or monitor, which offers decompressed image signals such that they can be displayed on the monitor with the time behavior of the data display device.
  • the image memory present in the decoder circuit for decoding the non-equidistant image signal, in which the equidistant image signal is stored, is used.
  • the decoder circuit is sent synchronization signals from the data display device, which indicate which image signal is to be displayed on the monitor and which cause the image signal to be transmitted to the data display device in accordance with the frequency of the data display device.
  • the data display device controls the circuit by means of a synchronization mechanism, which generates an equidistant image signal from the non-equidistant image signal, in such a way that that circuit is able to do that Generate equidistant image signal synchronized with the operation of the monitor.
  • FIG. 1 shows a block diagram of an arrangement by means of which incoming non-equidistant image signals are converted into equidistant image signals and is synchronized with the mode of operation of the monitor of the data display device
  • Figures 2 and 3 show a detailed representation of the arrangement provided that the transmission of the image signals takes place according to the MPEG standard
  • Figure 4 shows another embodiment of the arrangement.
  • the arrangement is supplied with, for example, MPEG video signals MD and decoded in a known decoder circuit DEC.
  • the decoder circuit DEC also contains an image memory which at least also contains the current image to be displayed on a monitor MO, in addition to other images which are required in order to recover the current image. Methods for decoding these image signals are known; they result, for example, for the MPEG standard from VLSI implementation of MPEG decoders on pages 165 to 171.
  • the decoder circuit DEC generates, from the MPEG video signals MD, equidistant image signals B which are stored in the image memory or video memory VSP of the Data display device can be cached or passed on directly to the screen.
  • the image signals must be fed from the image memory VSP to the monitor MO in an equidistant form and in accordance with its time behavior, in FIG. 1 as image signals RGB2.
  • This takes advantage of the fact that the images generated there must be stored in the decoder circuitry DEC, since this is necessary in order to decompress the images compressed according to the standard and to produce them in equidistant form.
  • the result is that only by the Synchronisa ⁇ tion via the monitor control MST the image signals are offered to the monitor MO in such a way that the latter can also display the images without the need for additional memories.
  • FIGS. 2 and 3 differs from FIG. 1 in some respects.
  • the image signals M-D compressed according to the MPEG standard are decoded according to the MPEG standard in an arrangement FD, inversely quantized in an arrangement Q and inversely transformed DCT.
  • the pixels are generated in an arrangement BG and stored in the image memory BSP. From the images stored in the image memory BSP, the images are generated in an equi-distant form in accordance with the MPEG standard with the aid of an arrangement MP.
  • the interpolator IP which is in any case present in a decoder circuit, is used and is synchronized accordingly. This can e.g. via a video generator VG present at the data display device, which sends side synchronization signals S1 to the interpolator IP, which indicate when a new image section from the decoder circuit DEC must be given to the video generator VG.
  • Which image section is to be displayed on the monitor MO can be determined, for example, via a computer bus BUS. Every time a pixel B of the MPEG image on the monitor MO to be displayed, the video generator VG continues to send a pixel synchronization pulse S2 to the interpolator IP. This pixel synchronization pulse S2 indicates to the interpolator IP that it must transmit another pixel B to the video generator VG.
  • the image sections to be displayed on the monitor MO can be addressed in the image memory BSP of the decoder circuit and the time at which the individual pixels are transmitted to the video generator VG can also be determined.
  • the pixel synchronization pulses S2 that regulate the time behavior are then selected such that the transmission of the pixels is adapted to the time behavior of the data display device. This means that the adaptation to the behavior of the data display device takes place with the aid of synchronization, e.g. by the video generator VG using the image memory available in the decoder circuit, in which the current image to be displayed is always stored.
  • FIG. 3 also contains further arrangements which are not required for the method according to the invention, but which are present in a data display device which must display images which e.g. be delivered by a computer.
  • This includes an image memory VSP1, which is connected to the computer bus BUS, which leads to a computer.
  • a pixel generator BPG is provided, which generates the pixels from the signals supplied by the computer, which are stored in the pixel memory VSP1 so that they can be displayed on the monitor MO.
  • These units BPG and VSPl are, however, not required in the exemplary embodiment in FIG. 2 in order to generate the MPEG signals M-D as pictures after their decoding on the monitor MO.
  • pixels and image signals are denoted by B, addresses by A.
  • the arrangements IP, BSP, MP, BG, Q, FD, which form the decoder circuit, are known from the literature and can be found, for example, in the literature cited above.
  • the arrangements BPG, VSPl and VG are usually present in the data display devices.
  • the invention consists in that, by utilizing the existing arrangements or modules solely by means of a sensible synchronization, image signals which are not in a form which the monitor can process are offered to the monitor in such a way that they are displayed can.
  • the video signals RGB2 are applied to the monitor by the decoder DEC or video generator VG via a multiplexer Mux.
  • FIG. 1 The advantage of FIG. 1 is that, compared to FIGS. 2 to 4, no additional synchronization to the multiplexer MUX or video generator has to be established. The synchronization is necessary to indicate whether pixels from the pixel generator or from the video data stream are displayed on the monitor.

Abstract

During the transmission of video signals different standards are used to compress the images such that high-resolution images can also be transmitted. One example is the MPEG standard. When such images are to be displayed on the video terminal of a computer, they have to be adapted to the dynamic behaviour thereof. Therefore, on the receiver side, the compressed images have to be decompressed by means of a decoder circuit so that the original images are recreated. To this end, in addition to the actual image which is to be displayed, preceding or possibly subsequent images have to be stored temporarily in an image memory in the decoder circuit. In order to be able to display the images contained in the decoder circuit image memory on the video terminal, synchronization pulses (S1, S2) are generated in the video terminal. The first synchronization pulse (S1) indicates which image is to be displayed on the video terminal and the second synchronization pulse (S2) indicates at what moment the individual pixels of the image to be displayed are to be transmitted to the video terminal.

Description

Beschreibungdescription
Verfahren zur Darstellung von in nicht äquidistanter Form übertragenen Bildsignalen auf einem Datensichtgerät, das nur äquidistante Bildsignale anzeigtMethod for displaying image signals transmitted in non-equidistant form on a data display device that only displays equidistant image signals
Daten, z.B. Bildsignale, werden heute entsprechend unter¬ schiedlicher Standards (z.B. MPEG1 oder MPEG2) vor der Über¬ tragung komprimiert, anschließend übertragen und dann wieder so aufbereitet, daß sie von einem Datensichtgerät dargestellt werden können. Dabei besteht das Problem, daß die übertrage¬ nen Bildsignale nicht äquidistant sind, das Datensichtgerät aber nur äquidistante Bildersignale darstellen kann. Ein äquidistantes Bildsignal ist dabei ein Signal, bei dem für jeden Bildpunkt dieselbe Datenmenge übertragen wird und bei dem für die Übertragung der für jeden Bildpunkt nötigen Daten dieselbe Zeit verwendet wird. Ein Beispiel für ein äquidi¬ stantes Bildsignal ist das heute zur Übertragung von Fernseh¬ bilder verwendete PAL-Verfahren oder die RGB2-Ansteuerung eines Datensichtgerätes. Dementsprechend ist ein nicht äqui¬ distantes Bildsignal ein Signal, bei dem je Bildpunkt eine andere Menge von Daten übertragen wird. Zur Übertragung von nichtäquidistanten Bildsignalen werden Bildpunkte zusammenge¬ faßt und deren Daten zusammen übertragen. Selbst die Übertra- gung zusammengefaßter Bildsignale benötigt nicht immer die¬ selbe Zeit. Eine nicht äquidistanten Bildsignal liegt ein äquidistantes Bildsignal zugrunde, das zum Zwecke der Dar¬ stellung oder Verarbeitung des Bildsignales aus dem nich¬ täquidistanten Bildsignal wieder abgeleitet werden muß. Ein Beispiel für ein nichtäquidistantes Bildsignal sind Signale, die nach dem MPEG-Standard komprimiert worden sind.Data, e.g. Image signals are today compressed according to different standards (e.g. MPEG1 or MPEG2) before transmission, then transmitted and then processed again so that they can be displayed by a data display device. The problem here is that the transmitted image signals are not equidistant, but the data display device can only display equidistant image signals. An equidistant image signal is a signal in which the same amount of data is transmitted for each pixel and in which the same time is used for the transmission of the data required for each pixel. An example of an equidistant image signal is the PAL method used today for the transmission of television images or the RGB2 control of a data display device. Accordingly, a non-equi-distant image signal is a signal in which a different amount of data is transmitted for each pixel. To transmit non-equidistant image signals, pixels are combined and their data are transmitted together. Even the transmission of combined image signals does not always take the same time. A non-equidistant image signal is based on an equidistant image signal, which must be derived from the non-equidistant image signal for the purpose of displaying or processing the image signal. An example of a non-equidistant image signal are signals that have been compressed according to the MPEG standard.
Aus EP 0500 147 A2 ist ein Verfahren zur Ansteuerung eines Monitors und eine Monitorsteuerschaltung bekannt, die es ermöglicht, auf einem Datensichtgerät ein nichtäquidistantes Bildsignal darzustellen, das nach einem der bekannten Stan¬ dards komprimiert worden ist, obwohl die Betriebsweise des Datensichtgerätes nicht mit dem Bildsignal synchron ist, das aus dem nicht äquidistanten Bildsignal gewonnen werden kann. Dort wird vorgeschlagen, in der Monitorsteuerschaltung neben dem Video-Speicher einen FIFO-Speicher vorzusehen, der als Synchronisationsschnittstelle zwischen dem eingangsseitigen Bildsignal und dem Videospeicher des Datensichtgeräts verwen¬ det wird.From EP 0500 147 A2 a method for controlling a monitor and a monitor control circuit are known which make it possible to display a non-equidistant image signal on a data display device which has been compressed according to one of the known standards, although the mode of operation of the Data display device is not synchronized with the image signal, which can be obtained from the non-equidistant image signal. It is proposed there to provide a FIFO memory in the monitor control circuit in addition to the video memory, which is used as a synchronization interface between the input-side image signal and the video memory of the data display device.
Das der Erfindung zugrundeliegende Problem besteht darin, ein weiteres Verfahren anzugeben, nach dem ohne Verwendung eines FIFO-Speichers oder eines zweiten Videospeichers die aus den nicht äquidistanten Bildsignalen extrahierten äquidistanten Bildsignale mit den Eigenschaften des Datensichtgerätes, insbesondere dessen Zeitverhalten, synchronisiert wird.The problem on which the invention is based is to specify a further method according to which the equidistant image signals extracted from the non-equidistant image signals are synchronized with the properties of the data display device, in particular its timing, without using a FIFO memory or a second video memory.
Diese Aufgabe wird gemäß den Merkmalen des Patentanspruchs 1 gelöst.This object is achieved in accordance with the features of patent claim 1.
Das erfindungsgemäße Verfahren hat also den Vorteil, daß es ohne zusätzliche FIFO-Speicher auskommt und trotzdem demThe method according to the invention thus has the advantage that it does not require additional FIFO memory and nevertheless that
Datensichtgerät, also dessen Anzeigeeinheit oder Monitor, die dekomprimierten Bildsignale so anbietet, daß sie mit dem Zeitverhalten des Datensichtgerätes auf dem Monitor darge¬ stellt werden können. Dazu wird der in der Dekoderschaltung zur Dekodierung des nichtäquidistanten Bildsignales vorhan¬ dene Bildspeicher, in dem das äquidistante Bildsignal gespei¬ chert ist, herangezogen. Der Dekoderschaltung werden Synchro¬ nisationssignale vom Datensichtgerät zugesandt, die angeben, welches Bildsignal auf dem Monitor dargestellt werden soll und die bewirken, daß das Bildsignal entsprechend der Fre¬ quenz des Datensichtgerätes zum Datensichtgerät übertragen wird.Data display device, that is to say its display unit or monitor, which offers decompressed image signals such that they can be displayed on the monitor with the time behavior of the data display device. For this purpose, the image memory present in the decoder circuit for decoding the non-equidistant image signal, in which the equidistant image signal is stored, is used. The decoder circuit is sent synchronization signals from the data display device, which indicate which image signal is to be displayed on the monitor and which cause the image signal to be transmitted to the data display device in accordance with the frequency of the data display device.
Allgemein gesagt steuert das Datensichtgerät mittels eines Synchronisationsmechanismus die Schaltung, die aus dem nicht äquidistanten Bildsignal ein äquidistantes Bildsignal er¬ zeugt, derart an, daß jene Schaltung in der Lage ist, das erzeugte äquidistante Bildsignal mit der Betriebsweise des Monitors synchron zu gestalten.Generally speaking, the data display device controls the circuit by means of a synchronization mechanism, which generates an equidistant image signal from the non-equidistant image signal, in such a way that that circuit is able to do that Generate equidistant image signal synchronized with the operation of the monitor.
Anhand von Ausführungsbeispielen, die in den Figuren darge- stellt sind, wird die Erfindung weiter erläutert. Es zeigenThe invention is further explained on the basis of exemplary embodiments which are shown in the figures. Show it
Figur 1 ein Blockschaltbild einer Anordnung, durch die ankom¬ mende nicht äquidistante Bildsignale in äquidistante Bildsi¬ gnale umgewandelt werden und mit der Arbeitsweise des Moni- tors des Datensichtgerätes synchronisiert wird,1 shows a block diagram of an arrangement by means of which incoming non-equidistant image signals are converted into equidistant image signals and is synchronized with the mode of operation of the monitor of the data display device,
Figur 2 und 3 eine ausführliche Darstellung der Anordnung unter der Voraussetzung, daß die Übertragung der Bildsignale nach dem MPEG Standard erfolgt, Figur 4 eine weitere Ausführungsform der Anordnung.Figures 2 and 3 show a detailed representation of the arrangement provided that the transmission of the image signals takes place according to the MPEG standard, Figure 4 shows another embodiment of the arrangement.
Nach Figur 1 werden der Anordnung z.B. MPEG-Videosignale M-D zugeführt und in einer Decoderschaltung DEC bekannten Aufbaus dekodiert. In der Decoderschaltung DEC ist auch ein Bildspei¬ cher enthalten, der zumindest auch das aktuelle auf einem Monitor MO darzustellende Bild enthält, zusätzlich zu anderen Bildern, die erforderlich sind, um das aktuelle Bild wieder zu gewinnen. Verfahren zur Decodierung dieser Bildsignale sind bekannt, sie ergeben sich z.B. für den MPEG Standard aus VLSI-Implementation of MPEG Decoders Seite 165 bis 171. Die Decoderschaltung DEC erzeugt aus den MPEG Videosignalen M-D äquidistante Bildsignale B, die im Bildspeicher oder Video¬ speicher VSP des Datensichtgerätes zwischengespeichert oder direkt an den Bildschirm weitergegeben werden können. In ersteren Fall müssen aus dem Bildspeicher VSP dem Monitor MO die Bildsignale in äquidistanter Form und entsprechend seinen Zeitverhalten hinzugeführt werden, in Figur 1 als Bildsignale RGB2. Die Synchronisation S zwischen den von der Decoder¬ schaltung DEC erzeugten äquidistanten Bildsignalen mit den Bildsignalen RGB2, die vom Monitor MO dargestellt werden können, erfolgt mit Hilfe einer Monitorsteuerung MST, die veranlaßt, daß aus der Decoderschaltung DEC die auf dem Bildschirm darzustellenden Bilder zum Videospeicher VSP übertragen werden und zwar mit dem Zeitverhalten des Monitors MO. Dabei wird ausgenutzt, daß in der Decoderschalatung DEC die dort erzeugten Bilder gespeichert werden müssen, da dies notwendig ist, um die nach den Standard komprimierten Bilder wieder zu dekomprimieren und in äquidistanter Form zu erzeu¬ gen. Die Folge ist, daß ausschließlich durch die Synchronisa¬ tion über die Monitorsteuerung MST die Bildsignale dem Moni¬ tor MO derart angeboten werden, daß dieser die Bilder auch darstellen kann, ohne daß zusätzliche Speicher dazu vorhanden sein müssen.According to FIG. 1, the arrangement is supplied with, for example, MPEG video signals MD and decoded in a known decoder circuit DEC. The decoder circuit DEC also contains an image memory which at least also contains the current image to be displayed on a monitor MO, in addition to other images which are required in order to recover the current image. Methods for decoding these image signals are known; they result, for example, for the MPEG standard from VLSI implementation of MPEG decoders on pages 165 to 171. The decoder circuit DEC generates, from the MPEG video signals MD, equidistant image signals B which are stored in the image memory or video memory VSP of the Data display device can be cached or passed on directly to the screen. In the former case, the image signals must be fed from the image memory VSP to the monitor MO in an equidistant form and in accordance with its time behavior, in FIG. 1 as image signals RGB2. The synchronization S between the equidistant image signals generated by the decoder circuit DEC with the image signals RGB2, which can be displayed by the monitor MO, takes place with the aid of a monitor control MST, which causes the images to be displayed on the screen from the decoder circuit DEC to the video memory VSP are transmitted with the time behavior of the monitor MO. This takes advantage of the fact that the images generated there must be stored in the decoder circuitry DEC, since this is necessary in order to decompress the images compressed according to the standard and to produce them in equidistant form. The result is that only by the Synchronisa ¬ tion via the monitor control MST the image signals are offered to the monitor MO in such a way that the latter can also display the images without the need for additional memories.
Eine ausführlichere Darstellung zeigt Figur 2 und 3, die sich von Figur 1 in einigen Punkten unterscheidet. Bei Figur 2 und 3 wird davon ausgegangen, daß die ankommenden Bildsignale nach dem MPEG-Standard behandelt worden sind. Dieser kann z.B. der zitierten Literaturstelle entnommen werden und ist dem Fachmann auch bekannt. Die nach dem MPEG-Standard kompri¬ mierten Bildsignale M-D werden entsprechend dem MPEG-Standard in einer Anordnung FD dekodiert, in einer Anordnung Q invers quantisiert und invers DCT transformiert. In einer Anordnung BG werden die Bildpunkte erzeugt und im Bildspeicher BSP gespeichert. Aus den im Bildspeicher BSP gespeicherten Bil¬ dern werden mit Hilfe einer Anordnung MP die Bilder in äqui¬ distanter Form entsprechend dem MPEG-Standard wieder erzeugt. Die Bilder müssen nun dem Monitor MO so zugeführt werden, wie er sie darstellen kann. Dazu wird der bei einer Decoderschal¬ tung sowieso vorhandene Interpolator IP verwendet, der ent¬ sprechend synchronisiert wird. Dies kann z.B. über einen beim Datensichtgerät vorhandenen Videogenerator VG erfolgen, der Seitensynchronisationssignale Sl an den Interpolator IP sendet, die angeben, wann ein neuer Bildausschnitt von der Dekoderschaltung DEC an den Videogenerator VG gegeben werden müssen.A more detailed illustration is shown in FIGS. 2 and 3, which differs from FIG. 1 in some respects. In Figures 2 and 3 it is assumed that the incoming image signals have been treated according to the MPEG standard. This can e.g. are taken from the cited reference and is also known to the person skilled in the art. The image signals M-D compressed according to the MPEG standard are decoded according to the MPEG standard in an arrangement FD, inversely quantized in an arrangement Q and inversely transformed DCT. The pixels are generated in an arrangement BG and stored in the image memory BSP. From the images stored in the image memory BSP, the images are generated in an equi-distant form in accordance with the MPEG standard with the aid of an arrangement MP. The images must now be fed to the monitor MO as they can represent them. For this purpose, the interpolator IP, which is in any case present in a decoder circuit, is used and is synchronized accordingly. This can e.g. via a video generator VG present at the data display device, which sends side synchronization signals S1 to the interpolator IP, which indicate when a new image section from the decoder circuit DEC must be given to the video generator VG.
Welcher Bildausschnitt auf dem Monitor MO dargestellt werden soll, kann z.B. über einen Computerbus BUS festgelegt werden. Jedesmal, wenn ein Bildpunkt B des MPEG-Bildes am Monitor MO dargestellt werden soll, sendet weiterhin der Video-Generator VG einen Bildpunkt-Synchronisationsimpuls S2 an den Interpo¬ lator IP. Dieser Bildpunkt-Synchronisatonsimpuls S2 zeigt dem Interpolator IP an, daß er einen weiteren Bildpunkt B an den Videogenerator VG übertragen muß.Which image section is to be displayed on the monitor MO can be determined, for example, via a computer bus BUS. Every time a pixel B of the MPEG image on the monitor MO to be displayed, the video generator VG continues to send a pixel synchronization pulse S2 to the interpolator IP. This pixel synchronization pulse S2 indicates to the interpolator IP that it must transmit another pixel B to the video generator VG.
Durch diese Synchronisierung durch den Videogenerator VG des Datensichtgerätes können die auf den Monitor MO darzustellen¬ den Bildausschnitte im Bildspeicher BSP der Decoderschaltung adressiert werden und weiterhin der Zeitpunkt festgelegt werden, zu dem die einzelnen Bildpunkte zum Videogenerator VG übertragen werden. Die Bildpunkt-Synchronisationsimpulse S2, die das Zeitverhalten regeln, sind dann derart gewählt, daß die Übertragung der Bildpunkte dem Zeitverhalten des Daten- Sichtgerätes angepaßt ist. Das heißt, die Anpassung an das Verhalten des Datensichtgerätes erfolgt mit Hilfe der Syn¬ chronisation, z.B. durch den Videogenerator VG unter Verwen¬ dung des in der Decoderschaltung vorhandenen Bildspeichers, in dem immer auch das aktuelle Bild, das dargestellt werden soll, gespeichert ist.As a result of this synchronization by the video generator VG of the data display device, the image sections to be displayed on the monitor MO can be addressed in the image memory BSP of the decoder circuit and the time at which the individual pixels are transmitted to the video generator VG can also be determined. The pixel synchronization pulses S2 that regulate the time behavior are then selected such that the transmission of the pixels is adapted to the time behavior of the data display device. This means that the adaptation to the behavior of the data display device takes place with the aid of synchronization, e.g. by the video generator VG using the image memory available in the decoder circuit, in which the current image to be displayed is always stored.
In Figur 3 sind noch weitere Anordnungen enthalten, die für das erfindungsgemäße Verfahren nicht erforderlich sind, die jedoch bei einem Datensichtgerät vorhanden sind, das Bilder darstellen muß, die z.B. von einem Rechner geliefert werden. Dazu gehören ein Bildspeicher VSP1, der mit dem Computerbus BUS verbunden ist, der zu einem Rechner führt. Weiterhin ist ein Bildpunktgenerator BPG vorgesehen, der aus den vom Rech¬ ner gelieferten Signalen die Bildpunkte erzeugt, die in dem Bildpunktspeicher VSP1 gespeichert werden, um auf dem Monitor MO dargestellt werden zu können. Diese Einheiten BPG und VSPl sind allerdings im Ausführungsbeispiel der Figur 2 nicht erforderlich, um die MPEG-Signale M-D nach ihrer Dekodierung auf dem Monitor MO als Bilder zu erzeugen.FIG. 3 also contains further arrangements which are not required for the method according to the invention, but which are present in a data display device which must display images which e.g. be delivered by a computer. This includes an image memory VSP1, which is connected to the computer bus BUS, which leads to a computer. Furthermore, a pixel generator BPG is provided, which generates the pixels from the signals supplied by the computer, which are stored in the pixel memory VSP1 so that they can be displayed on the monitor MO. These units BPG and VSPl are, however, not required in the exemplary embodiment in FIG. 2 in order to generate the MPEG signals M-D as pictures after their decoding on the monitor MO.
In den Figuren sind Bildpunkte und Bildsignale mit B, Adres¬ sen mit A bezeichnet. Die Anordnungen IP, BSP, MP, BG, Q, FD, die die Dekoderschal¬ tung bilden, sind aus der Literatur bekannt und können z.B. der oben angegebenen Literaturstelle entnommen werden. Die Anordnungen BPG, VSPl und VG sind bei den Datensichtgeräten üblicherweise vorhanden. Die Erfindung besteht darin, daß unter Ausnutzung der vorhandenen Anordnungen oder Module allein durch eine sinnvolle Synchronisation erreicht wird, daß Bildsignale, die nicht in einer Form vorliegen, wie sie der Monitor verarbeiten kann, so dem Monitor angeboten wer- den, daß er sie darstellen kann.In the figures, pixels and image signals are denoted by B, addresses by A. The arrangements IP, BSP, MP, BG, Q, FD, which form the decoder circuit, are known from the literature and can be found, for example, in the literature cited above. The arrangements BPG, VSPl and VG are usually present in the data display devices. The invention consists in that, by utilizing the existing arrangements or modules solely by means of a sensible synchronization, image signals which are not in a form which the monitor can process are offered to the monitor in such a way that they are displayed can.
Bei Figur 4 werden die Videosignale RGB2 vom Dekoder DEC oder Videogenerator VGüber einen Multiplexer Mux an den Monitor gelegt.In FIG. 4, the video signals RGB2 are applied to the monitor by the decoder DEC or video generator VG via a multiplexer Mux.
Vorteil der Figur 1 ist, daß im Vergleich zu den Figuren 2 bis 4 keine zusätzliche Synchronisation zum Multiplexer MUX bzw. Video-Generator hergestellt werden muß. Die Synchronisa¬ tion ist notwendig um anzugeben, ob Bildpunkte vom Bildpunkt- generator oder vom Video-Datenstrom auf dem Monitor darge¬ stellt werden.The advantage of FIG. 1 is that, compared to FIGS. 2 to 4, no additional synchronization to the multiplexer MUX or video generator has to be established. The synchronization is necessary to indicate whether pixels from the pixel generator or from the video data stream are displayed on the monitor.
Vorteil der Lösungen nach Figur 2 bis 4 ist aber, daß der Video-Datenstrom nicht im Bildspeicher abgelegt werden muß, was die Datenübertragung anderer Bildsignale auf den Bild¬ speicher immens entlastet.The advantage of the solutions according to FIGS. 2 to 4 is, however, that the video data stream does not have to be stored in the image memory, which immensely relieves the data transmission of other image signals to the image memory.
Bei Lösung nach Figur 4 wird auf den existierenden Video- Generator zurückgegriffen. In the solution according to FIG. 4, the existing video generator is used.

Claims

Patentansprüche claims
1. Verfahren zur Darstellung von in nicht äquidistanter Form übertragenen Bildsignalen auf einem Datensichtgerät, das nur äquidistante Bildsignale anzeigt,1. Method for displaying image signals transmitted in non-equidistant form on a data display device that only displays equidistant image signals,
-bei dem die nicht äquidistanten Bildsignale durch eine Deko¬ derschaltung (DEC) in äquidistante Bildsignale dekodiert werden und in einem Bildspeicher (BSP) der Dekoderschaltung abgespeichert werden, - bei dem das Datensichtgerät zur Dekoderschaltung einenin which the non-equidistant image signals are decoded into equidistant image signals by a decoder circuit (DEC) and are stored in an image memory (BSP) of the decoder circuit, - in which the visual display unit for decoder circuitry
Seitensnchronisationsimpuls (Sl) sendet, der ein vom Daten¬ sichtgerät darzustellendes Bild addressiert,Sends side synchronization pulse (S1), which addresses an image to be displayed by the data display device,
- bei dem die Dekoderschaltung entsprechend dem Seitensyn¬ chronisationsimpuls (Sl) das Bild im Bildspeicher (BSP) der Dekoderschaltung addressiert,in which the decoder circuit addresses the image in the image memory (BSP) of the decoder circuit in accordance with the page synchronization pulse (S1),
- bei dem das Datensichtgerät einen Bildpunkt- Synchronisati¬ onsimpuls (S2) an die Dekoderschaltung sendet, das den Zeit¬ punkt der Übertragung der Bildpunkte des darzustellenden Bildes zum Datensichtgerät festlegt, - und bei dem die Dekoderschaltung das Bild entsprechend dem Bildpunkt-Synchronisationsimpuls (S2) zeitgerecht an das Datensichtgerät überträgt.- in which the data display device sends a pixel synchronization pulse (S2) to the decoder circuit, which determines the point in time at which the pixels of the image to be displayed are transmitted to the data display device, - and in which the decoder circuit converts the image to the pixel synchronization pulse (S2 ) transferred to the visual display device in good time.
2. Verfahren nach Anspruch 1, bei den zur Erzeugung der Synchronisationsimpulse (Sl, S2) der Videogenerator (VG) des Datensichtgerätes verwendet wird.2. The method according to claim 1, in which the video generator (VG) of the data display device is used to generate the synchronization pulses (S1, S2).
3. Verfahren nach Anspruch 1 oder 2,3. The method according to claim 1 or 2,
-bei dem die nichtäquidistanten Bildsignale gemäß dem MPEG- Standard codiert sind,-in which the non-equidistant image signals are encoded according to the MPEG standard,
-bei dem nach der Dekodierung die Bildsignale zu Bildern im Bildspeicher (BSP) der Dekoderschaltung gespeichert werden,in which, after decoding, the image signals for images are stored in the image memory (BSP) of the decoder circuit,
- und bei dem ein Interpolator (IP) von den Synchronisation¬ simpulsen so angesteuert wird, daß dieser die auf dem Daten- Sichtgerät darzustellenden Bilder im Bildspeicher (BSP) der Dekoderschaltung addressiert und zeitgerecht entsprechend dem Zeitverhalten des Datensichtgerätes zu diesem übertragt. - And in which an interpolator (IP) is controlled by the synchronization pulses so that it addresses the images to be displayed on the data display device in the image memory (BSP) of the decoder circuit and transmits them to the display device in a timely manner in accordance with the timing of the data display device.
PCT/DE1996/000191 1995-02-16 1996-02-07 Method of displaying video signals transmitted in a non-equidistant form on a video terminal which only displays equidistant video signals WO1996025732A1 (en)

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EP0847038A2 (en) * 1996-12-09 1998-06-10 STMicroelectronics, Inc. Rendering an audio-visual stream synchronized by a software clock in a personal computer

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US5027212A (en) * 1989-12-06 1991-06-25 Videologic Limited Computer based video/graphics display system
EP0572024A2 (en) * 1992-05-27 1993-12-01 Kabushiki Kaisha Toshiba Multimedia display control system for storing image data in frame buffer

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Publication number Priority date Publication date Assignee Title
US5027212A (en) * 1989-12-06 1991-06-25 Videologic Limited Computer based video/graphics display system
EP0572024A2 (en) * 1992-05-27 1993-12-01 Kabushiki Kaisha Toshiba Multimedia display control system for storing image data in frame buffer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0847038A2 (en) * 1996-12-09 1998-06-10 STMicroelectronics, Inc. Rendering an audio-visual stream synchronized by a software clock in a personal computer
EP0847038A3 (en) * 1996-12-09 1999-11-03 STMicroelectronics, Inc. Rendering an audio-visual stream synchronized by a software clock in a personal computer

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