WO1996002886A1 - Appareil a microprocesseur sans interruptions dote d'un moyen de synchronisation au passage par zero du chargement de donnees - Google Patents

Appareil a microprocesseur sans interruptions dote d'un moyen de synchronisation au passage par zero du chargement de donnees Download PDF

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Publication number
WO1996002886A1
WO1996002886A1 PCT/US1995/009023 US9509023W WO9602886A1 WO 1996002886 A1 WO1996002886 A1 WO 1996002886A1 US 9509023 W US9509023 W US 9509023W WO 9602886 A1 WO9602886 A1 WO 9602886A1
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WO
WIPO (PCT)
Prior art keywords
signal
terminal
data
chip select
state
Prior art date
Application number
PCT/US1995/009023
Other languages
English (en)
Inventor
Robert D. Juntunen
Original Assignee
Honeywell Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inc. filed Critical Honeywell Inc.
Publication of WO1996002886A1 publication Critical patent/WO1996002886A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423—Input/output
    • G05B19/0425—Safety, monitoring
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/21—Pc I-O input output
    • G05B2219/21136—Detection of zero crossing for command and maximum for reading value
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/25—Pc structure of the system
    • G05B2219/25042—Clock derived from power supply

Definitions

  • the invention described herein relates generally to microprocessor apparatus which implements zero crossing synchronization of data output and input, and more specifically to an alternating current load controller including microprocessor apparatus of non-interrupt architecture in which data is written and read in synchronism with zero crossings of the applied power with minimum program and/or hardware overhead.
  • Digital logic and signal processing apparatus which is very commonly used to provide switching control signals and perform other functions, is particularly susceptible to the effects of noise generated by switching alternating load currents at times other than zero crossings. Among other effects, such noise may adversely affect high resolution A/D conversions, and may introduce spurious signals which cause other digital signal processing errors. Thus, it is highly desirable to transmit switching control signals in synchronism with zero crossings. Likewise, it is highly desirable to read digital data only during zero crossings to eliminate errors resulting from noise caused by system loads other than those controlled by the digital signal processing apparatus in issue.
  • FIG. 1 A typical conventional microprocessor based system is shown in Figure 1 in which reference numeral 10 identifies a microprocessor of interrupt based architecture. Serial/parallel output and parallel/serial input buffers, respectively identified by reference numerals 11 and 12, are connected in series through D out and D m terminals thereon between Data Out and Data In pins 13 and 14 respectively on microprocessor 10.
  • microprocessor 10 includes Clock and Chip Select pins 15 and 16 respectively which are connected to corresponding terminals on output and input buffers 11 and 12.
  • Microprocessor 10 and output and input buffers 11 and 12 are implemented to serially circulate data at a rate determined by the repetition rate of a "clock" signal on pin 15.
  • a "chip select” signal functions to selectively activate output and input serial registers in the desired buffers in a system which contains multiple output and input buffers. It also enhances noise immunity by deactivating the registers when outputs to or inputs from external sources are not expected.
  • Output and input buffers 1 1 and 12 include parallel data output and input terminals 17 and 18 respectively which are connected to system components requiring control signals or providing input data.
  • output terminals 17 may be connected to drivers for load switching apparatus.
  • Terminals 18 may be connected to receive data signals from sensors, status monitors or other data processors.
  • control signals be latched out or loaded from terminals 17 to the associated utilization apparatus only at or near the zero crossings of applied electric power.
  • input signals provided to terminals 18 be accepted only at zero crossings.
  • Conventional microprocessor 10 conveniently accommodates this function by receiving a "zero crossing" signal at an Input pin 19, and producing a "load” signal at an Output pin 20 which is connected to corresponding Load terminals on buffers 11 and 12.
  • the "zero crossing" signal is produced by a zero crossing detector 21 which monitors the alternating electric energization and produces a digital signal which changes state in synchronism with the zero crossings of the energization.
  • the architecture of microprocessor 10 is such that the zero crossing signal is continuously monitored, and, when an output state change or loading of input data is required, normal program execution is interrupted at a zero crossing to provide a "load” signal at pin 20.
  • a non-interrupt type micro-processor it is possible in a non-interrupt type micro-processor to employ pins and data processing capability to implement data loading in synchronism with zero crossings. This would entail execution of a series of specific tasks which must be completed before a zero crossing input could be recognized. In complex systems where the operating system is taxed by other tasks, the resultant time delay could be sufficient to effectively prohibit data latching at or near a zero crossing. The problem is compounded where multiple control outputs and/or multiplexing of digital inputs is involved. Although a microprocessor can arrange the tasks according to a priority table as a work around to this limitation, when a large number of outputs is involved and/or short cycling is needed, valuable processing time is unduly tied up.
  • the invention is a circuit for loading data in synchronism with an AC signal in apparatus implemented with a microprocessor of non-interrupt architecture, the apparatus including a microprocessor and at least one buffer connected by "data in”,
  • the circuit includes logic means operable to (1) hold the signal at the "load” terminal at its last previous state when the signal supplied to the "chip select” terminal is of a first state, (2) force a signal of the first state at the "load” terminal when the signal at the "chip select” terminal changes from its first state to its second state, and (3) change the signal at the "load” terminal from its first state to its second state following transition of the signal at the "chip select” terminal from its second state to its first state and upon changing of the state of a signal at the "zero crossing” terminal.
  • the "chip select", “load” and “zero crossing” terminals of the logic means are connected to the “chip select” and “load” terminals of the buffer and means for supplying a signal which changes state in synchronism with the AC signal, respectively.
  • the logic means may include first and second D clocked flip-flops, each having a “reset” terminal connected to receive a signal which changes state with changes in the state of the signal on the "chip select” line.
  • the first and second flip-flops also have "clock” terminals connected to respectively receive inverted and non-inverted forms of the zero crossing signal, and "Q" terminals connected to inputs of an OR logic element whose output is connected to the "load” terminal of the buffer.
  • the applicant has provided for loading data in synchronism with an AC signal in microprocessor apparatus implemented with a low cost, high performance microprocessor of non-interrupt architecture, thereby providing various advantages over conventional interrupt type microprocessor apparatus.
  • Figure 1 is a block diagram of a conventional microprocessor based control system incorporating interrupt microprocessor architecture.
  • Figure 2 is a block diagram of a microprocessor based control system incorporating non-interrupt microprocessor architecture and logic means for achieving data loading in synchronism with an AC signal.
  • Figure 3 is a circuit diagram of data synchronization logic means incorporated into the control system of Figure 3.
  • Figure 4 is a truth table for D clocked flip-flops used in the logic means of Figure 3.
  • Non-interrupt type microprocessor 10 ' is shown with no ports corresponding to Input and Output ports 19 and 20 in Figure 1.
  • the functions performed by these ports and the program routines implemented in microprocessor 10 of Figure 1 are performed by a logic circuit identified by reference numeral 24 in Figure 2.
  • Logic circuit 24 includes a CS terminal connected to the chip select line, a ZC terminal which is supplied with the digital output signal of zero crossing detector 21 and a Load terminal connected to the "Load" terminals of output and input buffers 17 and 18.
  • logic circuit 24 is implemented with a pair of D clocked flip- flops 28 and 29, each having Clk, Data and Reset input terminals and a Q output terminal.
  • Flip-flops 28 and 29 operate according to the truth table of Figure 4.
  • the Data terminals are set or maintained at a logic "1" level.
  • logic circuit 24 is compatible with protocol used in the Motorola Synchronous Serial Peripheral Interface (SPI) and Toshiba Neuron chip NeuroWire serial communications in which the output and input serial registers in buffers 11 and 12 are activated by the "chip select" signal transition from a logic “ 1 " level to a logic “0” level, and so long thereafter as the "chip select” signal remains at the logic “0” level.
  • SPI Synchronous Serial Peripheral Interface
  • MISR11 Reference Manual published by Motorola Inc., 1991, for a full description of this interface and communications protocol and apparatus in which it is used.
  • terminal 25 of logic circuit 24 is connected to the Reset terminals of flip-flops 28 and 29 through an inverter 30.
  • Terminal 26 is connected directly to the Clk terminal of flip-flop 28, and through an inverter 31 to the Clk terminal of flip-flop 29.
  • the Q output terminals of flip-flops 28 and 29 are connected to the inputs of an OR logic element 32 whose output forms output terminal 27 of logic circuit 24.
  • the above-described circuit provides the following logic operation.
  • the "chip select" signal Prior to the start of a serial transmission, the "chip select" signal is at a logic “1" level, the "load” or “latch” output on terminal 27 is held at its last previous state.
  • the signals at the Q outputs of the flip-flops are at opposite logic levels. Accordingly, one of these outputs is at a logic "1" level, which results in the output of OR logic element 32 being at a logic "1" level.
  • the chip select signal transitions from a logic “ 1 " level to a logic “0” level. Accordingly, a logic “ 1 " level signal is supplied to the Reset terminals of both flip-flops 28 and 29, which forces the "Q" output signals of both flip-flops to a logic “0” level. All other inputs to the flip-flops are ignored during this interval. Since the Q outputs of both flip-flops are at a logic "0" level, the signal on terminal 27 is also at a logic "0" level. Following the period for serial transmission, the chip select signal transitions from a logic "0" level to a logic "1" level.
  • the rising edge of the "chip select" signal produces a logic "0" level at the Reset terminals of flip-flops 28 and 29. This does not change any flip-flop states. Both Q signals remain at a logic “0" level, but all other flip- flop inputs become active. Sometime later a zero crossing transition edge will be produced by zero crossing detector circuit 21. For a 60 Hz AC signal, the maximum time delay is 8.3 ms.
  • the transition in the "zero crossing” signal is transmitted in non- inverted form to the Clk terminal of flip-flop 28 and in inverted form to the Clk terminal of flip-flop 29, which results in a rising edge signal transition at the Clk terminal of one or the other of the flip-flops. This causes the logic " 1 " level signal at the Data terminal of that flip-flop to be clocked through to the Q output terminal, thus producing a logic "1 " level signal on Load terminal 27.
  • the applicant's invention provides for zero crossing synchronized loading or latching of data in apparatus employing a microprocessor of non-interrupt architecture. Concurrently, the microprocessor hardware and program are relieved of all tasks related to zero crossing synchronization.
  • the invention is characterized by simple and inexpensive implementation, thus achieving the desired function with minimum program and/or hardware overhead.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • General Engineering & Computer Science (AREA)
  • Bus Control (AREA)

Abstract

Contrôleur de charge de courant alternatif dans lequel les données sont transmises en série depuis un microprocesseur du type sans interruptions et sont mises en circulation dans des tampons d'entrée et de sortie de données en parallèle connectés en série. Le chargement des données au niveau des terminaux de données en parallèle des tampons d'entrée et de sortie est synchronisé avec les passages par zéro du courant alternatif par un circuit logique qui envoie des commandes de charge aux tampons en fonction de la synchronisation des signaux d'entrée de sélection de circuit et de passage par zéro.
PCT/US1995/009023 1994-07-18 1995-07-18 Appareil a microprocesseur sans interruptions dote d'un moyen de synchronisation au passage par zero du chargement de donnees WO1996002886A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US27622994A 1994-07-18 1994-07-18
US08/276,229 1994-07-18

Publications (1)

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WO1996002886A1 true WO1996002886A1 (fr) 1996-02-01

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0773601A2 (fr) 1995-11-13 1997-05-14 Anton Wermelinger Connexion enfichable de sécurité
CN102591234A (zh) * 2012-02-20 2012-07-18 成都电业局 一种基于单片机的双输入bcd编码器

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3651477A (en) * 1970-06-18 1972-03-21 Struthers Dunn Process control system
US4328539A (en) * 1978-07-28 1982-05-04 Amf Incorporated Sequence controller with microprocessor
WO1987007456A1 (fr) * 1986-05-21 1987-12-03 La Telemecanique Electrique Procede et dispositif de commande d'un electro-aimant dont l'excitation, par un courant periodique monoarche, provoque l'actionnement d'une piece mobile

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3651477A (en) * 1970-06-18 1972-03-21 Struthers Dunn Process control system
US4328539A (en) * 1978-07-28 1982-05-04 Amf Incorporated Sequence controller with microprocessor
WO1987007456A1 (fr) * 1986-05-21 1987-12-03 La Telemecanique Electrique Procede et dispositif de commande d'un electro-aimant dont l'excitation, par un courant periodique monoarche, provoque l'actionnement d'une piece mobile

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0773601A2 (fr) 1995-11-13 1997-05-14 Anton Wermelinger Connexion enfichable de sécurité
CN102591234A (zh) * 2012-02-20 2012-07-18 成都电业局 一种基于单片机的双输入bcd编码器

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