WO1995027939A1 - Processeur de simulation d'instruments de musique - Google Patents

Processeur de simulation d'instruments de musique Download PDF

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Publication number
WO1995027939A1
WO1995027939A1 PCT/US1995/004354 US9504354W WO9527939A1 WO 1995027939 A1 WO1995027939 A1 WO 1995027939A1 US 9504354 W US9504354 W US 9504354W WO 9527939 A1 WO9527939 A1 WO 9527939A1
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WIPO (PCT)
Prior art keywords
memory
processor
value
digital signal
values
Prior art date
Application number
PCT/US1995/004354
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English (en)
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WO1995027939B1 (fr
Inventor
Bryan J. Colvin, Sr.
Daniel B. Gochnauer
Perry R. Cook
Original Assignee
Media Vision, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Media Vision, Inc. filed Critical Media Vision, Inc.
Priority to AU22439/95A priority Critical patent/AU2243995A/en
Publication of WO1995027939A1 publication Critical patent/WO1995027939A1/fr
Publication of WO1995027939B1 publication Critical patent/WO1995027939B1/fr

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Classifications

    • G—PHYSICS
    • G10—MUSICAL INSTRUMENTS; ACOUSTICS
    • G10H—ELECTROPHONIC MUSICAL INSTRUMENTS; INSTRUMENTS IN WHICH THE TONES ARE GENERATED BY ELECTROMECHANICAL MEANS OR ELECTRONIC GENERATORS, OR IN WHICH THE TONES ARE SYNTHESISED FROM A DATA STORE
    • G10H7/00—Instruments in which the tones are synthesised from a data store, e.g. computer organs
    • G10H7/002—Instruments in which the tones are synthesised from a data store, e.g. computer organs using a common processing for different operations or calculations, and a set of microinstructions (programme) to control the sequence thereof
    • G10H7/004—Instruments in which the tones are synthesised from a data store, e.g. computer organs using a common processing for different operations or calculations, and a set of microinstructions (programme) to control the sequence thereof with one or more auxiliary processor in addition to the main processing unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
    • G06F15/7857—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers) using interleaved memory
    • G—PHYSICS
    • G10—MUSICAL INSTRUMENTS; ACOUSTICS
    • G10H—ELECTROPHONIC MUSICAL INSTRUMENTS; INSTRUMENTS IN WHICH THE TONES ARE GENERATED BY ELECTROMECHANICAL MEANS OR ELECTRONIC GENERATORS, OR IN WHICH THE TONES ARE SYNTHESISED FROM A DATA STORE
    • G10H2250/00—Aspects of algorithms or signal processing methods without intrinsic musical character, yet specifically adapted for or used in electrophonic musical processing
    • G10H2250/131—Mathematical functions for musical analysis, processing, synthesis or composition
    • G10H2250/211—Random number generators, pseudorandom generators, classes of functions therefor

Definitions

  • This invention relates to digital signal
  • processors to methods for generating digital sound signals, and to using parallel processors to execute, without pipeline delays, sound synthesis models that simulate the sounds of musical instruments.
  • a digital synthesizer typically generates a series of digital values which represent sound amplitudes at a series of discrete sampling times. Feeding the series of values through a digital-to-analog converter (DAC) or a coder-decoder (CODEC) to an amplifier and then to speakers produces sound.
  • DAC digital-to-analog converter
  • CDEC coder-decoder
  • Synthesizers use many synthesis methods to produce sounds that emulate the sounds of musical instruments.
  • One of the most accurate methods for emulating a musical instrument is playing a recording of the instrument. This is called sample synthesis and is commonly used in drum machines.
  • sample synthesis cannot practically mimic every musical instrument because some instruments produce many different sounds, and storing digital recordings of every sound requires too much memory. Accordingly, synthesis models have been developed which use
  • ADSR curves are amplitude envelopes which control the volume and duration of notes.
  • a synthesizer may generate a series of steady state sound amplitude values and then multiply each sound amplitude value by a corresponding value from an ADSR curve. The duration of the note depends on how quickly the ADSR curve goes to zero.
  • Wave table synthesis models musical instruments using two circular sound tables. One table represent sound harmonics during the attack. The other table represents the steady state. Two ADSR curves provide envelopes for the tables. For musical instruments that don't have a steady state, a third ADSR curve can be used to control filter parameters.
  • FM synthesis uses two or more ADSR curves that control sine wave generators which are frequency modulated to create a large spectrum of harmonics.
  • Wave guide synthesis emulates a musical instrument using models based on the physics of the instrument.
  • the wave guide models being based on a physical structure, are more intuitive for many developers of music instrument emulations.
  • the theory of lossless wave guides simplifies calculations needed to make modeling of many musical instruments achievable.
  • the Karplus Strong algorithm (Plucked String model) is a predecessor of wave guide synthesis models.
  • Synthesizers typically employ digital signal processors (DSPs) that execute software which
  • DSPs typically include math unite such as multipliers and summers which are fed data and model parameters from memory.
  • Data is often pipelined into the math unit, for example by decoding an instruction and fetching data for the next cycle of the math circuitry before the current cycle is complete. To avoid delays with a pipelined system, the new data is fed into the pipeline before the previous cycle is finished. If data required for the next cycle depends on the results of the current cycle, then the data is not ready when required and operation of the math unit is delayed until the required data travels through the pipeline. Accordingly, pipeline delays make DSPs slower because the math units have periods of
  • synthesizer architectures are needed which executed synthesis models without experiencing pipeline delays.
  • the current invention provides a DSP that is fast, relatively inexpensive, and well suited to implementing musical instrument simulations models such as wave guide models.
  • One embodiment of the present invention is a DSP that includes first and second processors which share a math unit. The two processors alternate controlling data input to the shared math unit, so that the shared math unit alternates between performing an arithmetic operation for the first processor and performing an arithmetic operation for the second processor. Results of the math unit processing for the first processor are stored while the math unit is processing data for the second processor, so that the results of the operation for the first processor are made ready for the math unit when the math unit begins the next operation for the first processor.
  • the first processor (often referred to as the foreground processor) executes a program which generates a sound amplitude value.
  • the second processor executes a program which generates a sound amplitude value.
  • processor preprocesses data from an external memory such as a DRAM, and stores the preprocessed data in a memory for use by the foreground processor.
  • the external memory is often used for storing look-up table values.
  • two processors control a multiplexer which supplies data to a math unit.
  • the math unit is a multiplier or a combined multiply-and-accumulate circuit.
  • Data is fed from the multiplexer through a set of flip-flops to the math unit. While the math unit is processing data for one of the two processors, the other processor selects the data supplied to input leads of the flip-flops. Math unit processing is not disturbed because signals from the flip-flops are not changed until the flip-flops' clock is triggered. Upon completion of processing by the math unit, new data from the multiplexer is loaded into the flip-flop set in response to a clock signal. The math unit begins operating for the second
  • processor and the first processor can change the data supplied through the multiplexer.
  • one or more memories provide input data to the multiplexer. If the access time of a memory is less that half the processing time of the math unit, the memory can be accessed more than once during each operation by the math unit, even when the memory has a single data port. For example, during two consecutive operations by the math unit, the first processor can access the memory at least once, the second processor can access the memory at least once, and an external device can access the memory at least once.
  • the flip-flop set maintains correct data for the math unit while the memories are accessed. In addition to the
  • a hardware white noise generator can be connected to the multiplexer to supply pseudorandom data.
  • a second set of flip-flops is often employed to store output data from the math unit.
  • the second flip-flop set temporarily stores the output data from the math unit so that the output data can be moved or stored in a desired location while the math unit is processing new data.
  • the math unit output data in the second flip-flop set can be written to one or many memory locations that are accessible by an interface for a CODEC or a DAC. Data can also be routed back as input to the multiplexer, so that the output data is available for further manipulation by the math unit.
  • a digital signal processor includes a foreground
  • the foreground processor executes a program to create a digital representation of a sound amplitude and is connected to a first memory which stores parameters used by the foreground processor.
  • the background processor is operably connected to the first memory and to a second memory which stores data, particularly look-up table values.
  • the second memory is implemented using DRAM and may be provided on one or more integrated circuit separate from the integrated circuit containing the foreground and background processors.
  • Look-up table values in the second memory can represent any function and are commonly used for delay lines, wave tables, and ADSR curves.
  • the background processor preprocesses data from the second memory. Typical preprocessing performed by the background processor includes operations such as interpolating between look-up table values or changing an offset within a look-up table representing an ADSR curve or other function. Special incrementing algorithms can control the rate at which an ADSR curve or other look-up table is sampled.
  • the Background processor typically includes a third memory for storing interpolation coefficients. The interpolation
  • interpolation coefficients are mathematically derived constants which the background processor multiplies by look-up table values and then sums to derive an interpolated value.
  • An exemplary derivation of interpolation coefficients for performing a cubic polynomial interpolation is disclosed below.
  • the interpolation coefficients can be stored in ROM.
  • Fig. 1 is a block diagram of a digital signal processor having a foreground and a background
  • Fig. 2 is a block diagram of circuit blocks which control data flow through a math unit in a digital signal processor in accordance with the present
  • Fig. 3 is a group of timing diagrams showing an example of how a port control interface, a foreground processor, and a background processor share control of a memory and a multiply-and-accumulate block in a digital signal processor in accordance with the present invention.
  • Fig. 4 is a memory map for an embodiment of the present invention.
  • Fig. 5 is a block diagram of a background
  • Fig. 6 is a flow diagram of an FIR filter
  • Fig. 7 shows plots of four types of ADSR curves.
  • Fig. 8 represents two pages of DRAM memory which store portions of the same look-up table and shows data which is repeated in both pages of DRAM to speed up access to data during interpolation.
  • Fig. 9 contains timing diagrams which illustrate the execution of background tasks and foreground instructions in a digital signal processor in
  • Fig. 1 shows a block diagram of a digital signal processor (DSP) 100 in accordance with the present invention.
  • DSP 100 includes parallel processors 101 and 102 which operate in a parallel interleave fashion and share a math unit 103.
  • Processors 101 and 102 contain conventional processing circuitry such as decoders for decoding instructions and control circuits for generating control signal to implement
  • Processors 101 and 102 are sometimes referred to as foreground processor 101 and background processor 102 to indicate the different functions of processors 101 and 102.
  • Background processor 102 preprocesses information such as look-up table data from a DRAM (not shown).
  • Foreground processor 101 processes information from background processor 102 and parameter memories 107 and 108 and then writes values representing sound amplitudes to a parameter memory 109.
  • the sound amplitude values are typically accessed by a CODEC (coder-decoder) or a DAC (digital-to-analog converter) through a CODEC interface 111.
  • the CODEC or DAC converts the digital sound amplitude values into analog sound signals.
  • an external device such as a personal computer writes data and instructions to DSP 100 through a port control interface 106.
  • Data to be processed by DSP 100 is written into parameter memories 107 and 108.
  • Instructions for foreground processor 101 are written into an instruction memory 110.
  • Parameter memories 107 and 108 and instruction memory 110 are typically implemented as static random access memory (SRAM) .
  • An external DRAM (not shown in Fig. 1) is
  • DRAM interface 104 typically uses a timing generator for refresh cycles and access to the DRAM.
  • the timing generator may be an external
  • the external device also writes control values to control registers 105.
  • the control values include configuration data such as used by CODEC interface 111.
  • CODEC interface 111 is configurable to provide digital signals to one or more DAC (not shown) or both provide and accept signals from one or more different CODECS (not shown) at a programmable sampling rate. Such CODEC interfaces are known in the art and not further described here.
  • Control registers 105 also store mode values which indicate tasks for background processor 102. Together with parameter values in memories 107 and 108, the mode values act as a program for background processor 102 and determine how background processor 102 processes data. In one mode, background processor 102 uses DRAM interface 104 to read data points from a look-up table in the DRAM and then uses shared math unit 103 to calculate an interpolated value between the data points. The interpolated value is written into
  • parameter memory 107 or 108 for later use by foreground processor 101.
  • Other operating modes employed in a specific embodiment of the invention are disclosed below.
  • Foreground processor 101 operates according to a program stored in instruction memory 110.
  • the program generates sound amplitude values according to one or more sound synthesis models. Generated values are stored in parameter memory 109.
  • Foreground processor 101 manipulates data from a number of sources including parameter memories 107 and 108 which may contain data that has been preprocessed by background processor 102, parameter memory 109 which typically contains the results of previous foreground processor operations, a white noise generator (not shown in Fig. 1), and other sources disclosed below.
  • Memory 109 may be an SRAM or a set of registers and typically includes (a) storage locations dedicated for output sound amplitude values and (b) general purpose storage locations used during calculation of sound amplitude values. Multiple output sound
  • amplitude values can be generated for multiple DACs or CODECS. For example, two output sound amplitudes may be generated for producing stereo sound. Values stored in the locations dedicated to output are accessible through CODEC interface ill at intervals determined by the programmable sampling rate. Sampling rate control values stored in control registers 105 determine the sampling rate and can be set through port control interface 106. A programmable clock circuit (not shown) provides a clock signal having a frequency determined by the sampling rate control values.
  • Fig. 2 shows a block diagram of a data selection circuit which includes parameter memories 107 to 109, multiplexers 209 to 211, and interconnecting circuit blocks for implementing data flow through shared math unit 103 in a DSP in accordance with the present invention.
  • shared math unit 103 includes a multiplier-accumulator (MAC) 215 which adds a digital value Z to the product of digital values X and Y.
  • MAC multiplier-accumulator
  • Multiplexer 209 and a circuit block 213 provide value X.
  • Multiplexer 209 selects an output value X' from a set including values MA and MB from parameter memories 107 and 108 respectively, values C. and C. from memory 109, and a value BPX from the background
  • Block 213 transforms the value X' according to a control signal provided by either the foreground or background processor. Examples of transforms that can be selected are no-change so that X equals X', a 2's complement so that X equals -X', and a pan so that X equals (1-X').
  • the 2's complement transformation causes MAC 215 to subtract the product of the values X' and Y from the value Z.
  • Other transformations can be implemented depending on the desired functions and instruction set of the DSP.
  • Multiplexer 210 provides the value Y which is selected from a set including the value MB from
  • Circuit block 206 provides a value representing the number one.
  • MAC 215 When value Y represents the number one, MAC 215
  • Circuit block 207 provides an incremental increase or a percentage decrease for an ADSR curve. The function of circuit block 207 is disclosed more fully below in regard to the foreground processor instruction set in Appendix A.
  • White noise generator 205 is a hardware random number generator which provides a pseudorandom series of digital values.
  • Software random number generators are commonly employed in wave guide synthesis models of musical instruments.
  • a hardware white noise generator facilitates implementation of synthesis models by permitting a single program instruction which
  • white noise generator may be used as white noise generator 205.
  • Multiplexer 211 provides the value Z which MAC 215 adds to the product of the values X and Y.
  • Value Z is selected from a value BPZ from the background
  • processor processor, value C, from memory 109, values MA and MB from parameter memories 107 and 108 respectively, and a value representing zero from circuit block 208
  • Memory 109 may simultaneously provide three values C x , C y , and C z and therefore has multiple data ports.
  • Parameter memories 107 and 108 each provide at most a single value and are single data port memories.
  • Single data port memories require less space in an integrated circuit, are less expensive than multi-port memories, and therefore reduce the cost of the DSP in accordance with the present invention when compared to a DSP with multi-port memories.
  • a binary representation of value Z contains more bits than binary representations of values X and Y because value Z is used for
  • Circuit blocks 212 convert values from memories 107 and 108 to the proper binary
  • Block 204 in addition to changing the representation of value C z , may change the magnitude of value C z during generation of an ADSR curve.
  • block 204 provides a value representing 1 or 0.5 depending on whether a faster or a slower attack is desired.
  • block 204 checks whether value C z will cause a discernable decrease in an ADSR curve value and if the value C z will not, block 204 provides a value which will cause a minimal decrease in the ADSR curve value.
  • the foreground processor or background processor depending on which of the processors is using MAC 215, generates select signals for multiplexers 209-211.
  • the foreground processor decodes instructions and provides select signals to multiplexers 209-211 and address signals to memories 107-109 typically while MAC 215 performs a multiply-and-accumulate cycle for the background processor.
  • the background processor decodes a mode value and parameters from parameter memories 107 and 108 to generate appropriate values BPX, BPY, and BPZ and select signals for multiplexers 209 to 211 while MAC 215 performs a multiply-and-accumulate cycle for the foreground processor.
  • the timing of the select and address signals are disclosed below.
  • a set of flip-flops 214 stores one set of values X, Y, and Z while a next set of values X, Y, and Z selected by the foreground or background processor propagates through the data selection circuit including multiplexers 209 to 211. New values X, Y, and Z are stored in flip-flop set 214 and provided to MAC 215 when a timing signal MAC_CLK is asserted. As is well known, signal MAC_CLK is asserted "high" or asserted
  • a flip-flop set 216 is also clocked by signal MAC_CLK and stores an output value (Z+X*Y) from MAC 215 when MAC 215 begins processing the next values X, Y, and Z.
  • the numbers of flip-flops in flip-flop sets 214 and 216 depend on the numbers of bits used to represent values X, Y, and Z. In one embodiment, each multiplicand value X or Y contains sixteen bits, and the addend value Z contains thirty-two bits. In such an
  • flip-flop set 214 stores 64 bits of
  • flip-flop set 216 stores a 33-bit value (the sum of two 32-bit numbers).
  • Circuit block 217 tests the output value stored by flip-flop set 216 and sets flags to indicate, for example, that the output value is zero, negative, overflows, or underflows the capacity of the storage location in memory 109 where the output value is to be stored.
  • circuit block 217 provides either a saturated value (the most positive or the most negative value that can be represented in the target register) or truncates the most significant bit of the output value from MAC 215. Whether the value provided by block 217 is saturated or truncated depends on a configuration control value SATF.
  • the value from block 217 is directed to a location in memory 109 indicated by an address signal from the foreground processor or is directed to the background processor on bus B_WRITE_DATA.
  • values DA, DB, MA, and MB are provided to circuit block 217 and are written to memory 109 during move instructions disclosed below.
  • Multiplexer 203 implements move instructions which move values into memories 107 and 108. Values C x , C y , and C. from memory 109, a value BP from the background processor, or a value MW from the port control
  • flip-flop sets 201 and 202 provide delayed values DA and DB from memories 107 and 108.
  • the delayed values DA and DB change every time signal MAC_CLK is asserted and indicate the previous values MA and MB provided by parameter memories 107 and 108 respectively. Delayed values DA and DB can be moved back into memories 107 and 108 through multiplexer 203 or into memory 109 through circuit block 217.
  • memories 107 to 109 are sufficiently fast to provide valid data signals in less than about half the time required for MAC 215 to execute a
  • control of parameter memories 107 and 108 and control of MAC 215 are time division multiplexed. Time division multiplexing of memories 107 and 108 permits use of less expensive single port memories even though memories 107 and 108 are accessed by the foreground processor, the background processor, and the port control interface.
  • Fig. 3 shows timing diagrams indicating control of parameter memories 107 and 108 and control of MAC 215 for typical instructions executed by the foreground processor.
  • the foreground processor controls the foreground
  • processor has sole control of memory 109, except at the end of sampling periods, when the CODEC interface may have access.
  • FP indicates the foreground processor has control
  • BP indicates the background processor has control
  • PC indicates that the port control interface has control. Timing of memory control can be varied according to particular
  • Each foreground instruction is completed in one instruction cycle time such as instruction cycle 310.
  • the instruction cycle is twice as long as a multiply-and-accumulate cycle (MAC cycle) for MAC 215 and four times as long as the memory access time for memories 107 to 109.
  • Instruction cycle 310 includes four memory access periods 330, 332, 334, and 336.
  • the foreground processor controls parameter memories 107 and 108, and MAC 215 processes data previously selected by the background processor.
  • the foreground processor generates address signals for parameter memories 107 to 109 and/or select signals for multiplexers 209 to 211.
  • Parameter memories 107 to 109 and/or circuit blocks 205 to 208 provide valid data values which propagate through multiplexers 209 to 211 to input leads of flip-flop set 214.
  • MAC cycle 322 is not disturbed because flip-flop set 214 maintains previous values X, Y, and Z on the input leads of MAC 215.
  • MAC 215 begins MAC cycle 320 for the foreground processor. Also at time T1, flip-flop set 216 stores the output value from previous MAC cycle 322 of MAC 215. The output value from flip-flop set 216 is directed by circuit block 217 to the background processor via bus B_WRITE_DATA.
  • flip-flops sets 201 and 202 store the selected values DA and DB at time T1.
  • Values DA and DB can be written into any of memories 107, 108, or 109 during memory access period 334, the next time that the foreground processor has control of memories 107 and 108.
  • the background processor controls memories 107 and 108.
  • the action of the background processor depends on the background
  • processor task and on the processing sequence for the task.
  • processor generates read addresses for memories 107 and 108 and reads parameter values from memories 107 and 108.
  • the background processor determines the task and subsequent processing sequence of the background processor.
  • the background processor In the last step of a typical processing sequence, the background processor generates write addresses for memories 107 and/or 108 and writes values to memories 107 and/or 108.
  • Execution of background tasks can be pipelined so that two or more background tasks are executed at once.
  • the background processor controls multiplexers 209-211 and therefore controls data flow to flip-flop set 214 even though the
  • the foreground processor controls memories 107-109 during access period 334.
  • the background processor directly provides data signals BPX, BPY, and BPZ so that new data is ready for MAC 215 at time T3. Accordingly, MAC 215 operates without pipeline delay.
  • the operation of the background processor is disclosed in more detail below.
  • the foreground processor controls memories 107-109. For instructions that move data into parameter memory 107 or 108 from memory 109 or from flip-flop sets 201 or 202, the foreground processor generates write addresses for memories 107 and 108 and select signals for multiplexer 203 so that selected values are written.
  • flip-flop sets 214 and 216 are
  • Flip-flop set 216 captures the output value from MAC 215.
  • the output value from flip-flop set 216 can be stored at a write address provided to memory 109 by the foreground processor during the memory access period 336 because the foreground
  • the processor does not share access of memory 109 with the background processor or the port control interface.
  • the port control interface controls memories 107 and 108 during memory access period 336, and provides select signals to multiplexer 203 for writing data MW to memories 107 and 108.
  • a new instruction cycle 315 begins at time T4 and proceeds in a manner similar to instruction cycle 310.
  • Fig. 4 shows a memory map of parameter memories
  • Parameter memories 107 and 108 and instruction memory 110 each contain 512 16-bit words of data or
  • Memory maps 407, 408, and 410 show a single slot from
  • parameter memory 107 parameter memory 107
  • parameter memory 108 parameter memory 108
  • Each slot in instruction memory 110 corresponds to a slot in
  • each collection of corresponding slots operates together as program and parameters for a distinct voice or emulation, but a number of slots may be combined to represent a more complex emulation.
  • Control registers 105 in Fig. 1 contain 32 sets of mode values which correspond to the 32 slots in
  • Memory 109 contains sixteen locations C0-C15 which are global to all slots. Eight locations C0-C7 are 24-bit locations and accessible through CODEC interface 111. The 24-bit locations are paired into four sets for four stereo CODEC channels. Each set contains left and right sound amplitude values. The remaining eight locations C8-C15 are 32-bit general purpose storage that may be used for intermediate calculations,
  • memories 107 and 108 store 16-bit fixed point representations of values between -2 and just less than 2.
  • the 16-bit representations have a sign bit, an integer bit, and 14 bits representing a
  • Memory 109 contains fixed point binary representations of numbers between -16 and just less than 16.
  • the fixed point binary representations contain a sign bit, a 4-bit integer part, and either a 19-bit or a 27-bit fractional part depending on whether the storage location is twenty-four or thirty-two bits.
  • the sound amplitudes provided through CODEC interface 111 are restricted to values between -2 and 2.
  • processor 101 of the exemplary embodiment as shown in Fig. 1 is provided in the Appendix A.
  • Each 16-bit foreground processor instruction contains up to three operands i, j, and k.
  • the operands are indices which identify data in parameter memories 107 to 109.
  • the instruction words are to the left of one or more equations which describe the operation performed by execution of the instruction.
  • subscripted quantities A, B, and C are data values from parameter memories 107, 108, and 109 respectively.
  • Operands which identify a data word from parameter memories 107 and 108 contain up to four bits and are offsets relative to a slot pointer which identifies the slot that foreground 101 processor is executing.
  • Foreground processor 101 updates the slot pointer as slots are completed.
  • Background processor 102 keeps a separate slot pointer so that foreground and background processor 101 and 102 can execute different slots.
  • Data in memory 109 is also identified with 4-bit operands, but the operands are global, i.e. independent of the slot pointer.
  • foreground processor provides addresses and select signals to the memories 107-109 and multiplexers 209-211 according to the values on the right side of the equation describing the instruction.
  • the result of MAC cycle 320 is written into memory 109 between times T3 and T4.
  • a single value C i +A j B k is calculated and written to two addresses C 1 and C i+l .
  • Values C l , A j , and B k are read during the first memory access period of the foreground processor, for example during period 330 in Fig. 3 and new values C i and C i+l are written after MAC has completes a multiply-and-accumulate cycle, for example during period 336 in Fig. 3.
  • Group A of the instructions in Appendix A includes two operand instructions. Group A instructions are executed in a single MAC cycle with the above disclosed timing. In some of the instruction, a value WN from white noise generator 205 is multiplied by a value from parameter memory 107 or 108. In group A, instructions 1011-0000-j-0i through 1011-0010-j-1i are for
  • One 32-bit multiplicand is a value C.
  • multiplicand has sixteen most significant bits in an A value and sixteen least significant bits in a value B.
  • operand i is a 3-bit value.
  • MAC 215 in the exemplary embodiment multiplies two 16-bit values, multiplication of 32-bit values requires more that one MAC cycle.
  • Values CH and CL indicate the sixteen most significant and sixteen least significant bits respectively in the value C.
  • Value NF is a sign for signed multiplication.
  • the function "absmitted" is the absolute value.
  • Group B of the instructions in Appendix A includes two operand instructions for addition and subtraction. Group B instructions are executed in a single MAC cycle using the timing described above.
  • the foreground processor causes block 206 (FORCE1) to provide a one as value Y so that MAC 215 performs an addition or
  • foreground processor causes circuit block 213 (NEG. PAN) to perform a 2's complement.
  • Group C of the instructions in Appendix A are two operand instructions that are useful in constructing filters.
  • the instruction combines a multiply and a move.
  • foreground processor generates address signals for parameter memories 107 to 109 according to the first equation describing the instructions in Appendix A.
  • flip-flop set 214 latches input values for MAC 215.
  • Flip-flop sets 201 and 202 also latch the values from memories 107 and 108.
  • the foreground processor If the instruction moves a value from memory 109 or from one of flip-flop sets 201 and 202, then during the second memory access period of the foreground processor, time interval 334 in Fig. 3, the foreground processor generates appropriate select and address signals for writing the moved value into the
  • the foreground processor generates appropriate select and address signals for circuit block 217 and memory 109, so that the result of the MAC cycle is written into memory 109.
  • the foreground processor generates address signals for input values to MAC 215 according to the right side of the first equation for the instruction.
  • the value to be moved between memory 107 and memory 108 is not read during period 330 and not stored in flip-flop set 201 or 202.
  • the foreground processor grants control of the
  • the foreground processor takes control of the destination memory 107 or 108 from the port control interface and generates address and select signals for writing the value to the destination memory 107 or 108, but the port control interface keeps control of the source memory 108 or 107. Accordingly, for this special case the foreground processor and the port control interface swap memory accesses to one of the memories 107 or 108, but both the foreground processor and the port control interface retain the usual number of accesses to memories 107 and 108 for the instruction cycle.
  • Group D of the instructions in Appendix A contains two operand move instructions. The instructions are completed in a single instruction cycle. Up to four moves can be executed in a single instruction cycle, one move into each memory 107 and 108, during each access period in which the foreground processor has control of memories 107 and 108. 32-bit values C can be moved into or from two 16-bit values A and B, where value A contains the 16 most significant bits and value B contains the 16 least significant bit. Such combined values A and B are indicated by AB in Appendix A. Move instructions 1110-0011-j-i through 1110-1010-j-i move and shift a value C. The shift can be performed by providing shift capabilities in multiplexer 203 of Fig. 2.
  • Group E of the instructions in Appendix A contains two parameter instructions which provide special functions for ADSR curves and decay curves.
  • the functions performed by the instructions depend on control values in control register 105 which indicate states "key on”, “key off”, “alt on”, and “alt off” for each slot.
  • Functions ADRS0_K, ADRS1__K, and ADRS2_K respond to key on and key off states. Functions
  • ADRS0_A, ADRS1_A, and ADRS2_A respond to alt on and alt off states.
  • ADRS1_K, and ADRS2_K generate values appropriate for an attack phase of an ADSR curve by incrementing a value C by a fixed increase.
  • the fixed increase is given by bits 0-6 of the value A times 1/8 for ADRS0_K and times 4 for ADRS1JK and ADRS2_K. Each time the instruction is repeated incrementing continues until the value C reaches 1, and then bit 7 of the value A is set
  • bits 8-15 of the value B are shifted to the right three bits (divided by eight) to determine the fraction.
  • the decay continues until the value C reaches a level indicated by bits 14-12 of the value A then bit 15 of the value A is set to indicate a sustain phase of the ADSR curve.
  • the instructions leave the value C is unchanged until a key off state arises and then bit 7 of the value A is cleared indicating a release phase of the ADSR curve.
  • the value C is decreased by a fraction of the value C where the fraction is indicated by bits 7-0 of the value B.
  • ADSR0_A, ADRS1_A, and ADRS2_A perform in the same manner as functions ADSR0_K, ADRS1_K, and ADRS2_K except that functions ADSR0_A, ADRS1_A, and ADRS2_A respond to the conditions alt on and alt off.
  • DECAY_A and DECAY_K implement long exponential decay function and are used with long table modes.
  • the instruction does nothing unless the
  • background processor mode which uses the value B as a parameter is a long table mode, and the background processor is accessing data in the last page of the long table. (Long table background mode is disclosed below.) On the last page, the instructions decrease a value C by a fraction indicated by the value B if the appropriate key off or alt off condition is set.
  • Group F of the instructions in Appendix A contains one operand and no operand instructions used mostly for conditional branching and manipulation of status flags. The instructions only permit forward branching so that no program loops are possible. Without loops, the maximum time required to execute all of the instructions
  • instructions in all of the slots can be limited to less than the sampling period.
  • Group G of the instructions in Appendix A contains one operand special move instructions which are useful for controlling background tasks that are described in detail below. Functions M0VH8 and MOVH10 move the most
  • MOVADL and MOVADH are typically used with background tasks which use a page size selector.
  • Some background tasks use a value A as a page size selector which selects the location of a physical page in a DRAM and the size of a logical page for storing a look-up table or delay line.
  • These background tasks use a value B as a pointer within the physical page.
  • Physical memory pages in the DRAM may for example contain 512 words. When the logical page is smaller than the physical page, more than one look-up table or delay line can be store in a single physical page of DRAM. For example, if value A selects a logical page size of 64 words, then value B may point to any of eight 64-word logical pages in a 512-word physical page. The most significant bits of the value B
  • MOVADL and MOVADH move bits from a value C to selected bits of a value B, either to the bits which indicate a location within a logical page or the bits which indicate the logical page.
  • a value A (the page size selector) determines the bits of the value B changed.
  • MOVADH instructions change just the bits indicating the logical page and are useful for creating a family of curves which can be selected algorithmically.
  • MOVADL instructions preserve the bits which indicate the logical page and change the bits which indicate a location with in the logical page.
  • Groups H and I of the instructions in Appendix A contain instructions for special functions. Functions UNPACKS and UNPACKU move four nibbles from a signed or unsigned 32-bit value C into two value A and two values B. Functions PACKU and PACKS moves nibbles from two values A and two values B into one 32-bit value C.
  • Functions RSPP, SPPA, SPPR, and SPPL are for jumping between instruction slots according to addresses given by a value C.
  • Functions FAR A and FAR B are for accessing parameter of other slots.
  • functions FKF, FKO, FAF, and FAO set states "key off”, “key on”, “alt off” and “alt on” respectively.
  • Functions I and FAR I are for accessing instructions in the current and in another slot.
  • ZF indicates the zero flag.
  • Fig. 5 is a block diagram showing greater detail of background processor 102.
  • the tasks executed by background processor 102 are determined by mode and control values stored in control registers 105 and by parameters stored in memories 107 and 108.
  • the mode values and control values are set by an external device such as a personal computer connected to the DSP through port control interface 106.
  • Parameter values in memories 107 and 108 are set or changed by the external device, foreground processor 101, or background processor 102.
  • control registers 105 One set of control values in control registers 105 indicates which slots are enabled and which slots are disabled.
  • Foreground processor 101 executes the instructions for each enabled slot such as instructions 410 in Fig. 4, and background processor 102 executes background tasks for each enabled slot as indicated by mode values in control registers 105 and parameter values in memories 107 and 108.
  • the number of slots enabled should not exceed the maximum number of slots that can be executed within a single sampling period.
  • Foreground processor 101 must be fast enough to execute all of the instructions in all enabled slots before an amplitude value is required by the CODEC interface.
  • background processor 102 either skips the slot and begins execution of the next
  • Block transfers permit an external device connected to port control interface 106 to access DRAM 502.
  • the external device disables a slot and during memory access periods of the port control interface 106, writes a DRAM address and data to locations in memories 107 and 108 corresponding to the disabled slot.
  • the external device sets a flag in control registers 105 to indicate that the disabled slot contains data to be written to DRAM 502.
  • background processor 102 reaches the disabled slot, background processor 102 transfers the data from memories 107 and 108 to DRAM 502, and foreground processor 101 executes no operations.
  • the external device writes a DRAM address to memory 107 or 108 and sets a second flag for the disabled slot.
  • processor 102 transfers data from DRAM 502 to memory 107 and 108 where port control interface 106 can read the data in subsequent memory access periods.
  • DRAM 502 is provided on one or more separate integrated circuits while the remaining circuits shown in Fig. 5 are situated together on a single monolithic integrated circuit.
  • DRAM 502 may include multiple banks of paged memory for data such as look-up tables, ADSR curves, delay lines, and any desired wave tables.
  • ADSR curves, delay lines, and wave tables are generically referred to herein as look-up tables.
  • Look-up tables in DRAM 502 provide output values that represent values y. of a function Y for a range of discrete values n.
  • the value n is indicated by the address provided to DRAM 502.
  • function values Y(n+x) are needed for fractional values x, and interpolation between look-up table values y a and y a+1 is required.
  • the background processor may perform interpolations.
  • a cubic polynomial approximates the function Y(n+x) as Y(n+x) - KjX 3 + K 2 x 2 + K,x + Ko (eq. 1)
  • eq. 1 yields values y a-l , y a , y a+l , and y a+2 for x equal -1, 0, 1, and 2 respectively if the values K 3 , K 2 , K 1 , and K 0 are as shown in eqs. 2-5.
  • Y(n+x) from eq. 6 is a sum of four terms, each term being the product of one look-up table values y,.,, y,, y a+1 , or y a+2 and a coefficient that depends on the fraction x.
  • Background processor 102 of Fig. 5 can interpolate by approximating look-up table functions with cubic polynomials.
  • the coefficients from eq. 6 for desired values of fraction x are stored in a table in an interpolation ROM 501.
  • coefficient values are stored in
  • interpolation ROM 501 for fractions x from 1/128 to 127/128 in steps of 1/128.
  • Appendix B shows a table of coefficient values referred to as "Lagrange Data" for a step size of 1/128.
  • Interpolated values y(n+x) between any two consecutive look-up table values y, and y, +1 are determine in four multiply-and-accumulate cycles using eq. 6.
  • address generator 507 generates a DRAM read address for the point y a-l .
  • the address generated depends on the mode values in control register 105 and on parameter values in memories 107 and 108 as disclosed in more detail below.
  • Address generator 507 supplies an address for the first of four consecutive location in DRAM 502 to be written into FIFO buffer 503.
  • the address generator 507 also provides an address in interpolation ROM 501 for the interpolation coefficients corresponding to the fractional value x.
  • values BPX, BPY, and BPZ are provided from interpolation ROM 501, FIFO 503, and an accumulator 509 respectively.
  • the output value from MAC 215 is stored into accumulator 509 until the last multiply-and-accumulate cycle provides the desired interpolated value.
  • the interpolated value is stored in memory 107 or 108 for later use by foreground processor 101.
  • Appendix B performs a filter operation which reduces the aliasing.
  • the Minimum Sidelobe Data coefficient values may be used in place of the Lagrange Data coefficients where aliasing may be a problem.
  • parameter memories 107 and 108 are included in the exemplary embodiment of the invention.
  • instruction memory 110 are divided into slots as shown in Fig. 4.
  • Each slot in memory 107 contains eight words A o -A s used by background processor 102, and each slot in memory 108 contains eight words B o -B s used by background processor 102.
  • Control registers 105 contain one 16-bit mode value for each slot.
  • Background processor 102 executes four background tasks per enabled slot. Each background task is determined by a nibble from the mode value and two parameters from each of the corresponding parameter slots. If the nibbles in the mode value are indexed by an integer n between 0 and 3, a task decoder 506 reads nibble n and parameters A 2m , A 2m+l , A 2n , and B 2n+l to determine a task to be executed. Once the task is determined, a state controller 504 and pipeline timing circuit 505 controls the sequence of operations for completion of the task. The operations for the tasks are pipelined as described below in regard to Fig. 9.
  • the exemplary embodiment of the invention has sixteen background tasks Indicated by mode nibbles.
  • Nibble 0000 indicates no background task.
  • the first mode (0001) is referred to as delay line mode and is primarily used for wave guide synthesis.
  • Delay line mode provides an interpolated value from a delay line in DRAM 502 and optionally writes a value to the delay line.
  • Background processor 102 maintains an 18-bit master write pointer used when determining where data is read or written in DRAM 502. The nine most
  • the absolute pointer is decremented after each sample period and used for determining addresses that should change every sampling period.
  • the absolute pointer is set every time a background task is executed in absolute mode and is used to define a base for a series of background tasks.
  • parameter A 2m indicates the write address in DRAM 502 if data is written.
  • Bit 15 of A 2m indicates whether DRAM access is in absolute or relative mode.
  • Bit 14 of A 2m is set if data is to be written.
  • Bits 11-13 of A 2m indicate a logic page size which determines the amount of memory used to generate the delay line. Page sizes range from 512 words to four words in powers of two.
  • Bits 9 and 10 of A 2m indicate which of four DRAM circuit contains the desired address. In relative mode, an address
  • the absolute pointer provides the nine most significant bits of the write address. In absolute mode, the absolute pointer is set to the value given by bits 0-8 of A 2m , and the write address has nine most significant bits given by bits 0-8 of A 2m and nine least significant bits given by the write index pointer wrapped around a page boundary.
  • Parameter A 2m+l indicates the value to write.
  • Parameter B 2m indicates the delay line length (an offset relative to the write address for reading from the delay line). Offsets beyond a logical page boundary wrap around.
  • the delay line length includes a
  • FIR filter mode is mode nibble 0010 binary and implements a two tap finite impulse response (FIR) filter illustrated in Fig. 6.
  • the FIR filter performs the sum of three products B 2m+l *A 2n + l + DRAM0*A 2m +
  • DRAMl*B 2m and writes the result into parameter B 2m+l .
  • the values DRAM0 and DRAM1 are read from a page of DRAM at an address given by a control value in control
  • registers 105 The page is divided in sections. Each section correspond to slot and contains values DRAM0 and DRAM1 for FIR filter mode tasks.
  • Read only look-up table mode has mode value nibble 0011 binary and interpolates a value from a look-up table contained in one or more pages of memory.
  • Parameter A 2m indicates the starting page and the number of pages in the look-up table.
  • Parameter B 2m indicates an offset relative to the start of the look-up table, including a fractional part for interpolation if the look-up table is one page or less.
  • One bit of parameter A 2m may be used to indicate ir wrap around or truncation occurs when the offset provides an address past a boundary of the look-up table.
  • Mode nibbles 0100 through 0111 indicate modes for generating four types of ADSR curves. Plots of the four ADSR curves as a function of time are shown in Fig. 7. Each type of ADSR curve has a look-up table stored in DRAM and a sampling rate that is given by a variable increment that is added to an offset every sampling period.
  • Mode 0100 is a single shot ADSR curve which when initiated by a key-on state 710, runs at a constant sampling rate through the ADSR look-up table once and thereafter returns a value zero.
  • Mode 0101 is a drum roll type ADSR curve which starting with a key-on state 720 repeatedly runs at constant sampling rate through the ADSR look-up table until a key-off state 722 occurs.
  • Mode 0110 is a piano ADSR curve which starts with a key-on state 730 and fast sampling rate but switches to a slow sampling rate after a fixed time 722.
  • the fast sampling rate permits more points in the look-up during the critical attack portion of a note and relatively fewer points thereafter.
  • the sampling rate of the piano ADSR curve returns to the fast sampling rate and runs through the remaining points of the look-up table as shown by a faster decay curve 734. If the key-off state does not occur, the slow sampling rate is maintained and a slower decay curve 736 is provided.
  • Faster and slower decay curves 734 and 736 use the same look-up table but sample through the values at different rates.
  • Mode 0111 is an organ ADSR which starts with a key-on condition 740 and after a fixed time 742, stays at a fixed point in the look-up table, until a key off state 744 occurs then sampling continues.
  • parameter A 2m indicates a speed shift factor, a starting physical page, and a logical page size for the ADSR look-up table.
  • Parameter B 2n indicates an offset within the ADSR table including a fractional part for
  • Parameter A 2n+l indicates a time step constant and the least significant bits (LSBs) of the offset in the ADSR look-up table.
  • the LSBs from the parameter A 2m+l gives offset resolution finer than the interpolation capabilities of the background processor. The added accuracy in offset value may be necessary to avoid round-off or truncation error during changes of the offset.
  • the background processor increments the offset by an amount given by the time step constant shifted by the speed shift factor. For long duration notes, the increment can be small, perhaps only a change only in the LSBs provided by A 2m+l .
  • An interpolated result from the ADSR table is written into parameter B 2n+l .
  • Mode nibble 1000 binary indicates Read-Only Wave Table mode.
  • parameter A ⁇ indicates an absolute address and size of a wave table and indicates how often the offset within the wave table should be changed, for example once every sampling period or once every two sampling period.
  • Parameter B 2m indicates an offset including a fractional part for interpolation. The offset wraps around if the offset is past an end of the wave table.
  • Parameter A 2m+l is a signed step rate which is added to the offset when the background processor changes the offset. An interpolated result is written to parameter B 2m+l .
  • Mode 1001 binary is long table mode which is used when a look-up table is contained in more than one page of DRAM as shown in Fig. 8.
  • Parameter A 2m indicates a starting page number and the number of pages containing the look-up table.
  • Parameter A ⁇ also indicates whether offset should wrap around from one end of the look-up table to the other or be truncated.
  • Parameter B 2n indicates a current page index and offset within the page.
  • Parameter A 2m+l indicates a step rate for changing the offset and an interpolation fraction for
  • y n-l , y n , y n+l , and Y n+2 are read from a look-up table for interpolation. Because access to four data values in two or more physical pages takes more time than access to four value in a single page, the data values in the last four locations of each page are repeated in the first four locations of the next page. For example, memory locations 820 in DRAM Page 1 contain the same data as locations 810 in DRAM Page 0. The very last page has final values copied to the beginning of the first page in look-up table when wrap around enabled.
  • Modes 1010 and 1011 are long table modes with 2-to-1 and 4-to-1 compression, and operate in
  • long table mode operates on a look-up table containing 16-bit word values
  • long table modes with 2-to-1 compression operates on a look-up table containing byte values
  • long table modes with 4-to-1 compression operates on a look-up table containing nibble values.
  • Mode 1100 is a long read-write delay line mode that both reads and writes to a delay line that extends over several pages of DRAM.
  • Parameter A 2m indicates a starting page and the number of pages containing the delay line.
  • Parameter B ⁇ indicates the delay line length as a page index and an offset within the page. No fractional offset is provided and therefore no interpolation is done in this mode. For large look-up tables, the accuracy provided by a large number of data points makes interpolation less important.
  • Parameter A 2m+l stores data to be written at an address indicated by a write index pointer maintained by background processor 102. The value read from the delay line is written to parameter B 2m+l .
  • Mode 1101 is long read only mode and is the same as mode 1100 except that no data is written.
  • Mode 1110 is either a sample record mode or a line input mode. Bits in parameter A ⁇ distinguish the sample record mode from the line input mode. Sample record mode records or stores into DRAM sound amplitude values generated by the DSP.
  • Parameter A 2m contains a starting address and a data size for writing of data into DRAM. Data may be written in word, byte, or nibble sizes.
  • Parameter B ⁇ contains a sample counter which indicates a current page index and an offset in the current page for writing data. The offset is incremented by the background processor as data is written.
  • Parameter A 2m+l contains the data to be written. Parameter B 2m+l contains an index for writing byte or nibble values and flags for stopping and starting recording.
  • Line input mode moves data from the CODEC
  • CODECS or ADCs Up to four stereo CODECS or analog-to-digital converters (ADCs) can be connected to the CODEC interface.
  • CODECS or ADCs For recording of a sound, CODECS or ADCs write sound amplitude values to registers in the CODEC interface.
  • Four pairs of registers are provided in the CODEC interface to store four pairs of values from the CODECS or ADCs, each pair of values being a left value and a right value as are common for stereo sound.
  • the sound amplitude values
  • parameter A 2m contains a flag which indicates line input mode rather than sample record mode and contains a code which indicates which of the four pairs values are transferred.
  • background processor transfers the left value of the pair indicated to parameter A 2m+l and the right value of the pair indicated to parameter B 2n .
  • Parameter B 2m+l is not used in this mode.
  • Parameter Aj indicates a slot pointer, a parameter index for a multiplicand A, and a parameter index for a multiplicand B.
  • Each parameter index has a code bit which indicates whether the parameter is in the current slot or the slot indicated by the slot pointer.
  • the product of A and B is store in A 2m+l .
  • Parameter B 2m indicates a slot pointer and two parameter indices for multiplicands A' and B' which are either in the current slot or the slot pointed to by the slot pointer.
  • the product of A' and B' is store in B 2m+l .
  • background processor 102 performs background tasks as indicated by mode values from control registers 105 and parameters from parameter memories 107 and 108. There are four background processor mode values for each slot indicating four background tasks. Each task requires up to four multiply-and-accumulate operations.
  • background processor 102 executes up to sixteen multiply-and-accumulate operations per slot which is exactly the same as the maximum number of instruction executed per slot by foreground processor 101.
  • background processor 101 processes a slot after background processor 102 has completed all of the background tasks for the slot. For example, at the beginning of a sampling period, background
  • processor 102 starts processing background tasks for slot 0 and foreground processor 101 is idle.
  • Foreground processor 101 starts processing slot 0 after background processor 102 has completed slot 0 and written preprocessed data into parameter memories 107 and 108, so that although background processor 102 and foreground processor 101 share math unit 103 in
  • Fig. 9 shows timing diagrams indicating an example of the operation of background processor 102 in
  • a sample clock asserts a signal START_BP which starts operation background processor 102.
  • Background processor starts decoding and executing background tasks starting with slot 0 (or the first enabled slot). Execution of operations to complete background tasks are pipelined and controlled by timing signals generated by a pipeline timing circuit 505.
  • Decoding by task decoder 506 begins with reading of mode values from control registers 105 and parameter values from memories 107 and 108. Background processor 102 has access to memories 107 and 108 once per
  • background 102 can read two parameters per instruction cycle, one from each or memories 107 and 108.
  • a signal RA0B0 is asserted low during instruction cycles in which background processor 102 reads even indexed parameters A 2m and B 2n from memories 107 and 108. For example, during instruction cycle 901, background processor 102 reads parameters A 0 and B 0 from slot zero.
  • a signal RA1B1 is asserted low during instruction cycles in which background processor 102 reads odd indexed parameters A 2a+l and B 2m+l from memories 107 and 108. For example, during instruction cycle 902, background processor 102 reads parameters A, and B, from slot zero.
  • Fig. 9 illustrates the example of a delay line mode background task described above.
  • the delay line mode background task requires one write to DRAM 502, four reads from DRAM 502, and four multiply-and-accumulates operations.
  • a row address signal RAS is asserted to DRAM 502 at time 951 after task decoder 506 and DRAM controller 510 have determined a row address (or physical page) for memory 502.
  • the physical page is determined from parameter A 0 , the write index pointer, and the absolute pointer as described above.
  • signal RAS remains asserted
  • a column address signal CAS is asserted five times, once for a write and four times for reads from the same page in DRAM 502. Data read from DRAM 502 goes into FIFO buffer 503.
  • background processor 102 While the signal RAS is assert, background processor 102 continues to access memories 107 and 108 and begins reading parameters for the next background task.
  • background processor 102 is controlling a multiply-and-accumulate operation for the first task of slot 0, accessing DRAM 502 for the second task of slot 0, and reading parameters for a third task of slot 0.
  • Each background task has four opportunities to use shared MAC 215.
  • Signals MK0, MK1, MK2, and MK4 are asserted low if the background task actually uses shared MAC 215 during the first, second, third, or fourth opportunity, respectively.
  • Signal MK0 is asserted low during instruction cycle 906, and MAC 215 multiplies a value from FIFO buffer 503 (the first value read from DRAM 502 after time 951 when signal RAS was asserted) by a first interpolation coefficient from interpolation ROM 501.
  • instruction cycles 907, 908, and 909 successive values from FIFO buffer 503 are multiplied by corresponding values from interpolation ROM 501 and the results are accumulated.
  • the accumulated results is the desired interpolated value.
  • Signals WA0B0 and WA1B1 are asserted low during instruction cycles when background processor 102 writes to memories 107 and 108.
  • signal WA1B1 is asserted low during instruction cycle 911, and background processor 102 writes the desired interpolated value to parameter B 1 .
  • interpolated values are always written to odd parameters, typically B 2m+l . Values written to even number parameters do not require interpolation or shared MAC 215. Accordingly, assertion of signal WA0B0 during instruction cycle 904 corresponds to the first task of slot 0 and even though the last write operation for the first task of slot 0 does occur until
  • instruction cycle 911 This timing is maintained for all background tasks regardless of the number of multiply-and-accumulate operations actually employed by a particular background task.
  • the second, third, and fourth task of slot zero proceed in the same manner as described above, and background processor 102 writes final results to memories 107 and 108 during instruction cycles 915, 919, and 923 respectively.
  • Reading parameter values for slot 1 begins with instruction cycle 917 which is before the third and fourth task of slot 0 are
  • Foreground processor 101 then transfers eight sound amplitude values from parameter memory 109 to CODEC interface 111 where one or more DAC or CODEC can access the sound amplitudes.
  • Foreground processor 101 and background processor 102 are then idle until a sample rate clock causes signal START_BP to be asserted again, and background processor 102 begins again with slot 0.
  • background processor 102 begins before the CODEC interface has read all the sound amplitude values. This is possible because background processor 102 does not disturb the sound amplitude values.
  • the envelope instructions perform different operations depending on control values and whether the envelope is in an attack, a decay, a sustain, or a release phase.
  • Ci Ci+Aj[6..0]*4 for ADSR2 and ADSR1, or
  • Ci Ci+Aj[6..0]*(1/8) for ADSR0 (slow attack).
  • Aj[15] is set, and otherwise the instruction performs NOP.
  • a sustain phase does not apply to ADR.
  • Ci Ci-(Ci/8)*Bj[7..0] for ADSR 1 and ADSR0.
  • ADR0 through ADR2 instructions work the same as ADSR0 through ADSR2 instructions except that there is no sustain point.
  • Envelope Generator requires two overhead instructions (get state and save state). q must be saved before it is modified.
  • C15 AB15; Get previous value.
  • C15 ADSR2 (C15, A14,B14); C15 is the new Envelope value.
  • the decay instruction augments the Long Table modes.
  • the last page may be looped in these modes.
  • This instruction creates an exponentially decaying envelope during that last page as it repeats.
  • This instruction requires 2 additional instructions to save and restore the C register. The instruction functions as follows:
  • Ci Ci-(Ci/8) *Bj ;
  • C14 AB15 ; Get previous envelope data.
  • C14 DECAY(C14, B7);
  • C14 is the envelope Data.
  • n Number of samples to achieve the targeted decay.
  • Fraction equals [1-B] for fast modes and [1-B/8] for slow modes.
  • B may take on a maximum value of 7.8E-3 for fast modes; this produces a fraction equal to 0.992.
  • B may take on an effective value of 3.8E-6 producing the fraction equal to 0.999996.
  • the decay time is as follows:
  • SR is defined as the sample rate
  • a relative address contains five bits S0 to S4 which indicate a slot number and four bits P0 to P3 which indicate a
  • the relative address contains two bits R0 and Rl which indicate the addressing mode.
  • the two bits Rl and R0 function as follows:
  • the relative address is defined as the sum of the slot pointer S4-S0 and either the current slot or the parameter pointer. h
  • the sum output wraps around.

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Abstract

Processeur (100) de signaux numériques autonome entièrement programmable qui comporte deux processeurs (101, 102) partageant, de manière imbriquée et parallèle, une unité mathématique (103) telle qu'un circuit de multiplication et accumulation. Un processeur arrière (102) commande une mémoire RAM dynamique et prétraite les informations pour un processeur de front (101). Une mémoire RAM statique (107, 110) sur puce stocke des paramètres de programme tant pour le processeur arrière que pour le processeur de front, et facilite le transfert d'informations entre lesdits processeurs. La mémoire RAM statique est multiplexée dans le temps pour en permettre l'accès par le processeur de front, le processeur arrière et les dispositifs externes sans qu'il soit nécessaire d'avoir recours à une mémoire RAM statique à accès multiples. Des bascules maintiennent les signaux de données dans l'unité mathématique pendant l'accès à la mémoire RAM statique. Le processeur de front possède une série d'instructions personnalisées qui optimise la mise en oeuvre de structures de filtres de synthèse musicale complexes. Un générateur de bruit blanc sur puce fournit rapidement des données pseudo-aléatoires pour certaines des instructions.
PCT/US1995/004354 1994-04-07 1995-04-06 Processeur de simulation d'instruments de musique WO1995027939A1 (fr)

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Citations (10)

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