WO1995000953A1 - Generateur de haute tension constante - Google Patents

Generateur de haute tension constante Download PDF

Info

Publication number
WO1995000953A1
WO1995000953A1 PCT/US1994/006022 US9406022W WO9500953A1 WO 1995000953 A1 WO1995000953 A1 WO 1995000953A1 US 9406022 W US9406022 W US 9406022W WO 9500953 A1 WO9500953 A1 WO 9500953A1
Authority
WO
WIPO (PCT)
Prior art keywords
clock
current
high voltage
comparator
input
Prior art date
Application number
PCT/US1994/006022
Other languages
English (en)
Inventor
A. Karl Rapp
Original Assignee
National Semiconductor Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corporation filed Critical National Semiconductor Corporation
Priority to KR1019950705926A priority Critical patent/KR960703483A/ko
Priority to JP7502832A priority patent/JPH08512190A/ja
Publication of WO1995000953A1 publication Critical patent/WO1995000953A1/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor

Definitions

  • the invention broadly relates to electrically erasable programmable read only memory (EEPROM) devices. It specifically is directed to the V high voltage generator employed for suGh devices. V is typically about 15 volts produced by a charge pump in an on-chip integrated circuit configuration. A charge pump is ordinarily employed to boost the typically 3- or 5-volt operating supply to the desired value. Desirably, the charge pump and other chip circuits should be operative down to about a 2 volt supply level and be capable of producing the 15 volt V pp .
  • EEPROM electrically erasable programmable read only memory
  • This invention makes use of a oopending patent application, serial no. 08/070.614 ⁇ filed 02 June / 1993, titled SELF-TIMING FOUR-PHASE CLOCK GENERATOR.
  • This application is directed to a clock generator having four phases that are employed to drive a oharge-pump high-voltage generator.
  • the clock frequenoy is directly proportional to an input current.
  • a plural-stage charge pump is driven from a plural-phase clock-signal generator which produces a clock fre ⁇ quenoy that is proportional to an input current.
  • the high voltage is applied to a voltage divider, the output of which is 0 connected to the inverting input of a comparator having an out ⁇ put current proportional to the differential input.
  • the non- inverting comparator input is connected to a band-gap reference potential source which provides a stable, temperature- and supply-voltage independent reference voltage. At startup, when 5 V is zero, the comparator output current will saturate at its highest value because of the large difference in input voltages.
  • the clock oscillator will be driven to its highest frequenoy as a result. Since a charge pump will develop an elevated output after a number of clock cycles, its output will 0 quickly rise.
  • V pp has risen to its desired value and the voltage-divider output has risen to equal the band-gap reference potential, the comparator output current will go to zero and the dock will stop. As long as V pp is at its desired value, the comparator output will remain at zero. However, when current is 5 drawn from V pp , the V pp level will begin to fall and the comparator will produce an output current so that the clock generator will produce a clock signal.
  • the dock frequenoy will be adjusted by the feedback circuit so that the charge pump will replenish the drop in V pp due to current drain. Thus, the oharge-pump frequency will be controlled so that the desired V level is maintained, independent of the magnitude of current drain.
  • Figure 1 is a blook diagram of the overall V pp voltage-regulator circuit.
  • Figure 2 is a graph showing the truncated response of the voltage comparator.
  • Figure 3 is a graph showing the waveforms for a four-phase clock signal.
  • Figure 4 is a schematic diagram of a charge-pump element.
  • Figure 5 is a blook diagram of a charge pump suitable for use in the figure 1 blook diagram.
  • Capacitor 16 is the V output voltage supply filter capacitor.
  • the V output is developed by a charge pump
  • a voltage divider composed of resistors 12 and 13, produces a controlled fraction of V pp at node 14. In a typical system, this fraction is about 1/12.5. This fraction is applied to the inverting input of comparator 15 which provides a controlled-current output as shown by current source 15'.
  • a band gap-reference 17 is connected to the noninverting input of comparator 15. Comparator 15 applies a current to a four-phase clock generator 18.
  • Figure 2 is a graph showing the performance of comparator 15 which is shown having a truncated response.
  • the differential input of comparator 15 is zero, the output current is zero. It will remain at zero as long as the inverting input is equal to or greater than the non-inverting input.
  • the noninverting input falls below (goes negative with respect to) the band gap reference, the comparator output current rises linearly until it reaches a limiting value (to the left of zero in figure 2) .
  • FIG 3 is a graph showing the clock phases generated in block 18 of figure 1. The production of these signals is taught in detail and claimed in copending application serial number 08/070,614 , which is cited above. For under- standing the operation of figure 1, all that must be known about the four-phase clock is illustrated in figure 3.
  • Each waveform transition is separated from a causitive opposite-polarity tran ⁇ sition by a current-controlled inverter gate-delay period.
  • Clock phases B and D are positive pulses with widths defined by delay buffer elements whose delay intervals are established inversely proportional to an input current.
  • the clock frequency is directly proportional to the input current which is obtained from comparator 15.
  • the clock generator shuts off and the frequency is zero.
  • the clock starts and the frequency thereof is directly proportional to current.
  • V is zero, and a startup is to be initiated.
  • the potential at node 14 is zero and the bandgap reference of 1.2 volts will overwhelm comparator 15 and maximum current will be forced into dock generator 18.
  • the clocks will start up and run at maximum frequency, thus causing charge pump 11 to rapidly raise the potential at terminal 10.
  • V rises and at some point comparator 15 will reach its linear region.
  • the dock frequency will be slowed and V pp will rise more slowly.
  • the rise of V will continue at a lesser rate until a 15 volt condition is reached and the clock will stop. This set of oon- ditions result in the startup time of the system being greatly reduced over that of a system that employs a fixed dock frequenoy.
  • FIG. 4 is a schematic diagram of a charge pump stage which responds to the four-phase clock to produce a voltage-multiplier action that will develop the required V pp .
  • This oharge-pump stage includes a pair of cascaded pump elements which alternately oondu ⁇ t to transfer charge.
  • the stage input is terminal 20 and the output is terminal 21.
  • Node 22 is at the midstage location.
  • Clocks A through D are respectively connected to terminals 23 through 26.
  • the first pump element, which receives docks B and C, contains N channel transistors 27 and 28.
  • N ohannel deple- tion transistors 29 and 30 have their source and drain electrodes shorted together so that they function as capacitors.
  • Transistor 30 is made larger than transistor 29 by a factor in excess of about 40 so that it provides a proportionately larger capacitance.
  • Transistor 30 is one of the bucket-brigade capaci ⁇ tances that contributes charge to be V output current.
  • Transistor 29 serves only to aid the charging of the gate of transistor 27.
  • a and D is composed of N channel transistors 31 and 32.
  • N channel depletion transistors 33 and 34 have their source and drain electrodes shorted together so that they too function as capacitors.
  • Transistor 34 is made larger than transistor 33 by a factor in excess of about 40 so that it provides a propor ⁇ tionately larger capacitance.
  • clocks B and D are alternately high so that transistors 27 and 31 are alternately turned on.
  • Transistor 27 will charge capacitor 30 during the time interval when clock C is low. It will be noted that when clock C is initially driven low, node 22 is pulled down thereby turning transistor 28 off. Thus, capacitor 30 will charge. Then, when clock C goes high, node 22 will rise and turn transistor 28 on, so that the gate of transistor 27 is connected to its drain. In this state, transistor 27 will be unilaterally conductive so that capacitor 30 cannot discharge through transistor 27. This action traps the charge on capacitor 30. After a sufficient number of clock cycles, node 22 will rise and approach a level of about the potential at terminal 20 plus a substantial portion of the peak voltage of clock C.
  • clock D will go high and capacitor 33 will couple the pulse to transistor 31 so as to turn it on. This occurs after clock A goes low so as to pull terminal 21 low, thereby turning transistor 32 off.
  • capacitor 34 will charge through transistor 31 from node 22. Then, when clock A goes high, the pulse at terminal 21 will turn transistor 32 on so that the gate of transistor 31 is returned to its drain thereby rendering transistor 31 unidirectionally conductive and the charge on capacitor 34 will be blocked.
  • capacitor 34 will charge to a level approaching the clock A peak value above the level of node 22. Thus, a nearly clock peak voltage will be added to the nearly peak voltage at node 22. Thus, an increment of nearly two clock peak voltages will be developed at terminal 21.
  • FIG. 1 a number of figure 4 stages can be cascaded so as to develop any desired output voltage.
  • FIG. 5 seven such stages comprise block 11 of figure 1. These stages are shown being operated from the four clock phases from generator 18.
  • Each of pump stages 36 through 42 comprise the circuit of figure 3. With this number of stages, the circuit of figure 3 can easily operate down to a two volt V QD level. A two volt input at terminal 20 needs to be multiplied only 7.5 times to achieve a 15 volt V .
  • the seven stages shown can provide this out ⁇ put after a relatively few number of clock cycles.
  • N channel transistor 43 which has its gate connected to its drain, acts as a one way coupling device that will pass the positive voltage out of pump element 42 to terminal 10.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
  • Read Only Memory (AREA)

Abstract

Un circuit générateur de haute tension produit une haute tension utilisée pour le fonctionnement d'une mémoire morte programmable effaçable par voie électrique. Le circuit est décrit en vue de s a mise en oeuvre dans un MOS comme un élément de puce. Une pompe de chargement composée de plusieurs étages est excitée par un signal d'horloge multiphase généré par un générateur de signal d'horloge multiphase dont la fréquence est déterminée par une intensité d'entrée. Un comparateur dont l'intensité de sortie est liée à une entrée différentielle présente une réponse tronquée; l'intensité de sortie est nulle si l'entrée différentielle est nulle et maximale lorsque le potentiel de l'entrée non inversante dépasse nettement le potentiel de l'entrée inversante. L'entrée non inversante est couplée à un potentiel de référence et l'entrée inversante est couplée de façon à recevoir une fraction contrôlée de la haute tension produite par la pompe de chargement. Au démarrage, la haute tension est à zéro et le comparateur applique une intensité maximale au générateur d'horloge, ce qui permet un fonctionnement à la fréquence maximale et minimise le temps de démarrage. Après le démarrage, la fréquence d'horloge est proportionnelle à l'intensité tirée du circuit de générateur de haute tension.
PCT/US1994/006022 1993-06-28 1994-05-27 Generateur de haute tension constante WO1995000953A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1019950705926A KR960703483A (ko) 1993-06-28 1994-05-27 일정 고전압 발생기(constant high voltage generator)
JP7502832A JPH08512190A (ja) 1993-06-28 1994-05-27 一定高電圧生成器

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US8384193A 1993-06-28 1993-06-28
US08/083,841 1993-06-28

Publications (1)

Publication Number Publication Date
WO1995000953A1 true WO1995000953A1 (fr) 1995-01-05

Family

ID=22181041

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1994/006022 WO1995000953A1 (fr) 1993-06-28 1994-05-27 Generateur de haute tension constante

Country Status (3)

Country Link
JP (1) JPH08512190A (fr)
KR (1) KR960703483A (fr)
WO (1) WO1995000953A1 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2735920A1 (fr) * 1995-06-21 1996-12-27 Sgs Thomson Microelectronics Generateur de haute tension avec oscillateur asservi a basse tension d'alimentation
EP1211790A2 (fr) * 2000-12-01 2002-06-05 Texas Instruments Deutschland Gmbh Circuit intégré à semi-conducteur
DE10259054A1 (de) * 2002-12-17 2004-07-15 Infineon Technologies Ag Spannungsgeneratoranordnung
DE10259055A1 (de) * 2002-12-17 2004-07-15 Infineon Technologies Ag Spannungsgeneratoranordnung

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101375864B1 (ko) * 2006-12-11 2014-03-17 삼성디스플레이 주식회사 전압 승압 장치, 전압 승강압장치 및 액정표시장치
KR100885788B1 (ko) * 2007-10-30 2009-02-26 주식회사 하이닉스반도체 펌프 회로
CN104022641B (zh) * 2014-06-05 2016-09-07 辉芒微电子（深圳）有限公司 防过冲且快启动的电荷泵电路及其防过冲的快启动方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2035629A (en) * 1978-07-21 1980-06-18 Rca Corp Regulated high voltage power supply
US4631421A (en) * 1984-08-14 1986-12-23 Texas Instruments CMOS substrate bias generator
EP0297545A2 (fr) * 1987-07-01 1989-01-04 Hitachi, Ltd. Circuit d'alimentation de puissance
EP0350462A2 (fr) * 1988-07-06 1990-01-10 STMicroelectronics S.r.l. Régulation de la tension de sortie d'un multiplicateur de tension
WO1993014555A1 (fr) * 1992-01-14 1993-07-22 Sierra Semiconductor B.V. Circuit de reaction pour generateur de haute tension de cmos servant a programmer des cellules de memoire (e)eprom

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2035629A (en) * 1978-07-21 1980-06-18 Rca Corp Regulated high voltage power supply
US4631421A (en) * 1984-08-14 1986-12-23 Texas Instruments CMOS substrate bias generator
EP0297545A2 (fr) * 1987-07-01 1989-01-04 Hitachi, Ltd. Circuit d'alimentation de puissance
EP0350462A2 (fr) * 1988-07-06 1990-01-10 STMicroelectronics S.r.l. Régulation de la tension de sortie d'un multiplicateur de tension
WO1993014555A1 (fr) * 1992-01-14 1993-07-22 Sierra Semiconductor B.V. Circuit de reaction pour generateur de haute tension de cmos servant a programmer des cellules de memoire (e)eprom

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
KURIYAMA ET AL: "A 5V-only 0.6um Flash EEPROM with row decoder scheme in triple-well structure", IEEE INTERNATIONAL SOLID STATE CIRCUITS CONFERENCE., vol. 35, February 1992 (1992-02-01), NEW YORK US, pages 152 - 153 *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2735920A1 (fr) * 1995-06-21 1996-12-27 Sgs Thomson Microelectronics Generateur de haute tension avec oscillateur asservi a basse tension d'alimentation
US5821639A (en) * 1995-06-21 1998-10-13 Sgs-Thomson Microelectronics S.A. High voltage generator with oscillator servo-linked to low supply voltage
EP1211790A2 (fr) * 2000-12-01 2002-06-05 Texas Instruments Deutschland Gmbh Circuit intégré à semi-conducteur
EP1211790A3 (fr) * 2000-12-01 2003-01-02 Texas Instruments Deutschland Gmbh Circuit intégré à semi-conducteur
DE10259054A1 (de) * 2002-12-17 2004-07-15 Infineon Technologies Ag Spannungsgeneratoranordnung
DE10259055A1 (de) * 2002-12-17 2004-07-15 Infineon Technologies Ag Spannungsgeneratoranordnung
DE10259054B4 (de) * 2002-12-17 2006-10-26 Infineon Technologies Ag Spannungsgeneratoranordnung
DE10259055B4 (de) * 2002-12-17 2006-11-16 Infineon Technologies Ag Spannungsgeneratoranordnung

Also Published As

Publication number Publication date
JPH08512190A (ja) 1996-12-17
KR960703483A (ko) 1996-08-17

Similar Documents

Publication Publication Date Title
US5694308A (en) Method and apparatus for regulated low voltage charge pump
KR910001643B1 (ko) 승압회로
US6538907B2 (en) Voltage drop DC-DC converter
JP3183672B2 (ja) チャージポンプ装置
US6414863B1 (en) Frequency control circuit for unregulated inductorless DC/DC converters
US6597235B2 (en) Voltage boost circuits using multi-phase clock signals
JP2531742B2 (ja) 電圧制御発振回路
JP3260144B2 (ja) チャージポンプ装置
US5532653A (en) Supply voltage compensated charge pump oscillator
EP1298777A1 (fr) Dispositif élévateur de tension régulée à haute efficacité
US9419516B2 (en) DC-DC voltage converter and conversion method
JP4853003B2 (ja) ソフトスタート回路及びこれを用いたスイッチング電源
JPH0556636A (ja) 電圧変換装置
US4736167A (en) PLL frequency synthesizer
JPH0511805B2 (fr)
US6373311B1 (en) Oscillator and switch-over control circuit for a high-voltage generator
JP2002247838A (ja) 昇圧回路及びドレイン、ソース間電圧緩和型インバータ回路
KR0167692B1 (ko) 반도체 메모리장치의 차아지 펌프회로
WO1995000953A1 (fr) Generateur de haute tension constante
US6977828B2 (en) DC-DC converter applied to semiconductor device
KR20050008541A (ko) 전원장치
JP2614938B2 (ja) チャージポンプ装置
US5398001A (en) Self-timing four-phase clock generator
US6369628B1 (en) Phase alignment circuit for periodic signals
US7535206B2 (en) Synchronous rectifying type switching regulator control circuit and semiconductor integrated circuit including the same

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP KR

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 1994918156

Country of ref document: EP

WWW Wipo information: withdrawn in national office

Ref document number: 1994918156

Country of ref document: EP

122 Ep: pct application non-entry in european phase
122 Ep: pct application non-entry in european phase
122 Ep: pct application non-entry in european phase