WO1994023373A1 - Dispositif pour une carte-mere de processeur de signaux numeriques permettant d'adapter un processeur rapide a des composants lents - Google Patents

Dispositif pour une carte-mere de processeur de signaux numeriques permettant d'adapter un processeur rapide a des composants lents Download PDF

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Publication number
WO1994023373A1
WO1994023373A1 PCT/AT1994/000035 AT9400035W WO9423373A1 WO 1994023373 A1 WO1994023373 A1 WO 1994023373A1 AT 9400035 W AT9400035 W AT 9400035W WO 9423373 A1 WO9423373 A1 WO 9423373A1
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WO
WIPO (PCT)
Prior art keywords
processor
speed bus
bus area
low
bus
Prior art date
Application number
PCT/AT1994/000035
Other languages
German (de)
English (en)
Inventor
Ronald Hasenberger
Original Assignee
Elin Energieanwendung Gesellschaft M.B.H.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elin Energieanwendung Gesellschaft M.B.H. filed Critical Elin Energieanwendung Gesellschaft M.B.H.
Priority to EP94912986A priority Critical patent/EP0692118A1/fr
Publication of WO1994023373A1 publication Critical patent/WO1994023373A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol

Definitions

  • the invention relates to a device for a digital signal processor board for adapting a fast processor to slow components.
  • a circuit is known in which the separation of the bus into a local bus and into a system bus is proposed to solve this problem.
  • the interface between the local bus and the system bus is controlled by a bus controller.
  • the local bus is designed as a multimaster bus, in which the processor works closely coupled to an arithmetic coprocessor, but decouples from the rest of the bus.
  • ERS ⁇ ZBL ⁇ TT REGEL26
  • the bus is divided into a fast and a slow bus in such a way that the entire periphery and the (large) main memory are located on the slow bus.
  • a fast bus contains a fast (mostly S-) RAM, in which part of the main memory is mapped. This division takes place essentially for cost reasons, since executing the entire main memory with fast RAMs would explode the costs.
  • the cache controller first determines whether the date requested by the processor is in the cache. If this is the case, the cache is accessed and the corresponding date is quickly made available.
  • This circuit arrangement is disadvantageous because the date, if it is not in the cache (cache miss), has to be fetched from the slow main memory, for which a considerable waiting time of the processor is required.
  • the use of a cache system for the aforementioned purpose thus results in a reduction in the number of accesses on the slow bus.
  • Furthermore, there is an extension of the impulses when accessing the slow bus because slow blocks have to be controlled.
  • the detection of cache hit or miss requires a very large amount of components, since the content of the cache changes depending on the type of previous actions. This results in a very complex, therefore prone to failure and expensive construction.
  • the object of the invention is to design a universal solution which enables the control of faster and slower process sequences with only one
  • a hold-time enhancer separates the digital signal processor board into a high-speed bus area and a low-speed bus area, and that the hold-time enhancer is connected to the high-speed bus area via data buses and connected to the low speed bus area.
  • the invention is advantageous because the separation by means of a hold-time enhancer makes it possible to create two bus areas, each with a precisely defined purpose, using only one processor.
  • the high-speed bus area corresponds entirely to the bus timing offered by the processor.
  • a buffer is provided in the hold-time enhancer for data transfer from the low-speed bus area to the processor, which is enabled for read access to the peripherals connected to the low-speed bus area and can be switched with high resistance in all other cases, and that Storage of the data in the high-speed bus area by means of a latch, which can be switched transparently as soon as write access to one of the units on the low-speed bus area can be carried out, and that the buffer by means of an associated controller that controls the driver part one or more processor cycles long switched on, then switched to high impedance, and that all signals from the processor to the low-speed bus area are routed via series resistors immediately after the latch acting as driver, and that between write and read access to the peripherals connected to the low-speed bus area There is at least one processor cycle and the default state at the low spe ed bus range is chosen to be high impedance, and that a delay in
  • Control lines by means of a D flip-flop is provided, and that this delay is synchronous to each next rising edge of a processor clock is feasible.
  • the driver of the processor is relieved by the configuration according to the invention, so that compliance with the data sheet timing is ensured in the high-speed bus area. Since the entire signal timing is newly generated for the low speed bus area, this low speed bus area is highly independent of the processor used; this makes it easy to switch to a different (e.g. faster) processor. In the case of a mechanically corresponding modular design, that circuit part (of course excluding the hold-time enhancer) which contains the low-speed bus area can be left unchanged.
  • 1 shows the circuit of the hold-time enhancer used.
  • 2 shows, in the form of a block diagram, the drive of an electric car, for the control of which the invention can be used.
  • Fig. 3 shows, also as a block diagram, a schematic diagram of the entire circuit arrangement of the digital signal processor board, which is used for the control of this electric car.
  • a buffer 101 is used in the hold-time enhancer 21 for data transfer from the low-speed bus area 54 to the processor 22, which enables read access to the peripherals connected to the low-speed bus area and switches in a high-resistance manner in all other cases .
  • the data are stored in the high-speed bus area by means of a latch 102, which can be switched transparently as soon as write access to one of the units on the low-speed bus area takes place.
  • the buffer 101 is activated by means of an assigned controller 103, which switches the driver part 29 on for one or more processor cycles stops, then switched to high impedance.
  • Control lines 105a, 105b by means of a D flip-flop 106 are necessary until the next rising edge of the processor clock.
  • a first charger la feeds a traction battery 2 of higher voltage and a second charger 3a of lower voltage.
  • the voltage from the traction battery 2 is fed via a switch 4 and a direct current measuring device 5a to a power section designed as an inverter 8.
  • Inverter 8 feeds an asynchronous machine 9 via two current measuring devices 6a, 7a.
  • a measuring line 6b, 7b leads to the digital signal processor board 11 both from the direct current measuring device 5a and from the current measuring devices 6a, 7a.
  • a further measuring line 5b connects the direct current measuring device 5a to the digital signal processor.
  • the inverter 8 is connected via a control line 17 to a converter control module 61 of the digital processor circuit board 11.
  • External transmitters 13a, 13b, 13c and 13d are connected via an interface board 12, which forms the transition to the lower voltage range.
  • the data for its internal program ROM are transferred from a boot ROM 23 with the aid of a boot memory selection line 25 to an analog-digital signal processor 22 fed.
  • a program ROM 24 for the analog-digital signal processor 22 can be accessed via the first and the second data bus 26, 27.
  • the boot ROM 23 is connected to the first and second data buses 26, 27;
  • a driver 29 is provided as a serial interface and is connected to the analog / digital signal processor 22 via a serial data bus 73.
  • the data from the analog-digital signal processor 22 in the high-speed bus area 53 can be fed via a data memory select line 31 to a first module 60 in the low-speed bus area 54 containing an address decoder 51 and a watchdog 67.
  • the current changes necessary for calculating the temporal changes in the current space vector amount of the asynchronous machine 9 are taken from the two current measuring devices 6a, 7a arranged between the converter 8 and the synchronous machine 9, shown in FIG. 2, and one provided in the low-speed bus area (54), first module 52 consisting of two analog-digital converters 68, 69 and an ADC timing 74, which is connected to the fourth data bus 30.
  • the control parameters of the asynchronous machine 9 can be fed via the third and fourth data bus 28, 30 to an EEPROM 59, which is connected to the address decoder 51 via the third data bus 28.
  • a converter control module 61 consisting of three dead time generators 62 and a converter protection 63 is provided, which is connected via the fourth data bus 30 to the EEPROM 59 and an incremental input 57 for conventional flow position determination. All signals that are not critical in terms of timing are fed via the fourth data bus 30 to a second module 55 consisting of an analog-digital converter 70 with multiple multiplexer and a FIFO 71 and an ADC control 72.
  • a second module 55 consisting of an analog-digital converter 70 with multiple multiplexer and a FIFO 71 and an ADC control 72.
  • There is also an external timer 64 and a real-time clock 65 and a battery-backed RAM 66 existing third module 58 is provided, which is connected to the third and fourth line buses 28, 30.
  • an analog-digital converter 56 is used, which is connected to the third and fourth data buses 28, 30.
  • the system bus is divided into two parts: a fast part (high-speed bus area), which can often be accessed, and a slow part (low-speed bus area), which is rarely accessed.
  • the high-speed bus range corresponds entirely to the bus timing offered by the processor.
  • the following properties are realized in the low speed bus area: a longer hold time in order to be able to connect slow blocks; longer pulse times, whereby the first corner frequency of the power density spectrum is set to a lower frequency; Less frequent signal changes, as a result of which the probability of a fault in analog circuit parts being reduced by the (fast) edges of the bus signals is reduced.
  • the separation of the processor from the long lines of the low-speed bus area also provides additional protection for the processor against interference trapped on long lines of the low-speed bus area.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)
  • Bus Control (AREA)

Abstract

L'invention concerne un dispositif pour une carte-mère de processeur de signaux numériques, permettant d'adapter un processeur rapide à des composants lents. Dans la technique des microprocesseurs ou dans le traitement électronique des données, il est fréquent qu'une installation comprenne aussi bien un bus rapide auquel il est souvent accédé, qu'un bus lent auquel sont raccordés des périphériques lents. Il est fréquent dans de tels cas de ne disposer, pour des raisons économiques, que d'un seul processeur pour les deux bus, ce qui pose un problème. Selon l'invention, l'utilisation d'un enrichisseur de temps de maintien (21) permet de séparer la carte-mère de processeur de signaux numériques en une zone de bus à grande vitesse (53) et en une zone de bus à faible vitesse (54). L'enrichisseur de temps de maintien (21) est relié par l'intermédiaire de bus de données (26, 27 et 28, 30) à la zone de bus à grande vitesse (53) ainsi qu'à la zone de bus à faible vitesse (54). L'invention est avantageuse du fait que la séparation de la carte-mère de processeur de signaux numériques, au moyen d'un enrichisseur de temps de maintien, permet d'obtenir deux zones de bus aux applications bien déterminées, en n'utilisant qu'un seul processeur.
PCT/AT1994/000035 1993-04-01 1994-03-31 Dispositif pour une carte-mere de processeur de signaux numeriques permettant d'adapter un processeur rapide a des composants lents WO1994023373A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP94912986A EP0692118A1 (fr) 1993-04-01 1994-03-31 Dispositif pour une carte-mere de processeur de signaux numeriques permettant d'adapter un processeur rapide a des composants lents

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
AT66693A AT401117B (de) 1993-04-01 1993-04-01 Einrichtung für eine digital-signalprozessor- platine zur anpassung eines schnellen prozessors an langsame bauteile
ATA666/93 1993-04-01

Publications (1)

Publication Number Publication Date
WO1994023373A1 true WO1994023373A1 (fr) 1994-10-13

Family

ID=3496614

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/AT1994/000035 WO1994023373A1 (fr) 1993-04-01 1994-03-31 Dispositif pour une carte-mere de processeur de signaux numeriques permettant d'adapter un processeur rapide a des composants lents

Country Status (3)

Country Link
EP (1) EP0692118A1 (fr)
AT (1) AT401117B (fr)
WO (1) WO1994023373A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3753232A (en) * 1972-04-06 1973-08-14 Honeywell Inf Systems Memory control system adaptive to different access and cycle times
EP0081961A2 (fr) * 1981-12-10 1983-06-22 Data General Corporation Système synchrone de bus de données avec vitesse de données automatiquement variable
US5058054A (en) * 1990-02-06 1991-10-15 Analogic Corporation Data transmission device for interfacing between a first rate data acquisition system and a second rate data processing system

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE421151B (sv) * 1979-01-02 1981-11-30 Ibm Svenska Ab Kommunikationsstyrenhet i ett databehandlingssystem
DE3735828C2 (de) * 1986-10-24 1994-11-10 Hitachi Ltd Verfahren zur Wiederaufnahme der Ausführung von Anweisungen nach einer Unterbrechung in einer mikroprogrammgesteuerten Datenverarbeitungsvorrichtung
CA2007737C (fr) * 1989-02-24 1998-04-28 Paul Samuel Gallo Operations de transfert de donnees entre deux bus asynchrones

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3753232A (en) * 1972-04-06 1973-08-14 Honeywell Inf Systems Memory control system adaptive to different access and cycle times
EP0081961A2 (fr) * 1981-12-10 1983-06-22 Data General Corporation Système synchrone de bus de données avec vitesse de données automatiquement variable
US5058054A (en) * 1990-02-06 1991-10-15 Analogic Corporation Data transmission device for interfacing between a first rate data acquisition system and a second rate data processing system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
V. BOCHEV: "DSP system comprises only five major chips.", EDN ELECTRICAL DESIGN NEWS., vol. 36, no. 18, September 1991 (1991-09-01), NEWTON, MASSACHUSETTS US, pages 159 *

Also Published As

Publication number Publication date
ATA66693A (de) 1995-10-15
EP0692118A1 (fr) 1996-01-17
AT401117B (de) 1996-06-25

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