WO1993025967A1

WO1993025967A1 - System for aiding debugging of integrated circuit microprocessor

Info

Publication number: WO1993025967A1
Application number: PCT/JP1992/000743
Authority: WO
Inventors: Yuukou Matsumoto
Original assignee: V.M. Technology Corp.
Priority date: 1992-06-08
Filing date: 1992-06-08
Publication date: 1993-12-23

Abstract

In the system, a machine instruction fetched by an instruction fetching unit (3) is transferred to an instruction recognizing unit (6) as well as to an instruction decoding unit (4). The instruction recognizing unit (6) judges whether or not the operation-code part of the transferred machine instruction is the operation-code to generate a break operation. When an affirmative decision is made, the instruction decoding unit (4) is informed of the message to that effect. The instruction decoding unit (4) transfers a predefined decode result instructing the break operation instead of the decode result of the fetched instruction to an instruction executing unit (5). Thereby, the break operation is started by the instruction executing unit. Therefore, without sensing the address generated with the execution of the instruction, a break is caused at the time intended by the program, and the debugging can be performed.

Description

Specification

Debugging support system for integrated circuit microprocessor

〔Technical field〕

The present invention relates to debugging support software for supporting program development in an integrated circuit microphone processor.

(Background technology)

When developing a program for an integrated circuit microprocessor, a debug support system called a debugger is often used, which is a software alone or a combination of software and software. In particular, when developing a microprocessor application system, a so-called software debugger consisting only of software often cannot handle the problem, so a debug support system using software is currently used.

Debugging support systems that use this hardware are called emulators or emulators, and have been put into practical use in a number of forms. A general function of these debug support systems is called a break. A break is a function in which the execution of a program to be debugged is interrupted once, and control is transferred to the debug program. ₍ The contents of registers and memory that are being executed by debugging It is possible to check the execution history up to that point.

When this break is performed by external hardware, the address output by the microphone processor is checked, and if the address targeted for the break is output, the microprocessor is interrupted. A method of multiplying, or a method of using hardware to overwrite an instruction to be fetched by a microprocessor when an address to be broken is output is adopted. However, in the method of detecting an address and generating an interrupt, in the case of a microprocessor that is highly pipelined internally, the execution inside the microprocessor is much faster when the address is detected externally. There are platforms where execution cannot be interrupted at the intended time because it is ahead of schedule. Also, the latter method of overriding an instruction that attempts to perform a fu- ture is not a problem if the starting address of the instruction is clear, but otherwise, it may cause a malfunction. In order to avoid such malfunctions, an instruction interpreting circuit comparable to the instruction decoder in the microprocessor must be provided externally to observe the instruction stream. In this case, the amount of hardware becomes extremely large. It will be lost. Furthermore, if the microprocessor has a cache system or the like, it will be more difficult to break at the target execution stage regardless of the method used.

Therefore, it has been considered to incorporate hardware for making a break into the microprocessor. In this way, the internal evening signal can be used, so even a microprocessor with a highly pipelined microprocessor or cache system can use the appropriate internal signal. It is possible to suspend execution at the intended time.

In any case, a commonly used debug support system monitors address output and outputs a specific address, regardless of whether the hardware for that purpose is installed inside or outside the microprocessor. The basic operation of setting a break at the time of detecting is the same. Therefore, an object of the present invention is to realize a debugging support system that can set a debugging break at an intended time without detecting an address.

[Disclosure of the Invention]

An debugging support system for an integrated circuit microprocessor according to the present invention includes an instruction fetching device for fetching a machine language instruction, and an instruction decoding device for decoding a machine language instruction fetched by the instruction fetching device. Receiving the machine instruction executed by the instruction fetch device and whether or not the operation code of the machine instruction is a predetermined operation code. A command recognition device that identifies a particular operation code to the command decoding device if the operation code is a specific operation code, and a command execution device that executes the decoding result of the command decoding device. The instruction decoding device, when receiving the notification from the instruction recognition device, displays the machine language sequence fetched by the instruction fetching device on the platform. And interrupted the code operation, and summer to supply the predefined Deco generates an de results. Instruction execution device instructs a break.

Here, while the instruction execution device accepts a break and performs a debugging operation, it is desirable to control the operation of the command recognition device so that a break does not occur.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic block diagram showing main components of an embodiment of the present invention.

FIG. 2 is a partial block diagram showing a part of the example of FIG. 1 in detail. FIG. 3 is an explanatory diagram showing the configuration of a trap 'operation' control * register in FIG.

Fig. 4 shows the trap, control, register (mask) and con- trol in Fig. 2. FIG. 3 is an explanatory diagram showing the configuration of a trap.

[Best mode for carrying out the invention]

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of the main components of one embodiment of the present invention. This example is an example in which the debugging support system of the present invention is applied to a microprocessor implemented on a CMOS integrated circuit. The machine language instruction group stored in the main storage device 1 is: Fetched by the instruction switch 3 via the 6-bit external data bus 2. The machine instructions that have been flushed are transferred to the instruction decoding device 4, where they are decoded and converted into a format executable by the instruction execution device 5. The converted instruction is transferred to the instruction execution device 5, where it is executed.

Reference numeral 6 denotes an instruction recognition device, and the machine language instruction transferred from the instruction fetch device 3 to the instruction decoding device 4 is also transferred to this instruction recognition device. The instruction recognition device 6 examines the transmitted machine language sequence and determines whether or not the sequence has a specific operation code for causing a break. If it is determined that the operation code is a specific operation code, a break instruction signal S 6 is output to the instruction decoding device 4. Upon receiving the break instruction signal S6, the command decoding device 4 abandons the normal command decoding operation and generates a predefined decoding result indicating a break, This is transferred to the instruction execution device 5. Instruction execution unit 5 When the break operation instruction is received, the break operation is started and a break acceptance signal S5 is output to the instruction recognition device 6. Upon receiving the break acceptance signal S5, the command recognition device 6 interrupts the command recognition operation. That is, the fetched machine language instruction is

5 Suspends the operation to determine whether it is a specific operation code that should cause a rake. In this example, the instruction recognizing device 6 has a 32-bit width control register, which can store information on the start and restart of the break operation and the machine language instruction to be recognized, respectively. It has become. In this example, the instruction recognition device 6

, η Instruction execution unit 5 is connected by a 32-bit internal data bus 7 so that the contents of the control register in instruction recognition unit 6 can be read and written by the instructions executed in instruction execution unit 5. Has become. FIG. 2 shows the details of the connection parts of the above-mentioned instruction switch 3, instruction decoder 4, and instruction recognition unit 6. As shown in the figure

, 5, the instruction switch 3 has a buffer 31 and an input selector 32. The code buffer 31 is composed of two sets of 16-bit buffers, each of which has a 16-bit wide external data bus 2 to an external bus interface (not shown). Stores machine instructions aligned in 32 bits via. Input selector 3 2

20 Multiplexer circuit for selecting which of the 16-bit buffers that make up the buffer 31 to transfer the machine instruction stored in it.

In the instruction recognition device 6, the input code and the buffer 61 latch the machine language sequence supplied through the input selector 32, and

2 5 Outputs for 'Operation' Code 'Comparator 6 2'. The output to this trap 'operation' code 'comparator 62 is divided into four systems and supplied. The truck here In the 'operation' code 'comparator 62, the received content is the trap' operation 'code' register 6 3 where the operation 'code' at which a break should occur is stored. Is compared with the contents of This comparison operation is performed independently for each of the four systems. Next, the control 'Register evening (mask)' comparator

The comparison result in the trap 'operation' code 'comparator 62 is supplied to 64, and the output of the later-described decode PLA is supplied from the instruction decoding device 4 side. Based on these outputs and its own mask value, it is determined whether or not a predetermined operation code for causing a break has been obtained. Note that the trap 'operation' code 'resistor register 63 and the control register (mask) · comparator 64 are connected to an instruction execution device via a 32 bit internal data bus 7. Connected to 5.

The decode PLA 41 of the instruction decoding device 4 receives the machine language instruction passed through the input selector 32 of the instruction fetch device 3. The decode PLA41 decodes a machine language instruction and constantly determines whether or not the part of the machine language instruction to be decoded is an operation 'code part. The output of the decode PLA 41 is supplied to the decoded instruction buffer control circuit 42 and also to the control register (mask) 'comparator 64 of the instruction recognition device.

FIG. 3 shows the bit configuration of the trap operation 'code register 63' of the instruction recognition device 6. This register is an operation to be trapped. It is a register for storing code, and is a 32-bit 32-bit system divided into 4 units of 8 bits in accordance with the 6-bit system. It has a configuration. In the figure, the four systems of the aperture ratio are shown as “TRAP 0P-C0DE0”, “TRAP 0P-C0DE1”, These are indicated as "TRAP 0P-C0DE2" and "TRAP 0P-C0DE3". The reason for making these partition units 8-bit configuration is that the machine language instructions in this example are variable-length in 8-bit units. Therefore, if the system of the machine language instruction is different, the configuration of the register 63 is different accordingly. Similarly, the reason for adopting the 32 bit configuration as a whole is to match the internal bus width of 32 bits, and the total number of bits varies depending on the internal bus width.

FIG. 4 shows the bit configuration of the control register in the control register (mask) comparator 64. This in register is used to specify the type of operation code to be trapped, whether or not to execute the trap, and a trap specific to one of the four systems, called ΟΡ ΟΡ-CODEOJ. Used for controlling the aperture mask. This register is 32 bits, of which the lower 17 bits are used for these purposes. 1 7-bit

Of these, the lower 8 bits are bits (ビッ, ΜΑΡ1, ΜΑΡ2, ΜΑΡ3) for specifying the format of the operation code to be trapped. In this configuration, two bits are allocated. The microprocessor of this example is capable of processing three different types of operation and code instructions.

The 20 bits are used to specify which of the three types of operation 'code to trap is in. If the system of machine language instructions handled is different, the bit structure for specifying the system will be different accordingly. In addition, if there is only one operation code system, such a bit group is unnecessary.

2 Γ>

Next, the middle 8 bits of the control register (TRAP OP-CODEO-MASK) are a group of bits used to expand the comparison circuit. This is a group of control bits for controlling the extension performed for only one system called “0P-C0DE0”. By setting one bit of this control bit group to “1”, comparison of the corresponding bits in the {0} -C0DE0 ”system is prohibited. Such control can be applied to all of the four comparison systems, or can be set so as not to be applied to any of them. Next, the 17th bit (TEN) of the register is used to control the enable / disable of the entire comparison circuit. This bit can be read and written by an instruction via the internal bus 7. Also, this bit can be forcibly set to the disabled state by a signal indicating that the operation 'code * trap is accepted and executed.

In the microprocessor of this example, first, a specific operation code that should cause a break is specified by a trap 'operation' code 'register 63 (see FIG. 3) in the instruction recognizer 6. ). Also, set the contents of the control 'register (mask) in the control' register (mask) 64 (see Fig. 4). In this state, execute the program to be debugged. During execution of the program, the machine language instruction fetched by the instruction fetch device 3 is transferred to the instruction decoding device 4 and also to the instruction recognition device 6 for n. In the trap 'operation • code' comparator 62 of the instruction recognition device 6, the operation code of the received machine language instruction is stored in the operation stored in the register 63. · Compare with code.

When an instruction operation code for causing a break is supplied, a match is obtained in the comparator 62, and a signal indicating a match is output from the control register (control register). Supplied to 6 4. Control 'Register (mask)' Control Based on the coincidence signal, the decoded PLA output obtained from the instruction decoding device 4 and the mask value of its own, the data 64 obtains a specific operation code for generating a break. Make a final determination of whether or not it has been performed. When it is determined that the specific operation code has been obtained, a signal S6 indicating the determination is output to the decoded instruction buffer control circuit 42 of the instruction decoding device 4. Thereafter, the instruction decoding device 4 generates a predefined decoding result indicating a break instead of the decoding result of the machine language instruction latched by the instruction fetching device 3, The generated decoding result is transferred to the instruction execution device 5. This causes the instruction execution device 5 to start a break operation.

When the break operation is started, a break acceptance signal S 5 is output from the instruction execution device 5 to the instruction recognition device 6. When the break acceptance signal S5 is received, the 17th bit (TEN) of the trap 'control' register of the instruction recognition device 6 is forcibly set to a state indicating that comparison operation is not permitted. You. Therefore, after this, the relative narrowing operation in the instruction recognition device is not performed. When the break operation is completed, the output of the break acceptance signal S6 stops, and the content of the 17th bit of the trap 'control' register is returned to a state where the relative operation is permitted again.

As described above, in this example, the instruction recognition device is arranged to detect a specific operation code to cause a break, and when such an operation code is detected, the instruction decoding device is controlled. Then, a break operation is started. Therefore, it is possible to cause a break at an intended time and perform a program debugging operation without being based on an address generated with the execution of an instruction. Also, in this example, the operation of the instruction recognition device is set to a non-permitted state during the execution of the break operation. It is possible to avoid a break during the operation. [Industrial applicability]

As described above, in the integrated circuit microprocessor of the present invention, hardware capable of detecting that a machine instruction having a specific operation code has been fetched is incorporated therein. Break operation is started when a specific operation code is detected. Therefore, according to the present invention, it is not necessary to control the start of the break operation based on an address generated with the execution of an instruction. Therefore, it is possible to solve the problem of the break operation control method based on address detection that it is difficult to generate a break at an intended time, and it is possible to easily realize an intended program debugging operation.

Claims

The scope of the claims

1. An instruction fetching device for fetching a machine language instruction, an instruction decoding device for decoding a machine language instruction fetched by the instruction witch, and a machine fetched by the instruction fetching device Language instruction, and identifies whether the operation 'code' of this machine instruction is a predetermined specific operation 'code, and if it is a specific operation code, An instruction recognition device for notifying the instruction decoding device to that effect, an instruction execution device for executing a decoding result of the instruction decoding device, and io, wherein the instruction decoding device comprises: When a message is received from the instruction recognition device, the decoding operation of the machine language instruction fetched by the instruction fetching device is interrupted, and a break is instructed in advance. It generates a defined already decode result, characterized in that is adapted to supply the decode result to the instruction execution unit integrated

A debugging support system for 15-circuit microprocessors.

2. The instruction execution device notifies the instruction recognition device that a break operation is being performed, and interrupts the operation code identification operation by the instruction recognition device. The integrated circuit microprocessor according to claim 1, wherein

2 デバッグ Debugging support system.