WO1993020550A1 - Dispositif d'affichage a cristaux liquides avec systeme d'adressage permettant d'obtenir des valeurs elevees de contraste et de luminosite tout en conservant une grande vitesse de commutation - Google Patents

Dispositif d'affichage a cristaux liquides avec systeme d'adressage permettant d'obtenir des valeurs elevees de contraste et de luminosite tout en conservant une grande vitesse de commutation Download PDF

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Publication number
WO1993020550A1
WO1993020550A1 PCT/JP1993/000421 JP9300421W WO9320550A1 WO 1993020550 A1 WO1993020550 A1 WO 1993020550A1 JP 9300421 W JP9300421 W JP 9300421W WO 9320550 A1 WO9320550 A1 WO 9320550A1
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WO
WIPO (PCT)
Prior art keywords
lines
line
time
selection
selected simultaneously
Prior art date
Application number
PCT/JP1993/000421
Other languages
English (en)
Inventor
Theo L. Welzen
Original Assignee
Citizen Watch Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co., Ltd. filed Critical Citizen Watch Co., Ltd.
Priority to EP93906873A priority Critical patent/EP0587913B1/fr
Priority to DE69321804T priority patent/DE69321804T2/de
Priority to KR1019930703675A priority patent/KR100244905B1/ko
Priority to JP5517308A priority patent/JPH06508451A/ja
Publication of WO1993020550A1 publication Critical patent/WO1993020550A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
    • G09G3/3625—Control of matrices with row and column drivers using a passive matrix using active addressing

Definitions

  • the invention relates to a display device comprising a liquid-crystal material between two supporting plates kept at a defined spacing whose surfaces face each other, a pattern of N line electrodes being arranged on the one surface, and a pattern of column electrodes being
  • the device comprises a control circuit for supplying data signals to the column electrodes and furthermore comprises a line-scanning circuit for periodic scanning of the line electrodes and supplying suitable line-select voltage signals.
  • Such display devices are known and are usually operated by way of multiplex-addressing according to the so-called RMS mode.
  • the pixels are switched, from a first state to an optically different second state with the aid of the line-scanning circuit which periodically scans the line electrodes using a line-select pulse of magnitude V s and with the aid of the control circuit for supplying data signals to the column electrodes, which control circuit applies data voltages of magnitude ⁇ V d to the column electrodes over the time during which a line electrode is being scanned, in such a way that the optical state which is effected in a display element is determined by the so-called Root Mean
  • RMS Square
  • the RMS voltage value V 2 for the display elements not selected, i.e. the display elements in the ON state, is given by:
  • V 2 2 (V s + V d ) 2 /N + (N - 1) * V d 2 /N (1)
  • V 1 for the display elements not selected, i.e. the display elements in the OFF state is given by:
  • V 1 2 (V s - V d ) 2 /N + (N - 1) * V d 2 /N (2)
  • Figure 2 shows, in diagrammatic form, a transmission voltage characteristic of a picture cell belonging to that display device.
  • N max ⁇ (S 2 + 1)/(S 2 - 1) ⁇ (3)
  • V d 2 V 1 2 * ⁇ 0.5/(1 - Q) ⁇ (5)
  • Q 2 N max -1
  • a greater multiplexing rate in other words a higher value for N max , requires a steeper slope of the
  • Figure 1 in diagrammatic form, shows part of a matrix-oriented display device 1 having N max selection lines (line
  • the information to be displayed is supplied to the data lines (column electrodes) 3.
  • the display elements 4 At the location of the crossing points of the selection lines 2 and the data lines 3 there are the display elements 4. Depending on the information supplied on the data lines 3, the display elements 4 are in an ON state or OFF state.
  • the image information (data voltage +V d ) is applied via the column electrodes.
  • line 2 a is selected which, together with the information then present on the data lines 3 a , 3 b , 3 c
  • the information then present on the data lines 3 determines the state of the pixels 4 ba , 4 bb , 4 bc .
  • the display element reacts to the cumulative effect of a number of addressing pulses (or select pulses).
  • a liquid-crystal display element in particular reacts in the same way as if it had been addressed by a sinusoidal-wave signal or a stepped-wave signal or the like, having the same RMS voltage value as that of the 'ON' and 'OFF' voltages V 2 and V 1 given by the expressions (1) and (2).
  • selection lines N max is related to the value of the ratio V 2 /V 1 (threshold slope).
  • the line-select voltage V s in particular will become high (the data or column voltage V d in this addressing scheme should always be chosen to be lower than the threshold voltage of the optical effect).
  • the object of the invention is to provide a display device in which, with a given high multiplexing rate and a given thin liquid-crystal layer thicknesses (which are important to effect fast switching), the "FRAME RESPONSE" behaviour described is reduced or eliminated, so that, while maintaining fast switching, contrast and brightness are improved, specifically in such a way that those contrast values and brightness values are achieved or approximated which arise if the optical effect shows true RMS behaviour.
  • said display device in which, with a given high multiplexing rate and a given thin liquid-crystal layer thicknesses (which are important to effect fast switching), the "FRAME RESPONSE" behaviour described is reduced or eliminated, so that, while maintaining fast switching, contrast and brightness are improved, specifically in such a way that those contrast values and brightness values are achieved or approximated which arise if the optical effect shows true RMS behaviour.
  • an addressing scheme is used in which the single, large select pulse for every line per frame time has been replaced by a plurality of smaller pulses which are distributed over the frame time in a regular manner.
  • the invention is based on the insight that using a plurality of smaller pulses during the frame time, instead of the single large select pulse per line, is possible if a plurality of lines are selected
  • Simultaneous selection of a plurality of lines during the frame time leads not only to a select signal having a smaller amplitude compared to standard RMS addressing, but at the same time provides the possibility of splitting the select signal with its associated selection period into a plurality of separate select pulses having a corresponding shortened pulse duration.
  • Figure 1 shows a diagram indicating a part of matrix-oriented display device
  • Figure 2 shows a transmission voltage characteristic of a picture cell of the display device
  • Figure 3 shows a transmission behaviour of the display device over one frame time
  • FIG. 4a and 4b show one embodiment of the present invention
  • Figure 5a to 5c show diagrams indicating wave forms for the second selection timespan ta/2 chosen from a point in time following after half the frame time;
  • FIGS. 6a and 6b show another embodiment of the present invention
  • Figure 7 shows the resulting voltages of the line-select signals and the data signals for elements 11 to 22 as shown in Figs. 6a and 6b during the selection time tb;
  • Figures 8a and 8b show the relationship between the selection timespan tb/4 and associated voltage over the frame time
  • Figure 9 shows the line-select signals used to define smaller selection periods than the total selection period tc.
  • Figure 4a shows voltage waveforms for the line signals and the data signals which can be used to write the information as represented in this figure by means of he designations 'ON' and 'OFF'.
  • the line-select voltage signals of the two lines selected simultaneously are mutually orthogonal.
  • the amplitude of the line-select voltage signals for the two lines to be selected simultaneously is equal to ⁇ A.
  • the amplitude of the data voltages in Figure 4a which are supplied to the columns during the addressing time t a to write the desired information, during one half of the addressing time is equal to ⁇ D and during the other half of the addressing time is equal to 0.
  • the actual shape of a data voltage signal is determined by information to be displayed (i.e. the pixels 'ON' or 'OFF').
  • Figure 4a gives the four data voltage signals by which the possible information contents of the pixels in question which occur on the selected lines can be
  • the pixels 1, 2, 5, 7 of the matrix illustrated in Figure 4a are assumed to be in the 'OFF' state; the pixels 3, 4, 6, 8 are in the 'ON' state.
  • Figure 4b shows the resulting voltages over the pixels 1 to 8 inclusive of Figure 4a over the addressing time t a .
  • the resulting voltage has been derived as the difference voltage V line - V column .
  • Figure 4b shows that the RMS voltage values during the addressing time t a of the pixels 1, 2, 5, 7 which are in the 'OFF' state, are equal to one another.
  • the RMS voltage values of the 'ON' elements are equal to one another during t a .
  • any 'ON' element and 'OFF' element in the matrix has the same RMS voltage value during the rest of the frame time (that is, during t f - t a ).
  • V on 2 ⁇ t a * (A 2 /2 + (A + D) 2 /2)
  • V off 2 ⁇ t a * (A 2 /2 + (A - D) 2 /2 )
  • N multiplexed (in this illustrative embodiment: N) and the slope of the transmission voltage characteristic curve.
  • the amplitude A of the line-select voltages for simultaneous selection of two lines is smaller by a factor of 2 1/2 than the select voltage V s required
  • the complete addressing time t a is in fact composed of two equal timespans t a /2 with associated
  • the second selection timespan t a /2 may, for example, be chosen from a point in time following after half the frame time. This is illustrated in Figure 5 with the aid of a matrix of 10 lines. For the sake of simplicity, only the line-select voltage signals of the 10 lines during the scanning of the matrix over one frame time are shown. The situation illustrated is that in which two adjacent lines are selected. As has already been
  • Figure 5a shows the scanning cycle in which the addressing time t a has not been split.
  • Figure 5b the line selection period t a has been split into two timespans t a /2, the second half of the total addressing time t a taking place from a point in time which is situated halfway along the frame time.
  • Figure 5c shows the
  • the addressing scheme described in Figure 5b results in an addressing method in which the single select pulse of standard Alt & Pleshko multiplex addressing has been replaced by two separate select pulses having smaller amplitudes and preferably occurring at points in time which are uniformly distributed over the frame time.
  • the maximum amplitude of the voltage over a pixel (during selection) for this addressing method is smaller than in the case of standard Alt & Pleshko addressing.
  • FRAME RESPONSE an addressing scheme can be chosen in which more than two lines are selected simultaneously, for example 4, or 6, or 8 etc.
  • addressing of an N-line matrix can take place if 4 lines are selected simultaneously during the frame scan.
  • Figure 6a shows voltage waveforms for the line signals which can be used to write the information as illustrated in this Figure.
  • Figure 6a shows only three columns i, j, k, with the associated information contents of the pixels 11 to 22 inclusive which correspond to the crossing points of the columns i, j, k and the illustrated first group of four lines to be selected simultaneously.
  • simultaneously selected lines are mutually orthogonal, in such a way that the select signal of one of the four lines to be selected simultaneously has a half-period which corresponds to the addressing time t b .
  • Figure 6a this is the first (uppermost) line of the group of lines to be selected simultaneously. It is not necessary, however, for this particular line to have this line-select voltage wave form.
  • the amplitude of the line-select voltage signals for the four lines to be selected simultaneously is equal to ⁇ B.
  • Figure 6b illustrates in which manner the data signals can be determined in order to write the
  • Pixel 11 should be in the 'OFF' state.
  • the data signal applied to pixel 11 during selection should be a data voltage signal which is in phase with the line-select signal of the corresponding selected line.
  • This signal is drawn in Figure 6b in the column whose heading reads COLUMN i.
  • the amplitude X of this signal (and the amplitude of the line-select signals) are determined by the requirement that the RMS voltage value of the 'OFF' elements must have a determined value while the RMS voltage value of the 'ON' elements should be as large as possible.
  • Pixel 12 should be in the 'OFF' state, and in analogy with the situation described above, the data voltage signal to be applied to pixel 12 during selection should be in phase with the line-select signal of the corresponding line.
  • This signal is drawn in Figure 6b in the column having the heading COLUMN i. The amplitude of this signal is equal to the amplitude of the above data signal for pixel 11.
  • Pixel 13 should be 'ON'. Therefore, a data signal should be applied to pixel 13 during selection, which is in antiphase with the line-select signal of the
  • This data signal for pixel 13 again has the same amplitude as the two data signals mentioned earlier of pixels 11 and 12 and is shown in the column whose heading is COLUMN i.
  • the data signal for pixel 14 during selection follows on the basis of reasoning analogous to that given for the other pixels in the column i in question. When summed, said four data signals produce the data signal as drawn in Figure 6b in the column whose heading is COLUMN i. During selection of the four lines to which the elements 11, 12, 13, 14 belong, this signal is applied to column i. In a
  • the data signal can be determined which has to be applied to column j in order to produce the required information contents of
  • data signals should be applied in which 5 levels can be distinguished, namely ⁇ E/2, 0.
  • the combination of these levels in a data signal applied to a column 1 during selection is determined by the image contents of the elements in the column 1 in question.
  • Figure 7 shows the resulting voltages (defined as V line - V column ) for elements 11 to 22 inclusive of Figure 6a during the selection time t b utilising the line-select signals drawn in Figure 6a and the data signals
  • element is equal to the RMS voltage value of any 'ON' element.
  • V on 2 ⁇ t b * (B 2 + B * E/2 + E 2 /4)
  • V off 2 ⁇ t b * (B 2 - B * E/2 + E 2 /4)
  • V off V 1
  • V on V 1
  • N multiplexed (in this illustrative embodiment: N) and the slope of the transmission voltage characteristic curve.
  • the amplitude B of the line-select voltages for simultaneous selection of four lines is smaller by a factor of 2 than the select voltage V s required according to standard Alt & Pleshko RMS multiplex addressing (for identical number of lines N of the matrix).
  • the complete addressing time t b is composed of four equal timespans t b /4 with associated characteristic voltage values for the line-select signals and the data signals.
  • the selection timespans t b /4 with the associated voltages can be distributed over the frame time.
  • Figure 8 This is illustrated in Figure 8 with the aid of a matrix of 12 lines. For the sake of simplicity, only the line-select voltage signals of the 12 lines during the scanning of the matrix over a frame time are shown. The situation illustrated is that in which four adjacent lines are selected simultaneously. As has already been indicated earlier, this is not necessary.
  • Figure 8a shows the scanning cycle in which the line selection period t b has not been split.
  • Figure 8b the line selection span t b has been split into four
  • timespans t b /4 which are uniformly distributed over the frame time.
  • Other distributions are obviously also possible, for example a uniform distribution over the frame time of two selection timespans which are each equal to t b /2.
  • Pleshko multiplex addressing has been replaced by four separate select pulses having smaller amplitudes and preferably occurring at points in time which are
  • the maximum amplitude of the voltage over the frame time is smaller than in the case of standard Alt & Pleshko addressing.
  • simultaneous addressing of four lines it is also possible, as already discussed, to make use of, for example, two separate selection time-spans having an equal duration t b /2 which may or may not be uniformly distributed over the frame time.
  • an addressing scheme comprising simultaneous selection of four lines and splitting of the total selection period t b into four separate, equal selection period spans as outlined in Figure 8b, are not sufficient to reduce or eliminate "FRAME RESPONSE", an addressing scheme can be chosen in which more than four lines are selected and the total selection period is again split into a number of
  • selection timespans which may or may not be equal and which are or are not uniformly distributed over the frame time, in analogy to the manner as illustrated with the aid of the addressing schemes in which two or four lines are selected simultaneously.
  • Figure 9 The select signals in Figure 9 are again orthogonal, and one of the voltage signals used has a half-period which corresponds to the addressing time (selection time).
  • the data signals which are used in combination with said line-select signals can be
  • the line-select signals of Figure 9 can again be used to define smaller selection periods than the total selection period t c shown in this figure, for example eight selection timespans of magnitude t c /8. Said eight selection periods may, for example, be uniformly
  • the amplitude Y n of the line-select signals and the maximum amplitude X n of the data signals will have to be chosen according to:
  • n The table below illustrates for a number of values of n, how many and which voltage levels may occur in the data signals which, in combination with line-select signals whose waveform is indicated in the illustrative embodiments given earlier, will lead to a desired image content.
  • n 2 ⁇ X 2 , 0
  • n 3 ⁇ X 3 , ⁇ X 3 /3
  • n 4 ⁇ X 4 , ⁇ X 4 /2, 0
  • n 5 ⁇ X 5 , ⁇ 3 * X 5 /5, ⁇ X 5 /5
  • n 6 ⁇ X 6 , ⁇ 4 * X 6 /6, ⁇ 2 * X 6 /6, 0

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

Dans un dispositif d'affichage à cristaux liquides possédant une structure matricielle, plusieurs lignes sont sélectionnées simultanément pendant le balayage périodique des électrodes de ligne, et le temps total de sélection est divisé en un nombre d'intervalles de temps qui sont répartis sur tout le temps de trame. Les tensions de sélection requises peuvent être choisies de façon qu'elles soient nettement plus petites que les tensions selon le système d'adressage multiplex d'Alt & Pleshko normalisé, ce qui permet d'avoir des tensions nettement plus basses s'appliquant aux éléments d'affichage pendant la sélection. Ces tensions, qui sont plus basses, combinées avec un nombre d'intervalles de temps répartis sur le temps de trame, ce nombre d'intervalles de temps résultant de la division de la période totale de sélection par temps de trame, conduisent à une réduction de ce que l'on appelle la 'REPONSE DE TRAME', ce qui permet d'obtenir un contraste et une luminosité améliorées d'affichages à cristaux liquides à commutation rapide, si l'on compare avec le système d'adressage Alt & Pleshko.
PCT/JP1993/000421 1992-04-01 1993-04-01 Dispositif d'affichage a cristaux liquides avec systeme d'adressage permettant d'obtenir des valeurs elevees de contraste et de luminosite tout en conservant une grande vitesse de commutation WO1993020550A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP93906873A EP0587913B1 (fr) 1992-04-01 1993-04-01 Dispositif d'affichage a cristaux liquides avec systeme d'adressage permettant d'obtenir des valeurs elevees de contraste et de luminosite tout en conservant une grande vitesse de commutation
DE69321804T DE69321804T2 (de) 1992-04-01 1993-04-01 Flüssigkristallanzeige mit einem adressierungsschema zum erreichen von hohem kontrast und hoher helligkeit mit instandhaltung von schnellem schalten
KR1019930703675A KR100244905B1 (ko) 1992-04-01 1993-04-01 고속스위칭을 유지하면서 높은 콘트라스트와높은 휘도값을 성취하기 위하여 어드레싱 구조로 된 액정디스플레이장치
JP5517308A JPH06508451A (ja) 1992-04-01 1993-04-01 高速スイッチングを保ちつつ高コントラスト及び高輝度値を達成するアドレッシング方式を備えた液晶表示装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
NL9200606A NL194875C (nl) 1992-04-01 1992-04-01 Weergeefinrichting bevattende een vloeibaar-kristal materiaal.
NL9200606 1992-04-01

Publications (1)

Publication Number Publication Date
WO1993020550A1 true WO1993020550A1 (fr) 1993-10-14

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PCT/JP1993/000421 WO1993020550A1 (fr) 1992-04-01 1993-04-01 Dispositif d'affichage a cristaux liquides avec systeme d'adressage permettant d'obtenir des valeurs elevees de contraste et de luminosite tout en conservant une grande vitesse de commutation

Country Status (6)

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EP (1) EP0587913B1 (fr)
JP (1) JPH06508451A (fr)
KR (1) KR100244905B1 (fr)
DE (1) DE69321804T2 (fr)
NL (1) NL194875C (fr)
WO (1) WO1993020550A1 (fr)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0585466A1 (fr) * 1992-03-05 1994-03-09 Seiko Epson Corporation Procede et circuit pour exciter des elements a cristaux liquides et dispositif d'affichage
EP0720140A2 (fr) * 1994-12-26 1996-07-03 Hitachi, Ltd. Méthode et appareil pour la sélection et l'application d'une tension de données dans un dispositif d'affichage à cristaux liquides à adressage actif
US5596344A (en) * 1991-07-08 1997-01-21 Asahi Glass Company Ltd. Driving method of driving a liquid crystal display element
US5877738A (en) * 1992-03-05 1999-03-02 Seiko Epson Corporation Liquid crystal element drive method, drive circuit, and display apparatus
US5900856A (en) * 1992-03-05 1999-05-04 Seiko Epson Corporation Matrix display apparatus, matrix display control apparatus, and matrix display drive apparatus
US5959603A (en) * 1992-05-08 1999-09-28 Seiko Epson Corporation Liquid crystal element drive method, drive circuit, and display apparatus
US6252572B1 (en) 1994-11-17 2001-06-26 Seiko Epson Corporation Display device, display device drive method, and electronic instrument

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100499431B1 (ko) * 1996-08-19 2005-11-04 세이코 엡슨 가부시키가이샤 액정 장치의 구동방법
KR102593763B1 (ko) 2023-05-23 2023-10-26 주식회사 스푼라디오 청취자 반응에 기반하여 방송 호스트의 방송 진행 방향을 유도하는 방법 및 이를 위한 서버

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DE2752602A1 (de) * 1977-10-31 1979-05-03 Bbc Brown Boveri & Cie Verfahren zum betrieb einer elektrooptischen anzeigevorrichtung

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DE2752602A1 (de) * 1977-10-31 1979-05-03 Bbc Brown Boveri & Cie Verfahren zum betrieb einer elektrooptischen anzeigevorrichtung

Non-Patent Citations (1)

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INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS 'Conference record of the 1988 international display research conference' 1988 , IEEE , NY *

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5596344A (en) * 1991-07-08 1997-01-21 Asahi Glass Company Ltd. Driving method of driving a liquid crystal display element
US6252573B1 (en) 1992-03-05 2001-06-26 Seiko Epson Corporation Drive method, a drive circuit and a display device for liquid crystal cells
US6084563A (en) * 1992-03-05 2000-07-04 Seiko Epson Corporation Drive method, a drive circuit and a display device for liquid crystal cells
US7138972B2 (en) 1992-03-05 2006-11-21 Seiko Epson Corporation Liquid crystal element drive method, drive circuit, and display apparatus
US6611246B1 (en) 1992-03-05 2003-08-26 Seiko Epson Corporation Liquid crystal element drive method, drive circuit, and display apparatus
US5877738A (en) * 1992-03-05 1999-03-02 Seiko Epson Corporation Liquid crystal element drive method, drive circuit, and display apparatus
US5900856A (en) * 1992-03-05 1999-05-04 Seiko Epson Corporation Matrix display apparatus, matrix display control apparatus, and matrix display drive apparatus
EP0585466A4 (en) * 1992-03-05 1996-11-06 Seiko Epson Corp Method and circuit for driving liquid crystal elements, and display apparatus
US5963189A (en) * 1992-03-05 1999-10-05 Seiko Epson Corporation Drive method, a drive circuit and a display device for liquid crystal cells
US6452578B1 (en) 1992-03-05 2002-09-17 Seiko Epson Corporation Liquid crystal element drive method, drive circuit, and display apparatus
US6208323B1 (en) 1992-03-05 2001-03-27 Seiko Epson Corporation Drive method, a drive circuit and a display device for liquid crystal cells
EP0585466A1 (fr) * 1992-03-05 1994-03-09 Seiko Epson Corporation Procede et circuit pour exciter des elements a cristaux liquides et dispositif d'affichage
US5959603A (en) * 1992-05-08 1999-09-28 Seiko Epson Corporation Liquid crystal element drive method, drive circuit, and display apparatus
US6252572B1 (en) 1994-11-17 2001-06-26 Seiko Epson Corporation Display device, display device drive method, and electronic instrument
EP0720140A3 (fr) * 1994-12-26 1997-02-26 Hitachi Ltd Méthode et appareil pour la sélection et l'application d'une tension de données dans un dispositif d'affichage à cristaux liquides à adressage actif
EP0720140A2 (fr) * 1994-12-26 1996-07-03 Hitachi, Ltd. Méthode et appareil pour la sélection et l'application d'une tension de données dans un dispositif d'affichage à cristaux liquides à adressage actif

Also Published As

Publication number Publication date
NL194875C (nl) 2003-05-06
NL194875B (nl) 2003-01-06
JPH06508451A (ja) 1994-09-22
DE69321804D1 (de) 1998-12-03
DE69321804T2 (de) 1999-05-12
EP0587913A1 (fr) 1994-03-23
EP0587913B1 (fr) 1998-10-28
KR100244905B1 (ko) 2000-02-15
NL9200606A (nl) 1993-11-01

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