Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
  • H01L21/321—After treatment
  • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
  • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
  • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
  • H01L21/3065—Plasma etching; Reactive-ion etching
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
  • H01L21/3105—After-treatment
  • H01L21/311—Etching the insulating layers by chemical or physical means
  • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Definitions

• This invention relates to a method of patterning oxide for the fabrication of integrated circuits using laser pantography.
• the patterning of oxide is one of the most basic and repeated steps in the fabrication of integrated circuit devices particularly in silicon microelectronics.
• Silicon dioxide (Si0 2 ) is often used as a mask against ion implantation or diffusion. It is also used as an isolation layer to define transistor geometries.
• this oxide patterning is done using photolithography techniques.
• Photolithography employs wet chemical processes for coating and developing a photoresist layer. The photolithography process required for each oxide delineation comprises a series of several steps. The photolithography process is a source of contamination and defect generation and often produces a loss of circuit yields.
• the present invention relates to a method of using a laser to provide a method of etching openings in a silicon dioxide (Si0 2 ) pattern on an integrated circuit or other semiconductor element.
• a thin layer, for example, 2,000 A, of amorphous silicon is blanket deposited over the surface area of an integrated circuit or other semiconductor element upon which an oxide pattern is to be delineated.
• a focused laser beam with sufficient power having a wavelength of, for example, 5,145 A as a point heat source and placing the integrated circuit
• the desired pattern is etched in the amorphous silicon.
• the semiconductor substrate is then placed in a plasma etcher or reactive ion etcher (RIE) .
• RIE reactive ion etcher
• a plasma etcher using a gas, such as CHF 3 which has a selectivity ratio of Si0 2 :Si equal to 10:1
• the laser etched pattern in the amorphous silicon can be transferred to the silicon dioxide.
• the amorphous silicon layer can be removed, if desired.
• One advantage of the present invention is that all wet chemical steps may be eliminated during etching of the oxide when fabricating integrated circuits.
• the use of the present invention is easily adapted to automation where standard machine interface ("SMIF") boxes for transferring substrates between machines are used. Therefore, clean room requirements are reduced or eliminated, providing for a truly all dry process for the fabrication of integrated circuits.
• SMIF standard machine interface
• Figure 1 illustrates a first step in accordance with a preferred embodiment of the present invention
• Figure 2 shows the second step in accordance with a preferred embodiment of the present invention
• Figure 3 illustrates the third step in accordance with a preferred embodiment
• Figure 4 shows the resulting step in accordance with a preferred embodiment of the present invention.
• Figures 5, 6, 7 and 8 show various steps of etching using the invention to etch a metallic layer with an amorphous silicon mask.
• Figures 9, 10, 11, 12 and 13 show an alternative preferred embodiment of the invention which etches a metallic layer using both an amorphous silicon mask and a silicon dioxide etched hard mask in a double masking technique.
• DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT The Figures, by way of example, illustrate a preferred embodiment of the present invention. It should be appreciated that the oxide patterning process of the present invention may be used in connection with any type of patterning of silicon dioxide on an integrated circuit or other semiconductor element. By way of example, the invention may be used in forming the implant mask openings on an integrated circuit.
• the semiconductor substrate 10 has a thin film of Si0 2 12 which has been either grown or deposited on the substrate.
• a blanket deposition of amorphous silicon 14 is made over the thin film of Si0 2 12. It is preferable that the amorphous silicon layer 14 be less than about 2,000 A in thickness.
• a focused laser beam illustrated by the arrows 16 in Figure 2 and having a wavelength of, for example, 5,145 A, is used as a point heat source.
• the semiconductor substrate 10 having the thin film layer of Si0 2 12 and amorphous silicon layer 14 is placed in a chamber having a gaseous environment of CLj or HCl or other halogen containing gas.
• the laser beam 16 is focused on the amorphous silicon 14 and traversed along the surface of the amorphous silicon 14 in the form of the desired Si0 2 pattern openings, and by doing so, the thin amorphous silicon layer 14 is etched away.
• the laser's light and heat interact with the halogen gas environment to loosen the gas's ionic covalent bond.
• the resulting etchant gas turns the amorphous silicon layer 14 into a gas at the point of contact of the laser beam on the amorphous silicon.
• the gaseous compounds are then pumped out of the pantography chamber. Because the reaction chamber remains at room temperature, process-gas contamination of the chamber or the workplace is virtually eliminated.
• the integrated circuit device After laser etching the amorphous silicon, the integrated circuit device is then placed in plasma etcher or reactive ion etcher (RIE) to transfer (by conventional integrated circuit fabrication means) the pattern existing on the amorphous silicon to the Si0 2 layer.
• plasma etcher using a gas such as CHF 3/ a selectivity ratio of silicon
• the amorphous silicon 14 can be plasma stripped to remove the amorphous silicon layer
• the invention as described eliminates the need for wet chemistry in all processes and particularly in the use of photolithography.
• the yield loss during photolithography due to particles, contamination, over and under cutting, and bad exposure are all eliminated.
• the process can be used to pattern oxides even over metal regions and is not subject to topology or reflectivity variations existing on the integrated circuit substrate.
• Figure 5 shows this embodiment of the invention.
• the amorphous silicon layer 14 is deposited over the metallic layer 21 on the substrate 10.
• the laser 16 etches the amorphous silicon 14 in the manner of the previous embodiments.
• the etched amorphous silicon 14 is then used as a mask to etch the metallic layer 21 by placing it in a blank environment.
• the amorphous silicon layer may be removed if required or it may be left in place as shown in
• the heat flow into the metal layer 21 of this embodiment may cause a loss of the subsequent lasography effect required. This might be avoided by the use of excimer lasers to etch, or other means.
• the preferred embodiment is to
• SUBSTITUTE SHEET deposit a layer of silicon dioxide between the metal layer 21 and the amorphous silicon 14, as shown in Figure 9.
• laser 16 then will etch a mask in the amorphous silicon 14.
• the silicon dioxide layer 12 will then be etched through the amorphous silicon mask 14, as shown in Figure 11.
• the metal layer 21 may be etched through the hard mask provided by the silicon dioxide 12. This is a double masking technique.
• the etching of the silicon 12 and the metal layer 21 might, in theory, be done in the same chamber with a two-step process, however, it is preferable to etch the Si0 2 in a separate step from the metal in order to split the etch chemistry and for cleanliness reasons.
• the amorphous silicon layer 14 may be plasma stripped if required, as shown in Figure 13. Also, the silicon dioxide layer 12 may be removed as shown in Figure 14, if required.
• the laser can be accurately controlled during the etching of the amorphous silicon, undercutting can be minimized or can be controllably reproduced.

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• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Manufacturing & Machinery (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Plasma & Fusion (AREA)
• Drying Of Semiconductors (AREA)

Applications Claiming Priority (2)

Publications (1)

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Family Applications (1)

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Cited By (1)

Citations (3)

• 1992
  • 1992-04-27 WO PCT/US1992/003670 patent/WO1993018545A1/en active Application Filing
• 1993
  • 1993-03-25 TW TW82102266A patent/TW217465B/zh active

Patent Citations (3)

Non-Patent Citations (1)

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