WO1993010505A1 - Procede et dispositif pour controler le contenu d'images - Google Patents

Procede et dispositif pour controler le contenu d'images Download PDF

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Publication number
WO1993010505A1
WO1993010505A1 PCT/DE1991/000876 DE9100876W WO9310505A1 WO 1993010505 A1 WO1993010505 A1 WO 1993010505A1 DE 9100876 W DE9100876 W DE 9100876W WO 9310505 A1 WO9310505 A1 WO 9310505A1
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WO
WIPO (PCT)
Prior art keywords
image
ideal
real
edge
memory
Prior art date
Application number
PCT/DE1991/000876
Other languages
German (de)
English (en)
Inventor
Karl Ramlow
Peter Schneider
Heinz Stahn
Original Assignee
Karl Ramlow
Peter Schneider
Heinz Stahn
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Karl Ramlow, Peter Schneider, Heinz Stahn filed Critical Karl Ramlow
Publication of WO1993010505A1 publication Critical patent/WO1993010505A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/0002—Inspection of images, e.g. flaw detection
    • G06T7/0004—Industrial image inspection
    • G06T7/001—Industrial image inspection using an image reference approach
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/10—Segmentation; Edge detection
    • G06T7/13—Edge detection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/30—Subject of image; Context of image processing
    • G06T2207/30108—Industrial image inspection
    • G06T2207/30148—Semiconductor; IC; Wafer

Definitions

  • the invention relates to a method and an arrangement for checking the content of images by comparing a real image with an ideal image, both of which relate to the same image content, the images to be compared being broken down into elements arranged according to rows and columns, analog elements of the real image and of the ideal image are scanned in x and y coordinates, preferably directed at right angles to one another, compared with one another and the comparison result is further processed.
  • the application relates to all cases in which two nominally identical images have to be examined for differences in their equality.
  • the equality relates to the different image parameters, such as the pattern (lay-out), the gray value, the light length, the phase, the transmittance, the reflectance, the intensity, etc. Which of these parameters are to be compared in the two images depends on the converter with which the two templates should be examined.
  • the invention can be used in particular to control masks in the manufacturing process of integrated circuits.
  • the non-optical data developed on a CAD (Computer Aided Design) system is converted into the mask layout using the EBA or the OPG.
  • 10: 1 reticles, 5: 1 reticles and 5: 1 block reticles can be produced.
  • the 10: 1 and 5: 1 reticles only contain the layout of a circuit level once.
  • these reticles can be used to create 1: 1 masks for the production of integrated circuits (IC), which are repeated in a regular arrangement and accordingly reduce the lay-out of the reticle contain.
  • the lay-out of the corresponding IC level is contained several times in the 5: 1 block reticle.
  • a wide variety of errors occur in the manufacture of the masks. Defects result from dirt particles, bridges, interruptions, indentations, bulges and pinholes. In addition, picture elements are missing or parasitic picture elements are generated. These errors can lead to the failure of the IC and must therefore be determined.
  • the defect control devices (DKG) used for this purpose exist in two basic variants, see US Pat. Nos. 4,247,203, 4,347,001, 4,532,650, 4,614,430, 4,809,341.
  • a first variant two nominally identical lay-out points of two different single images of one and the same mask are successively scanned via two optically identical channels.
  • the single images are the real image and that Ideal image of the mask. If the information obtained at the end of the optical channels with the aid of an optical-electronic converter (OEW) each shows differences, there are differences in the image content and thus defects.
  • OEO optical-electronic converter
  • the advantages of this variant can be seen in the high working speed and the high resolving power (up to 0.35 ⁇ m). Their drawbacks lie in the fact that defects which are present in both individual images, so-called repeat defects, are not recognized. Furthermore, it is not possible to check individual images for completeness using CAD data. Reticles with only a single image cannot be checked at all.
  • the image content of the mask to be checked is recorded with an optical channel and a downstream OEW (real image) and compared with the correspondingly processed image from the CAD data (ideal image).
  • OEW real image
  • CAD data ideal image
  • the invention is intended to avoid the disadvantages of the prior art, so that high accuracy and speed of operation are ensured, as is low apparatus and financial expenditure.
  • the invention is therefore based on the object of designing and processing the individual images in such a way that pseudo defects are avoided and the possibility of comparing a real image with an ideal image is given regardless of whether the ideal image is present optically or as a stored data block.
  • this object is achieved in that an x-edge image and a y-edge image are produced from the real image and from the ideal image, which scans through each x-edge image in the y-direction and each y-edge image in the x direction, and in this way an x / y- and a y / x-edge image are generated that a real difference image or an ideal difference image is generated by the difference between the y / x and x / y edge images of the real image or the ideal image that by comparing the real difference image with a real comparison image is ascertained from the ideal difference image and that the ideal difference image is scanned for itself and, as a result of the survey, a defect image is created on the basis of the non-zero corners of the ideal difference image.
  • the scanning is carried out line by line parallel to the x-direction.
  • the y-edge image is made by progressively scanning columns parallel to the y-axis.
  • a single-threshold criterion is used to detect the edge transitions light / dark and dark / light.
  • the intensity value of the preceding picture element is subtracted from that of the following picture element.
  • a circuit block is arranged between the units supplying the data of the real image and the ideal image and an evaluation unit, which contains a column selection circuit and an interface, between which parallel processing columns are located.
  • the column selection circuit forwards the data coming from an OEW (4 bits wide) to the respective free processing column, forms the required threshold value and counts the picture elements scanned in an image for the sequence control.
  • Each processing column contains a memory for the x-edge image and the y-edge image as well as for the x / y-edge image and that y / x edge image, a subtraction device for the latter two edge images and an output memory.
  • the invention enables the best previously known result parameters, in particular the working speed and the resolving power, to be at least maintained, with a significant reduction in the expenditure on process, production and computing technology.
  • FIG. 2 shows a section of the conversion process shown in FIG. 1,
  • FIG. 3 shows a mask fitted into a coordinate system
  • FIG. 4 shows the pixel arrangement of a partial image
  • Figure 5 shows the block diagram of an inventive
  • FIGS. 5 and 6 shows a detail from FIGS. 5 and
  • FIG. 7 shows a simplified basic circuit diagram of a processing column.
  • Figure 1 shows that a real image 1 first in a Real difference image 2 and in the same way an ideal image 3 can be converted into an ideal difference image 4.
  • a real comparison image 5 is derived from the real difference image 2 and the ideal difference image 4, which represents the basis for a defect image 6.
  • the basic conversion process of the real image 1 and, in the same way, of the ideal image 3 into the real difference image 2 or ideal difference image 4 is shown in FIG.
  • An x-edge image 7 and a y-edge image 8 are first produced from the real image 1, and an x / y-edge image 9 and a y / x-edge image 10 are made therefrom.
  • the real difference image 2 is then derived from the edge images 9 and 10.
  • the ideal difference image 4 results from the ideal image 3.
  • FIG. 3 For a detailed representation of the derivation of the defect image 6 from the real image 1 and the ideal image 3, reference is made to FIG. 3, in which a mask 11 which is fitted into an xy coordinate system is shown.
  • the field 12 to be checked it contains a grid of individual images 13, the edges of which run parallel to the coordinate directions.
  • Each individual or partial image consists of 1024 in the x direction and 64 elements (pixels) 14 according to FIG. 4 in the y direction, which are up to ten times smaller than the smallest structure to be expected.
  • Each field of the mask 11 is scanned with a CCD line with 1024 pixels by 64 times this line in the y direction. is placed one below the other.
  • the blanking at the next line position is carried out by a device control (not shown) when the line has covered the path from the edge length of a pixel 14 to the mask 11.
  • a device control not shown
  • the 1024 * 64 pixels with 4-bit depth are stored in a correspondingly large memory.
  • a single-threshold criterion for the edge transitions light / dark and dark / light is used to process the present real image 1.
  • the intensity value of the nth pixel is subtracted from that of the (n-1) th pixel. If the difference formed in this way exceeds a predetermined threshold value S, an edge is present.
  • the above-mentioned Threshold criterion used, with the value zero being set as the threshold value.
  • the above-mentioned rules for placing the characters for the leading and trailing edges are also retained.
  • the x-edge image is now screened in the y-direction using the modified single-threshold criterion.
  • the y / x edge image is created.
  • the y-edge image is scanned in the direction x; the x / y edge image is created.
  • the values of the corresponding pixels 14 of the x / y edge image are subtracted from those of the y / x edge image, which results in the real difference image.
  • the procedure described above for obtaining the real difference image is also applied to the formation of the ideal difference image. It does not matter whether the ideal image is available as an optical image or in CAD data. In the latter case, the ideal image must first be brought into the pixel shape before it can be transformed into an ideal difference image 4.
  • the defect and image difference extraction takes place in the context of the method according to the invention as follows:
  • the real difference image is searched completely for those pixels 14 which have a non-zero value. If such a pixel is determined, the corresponding pixel of the ideal difference image is checked to determine whether the value and the sign of its value correspond to the value of the pixel in the real difference image. Due to tolerance-related x-y offsets between the real and ideal image, which are also of the same size between the real and ideal difference image, the corresponding pixels are generally the same. not to be expected; So-called raster errors occur, even if one assumes non-defective picture elements.
  • a sufficiently large environment of a corresponding pixel in the ideal difference image must be searched for the required value of the pixel from the real difference image.
  • these can be the 8 or 24 immediately adjacent pixels of the corresponding pixel in the ideal difference image. It could also be a block from one more larger number of pixels are used in which the corresponding pixel is located. If the searched pixel is found in the given environment, it is a non-defective structure. If the pixel is not found, then there is a defect. In the defect memory, which is used to record all defects, a character, for example "5", appears at the same position that the non-zero pixel has in the real difference image.
  • 15 means a real mask (real image) or a partial image of this mask.
  • a CCD line 16 which functions as an AD converter, is used to scan the mask.
  • the signals generated in the CCD line 16 when the mask 15 is scanned are fed to a circuit block 17 which is connected to a control and evaluation computer 18.
  • Analogous to the real mask row there is the ideal mask row, which begins with the ideal mask 19 and is connected to the control and evaluation computer 18 via a CCD line 20, a switch 21 and a circuit block 22.
  • a CAD data store 23 can be coupled into the ideal mask row via a CAD data converter 24 and the switch 21.
  • the switch 21 can be flipped so that it either allows the data flow from the ideal mask row or the CAD data flow to the control and evaluation computer 18, which evaluates and controls the entire control process.
  • a column selection circuit 25 is connected on the one hand to the CCD line 16 or 20 or to the CAD data conversion 24 and on the other hand to columns 26, 27, 28, 29.
  • the column selection circuit 25 has a threshold value circuit and a counter for sequence control.
  • Each of the processing columns 26 to 29 successively has an input 30, mutually parallel memories for x and y, which are denoted by 31 and 32, for the edge image x and the edge image y, which are denoted by 33 and 34, and the edge image x / y and the edge image y / x, which are designated by 35 and 36.
  • an image subtraction stage 37 for forming the real or ideal difference image and an initial Memory 38 provided.
  • Each of the processing columns 26 to 29 is connected to a DMA (Direct Memory Access) interface 39 via the output memory 38.
  • DMA Direct Memory Access
  • FIG. 7 shows the individual elements of one of the processing columns 26 to 29 and their interconnections, which allow the various edge and difference images to be produced in a simple manner by advantageously interconnecting their individual elements and multiple use.
  • the input 30 is connected to the x memory 31 and the y memory 32 via switches 41 and 42, respectively.
  • Each of the switches 41 and 42 has switch positions a, b, c and corresponds to a switch 43 downstream of the memory 31 or a switch 44 downstream of the memory 32, which have the corresponding switch positions b, c, d.
  • the memory 31 is connected to a comparator 45 and this is connected to an evaluation logic 46.
  • the evaluation logic 46 has two outputs. One output leads to a switch 47 with switch positions b and c, which correspond to the aforementioned switch positions b and c.
  • Switch position b of switch 47 is connected to switch position b of switch 41 via a line 49.
  • Switch position c of switch 47 is connected to switch position c of switch 42 via a line 48.
  • the second output of the evaluation logic 46 is one Switch 50 performed, which allows the connection 51 between the counter 52 of the column selection circuit 25 and a 16 * 16 bit memory 53 to close or open.
  • the switch 44 establishes a connection between the memory 32 and a comparator 54, which in turn is connected to an evaluation logic 55 which, like the evaluation logic 46, has two outputs.
  • One output leads to a switch 56, which in turn has two switch positions b and c, which correspond to the switch positions b and c of the switch 47 already mentioned.
  • the switch position b of the switch 56 is connected to the switch position b of the switch 42 via a line 58.
  • the switch position c of the switch 56 is connected to the switch position c of the switch 41 via a line 57.
  • a line 59 leads from the switch position c of the switch 43 to the comparator 54.
  • a line 61 leads to a component component 62, which is connected to the output memory 38 via an adder 63.
  • the second output of the evaluation logic 55 acts on a switch 65, which is located in the connection 51 between the counter 52 and a 16 * 16 bit memory 66.
  • a 20 MHz clock 67 is used to clock the counter 52 for the sequence control.
  • the output memory 38 and the 16 * 16 are also directly connected to the DMA interface 39 bit memory 53 and 66.
  • the signals coming from the CCD line 16 or the CAD data converter 24 via the switch 21 (FIG. 5) are fed by the column selection circuit 25 to the respective free column, for example the column 26, via the input 30 (FIG. 6) .
  • the threshold value circuit integrated in the column selection circuit 25 ensures that only edge transitions above a certain, practice-oriented intensity limit (a threshold value) are effective and are written into the memories 31, 32 for x and y via the switches 41, 42 in the switch positions a.
  • a CCD line 16 of 1024 pixels each experiences 64 line shifts
  • 1024, 64 * 64 picture elements are written into each of the memories 41, 42 before a transition to the next memory or to the next processing column 27, 28 or 29 takes place.
  • the transition is initiated by a central control unit 18 (FIG. 5), which generates the CCD line detection and shift, is itself influenced by this detection and shift and ends the old count after every 1024 * 64 pixels (picture elements) and that opening the new memory and initiating the new count. It acts on the AD converter 16 or 20 or on the CAD data conversion 24.
  • the counter 52 in the column selection circuit 25 is started, from the counter reading of which the sequence control, the addressing of the memories 31, 32 and possibly result in further activities.
  • the values are read line by line from the memory 31 and column by column from the memory 32, buffered, fed to the comparators 45 and 54 in the switch position b via the switches 43, 44 and compared there with the corresponding previous values.
  • det which shows whether it is an edge or not or what type of edge (leading or trailing edge) it is.
  • This signal is temporarily stored in a flip-flop integrated in the evaluation logic 46 or 55 and subjected to an evaluation with the signal from the previous comparison. This evaluation ensures that if the same edge signal occurs several times, the corresponding edge information is only set in one memory location.
  • switches 43 and 44 are switched to switch position c, so that comparator 54 is connected to memory 31 via line 59 and comparator 45 is connected to memory 32 via line 60.
  • the x-edge image contained in the memory 31 becomes columns by column and the one written in the memory 32
  • the y-edge image is read out line by line, fed to the comparator 45 or 54 and the evaluation logic 46 or 55.
  • the result is the x / y edge image, which is stored in the memory 31 via the line 57 and the position c of the switches 56 and 41, and the y / x edge image which is stored on the line 48 and the position c of the switches 47 and 42 is stored in the memory 32.
  • the image subtraction is carried out by forming differences.
  • the x / y and the y / x edge image are read out sequentially from the respective memory 31 or 32, the switches 43, 44 being in the switch position d.
  • the picture elements of the x / y edge image pass through the line 61 one after the other to the two's complement 62, where each signal is negated with a subsequent addition with a one in the last position.
  • the picture elements of the y / x edge picture are led via line 64 to the 4-bit full adder 63, in which the two's complement of the x / y edge picture is subtracted from the y / x edge picture and transferred into the output memory 38.
  • the DMA interface 39 is activated by the computer 52 of the column selection circuit 25, which empties the output memory 38 and the 16 * 16-bit buffer memories 53 and 66 and the memory contents in the control and evaluation computer 18 (Fig. 5) transfers integrated memory.
  • the evaluation column 26 is thus again available for recording pixel values.
  • the control and evaluation computer 18 serves on the one hand for the coordinated interaction of all parts of the control process with regard to the content of the images or partial images and on the other hand for displaying the coordinates of the defect locations (pixels) in the images or partial images. After that it is possible Lich, individually inspect the defects in a known manner and decide on the need to correct the respective defect or to reject an entire image or mask.
  • FIGS. 5 to 7 applies both to the formation of real difference images 2 and ideal difference images 4.
  • the real difference image 2 (FIG. 1)
  • all parasitic, surplus and defective structures are determined after its production by setting the basic values to zero in a first defect detection step.
  • missing structures are determined on the basis of the ideal difference image, in that the ideal difference image is processed independently without reference to the regular corners of the real difference image.
  • the real comparison image 5 and the defect image 6 (FIG. 1) are created in the control and evaluation computer 18 (FIG. 5).

Abstract

L'invention concerne un procédé et un dispositif pour contrôler le contenu d'images et notamment de caches lors de la fabrication de circuits intégrés. Lors de la comparaison entre une image réelle et une image idéale, les deux images sont divisées en éléments d'images disposés en colonnes et en lignes, et analysées selon les coordonnées x et y. On obtient ainsi une image marginale x et une image marginale y, qui sont analysées dans le sens y et le sens x respectivement pour former des images marginales x/y et y/x. Par soustraction des images marginales y/x et x/y de l'image réelle et respectivement de l'image idéale, on obtient une image différentielle réelle et une image différentielle idéale. En comparant l'image différentielle réelle avec l'image différentielle idéale, on obtient une image comparative réelle. Pour finir, l'image différentielle idéale seule est analysée et on obtient une image défectueuse qui permet de se prononcer sur l'utilisation ultérieure de l'image réelle.
PCT/DE1991/000876 1990-08-27 1991-11-13 Procede et dispositif pour controler le contenu d'images WO1993010505A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE4027002A DE4027002C2 (de) 1990-08-27 1990-08-27 Verfahren und Anordnung zur Kontrolle des Inhaltes von Bildern

Publications (1)

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WO1993010505A1 true WO1993010505A1 (fr) 1993-05-27

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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4027002C2 (de) * 1990-08-27 1995-10-05 Jena Engineering Gmbh Verfahren und Anordnung zur Kontrolle des Inhaltes von Bildern
JP3386025B2 (ja) * 1999-12-15 2003-03-10 株式会社ニコン 画像特徴抽出装置、画像特徴抽出方法、監視検査システム、半導体露光システム、およびインターフェースシステム
DE10361936B4 (de) * 2003-12-29 2006-04-13 Lpcon Gmbh Vorrichtung zur Fehlererkennung an Druckbildern während des Druckprozesses

Citations (4)

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Publication number Priority date Publication date Assignee Title
EP0159859A2 (fr) * 1984-04-10 1985-10-30 Motion Analysis Corporation Détecteur orthogonal de contour sur signal vidéo
US4642813A (en) * 1983-04-18 1987-02-10 Object Recognition Systems, Inc. Electro-optical quality control inspection of elements on a product
EP0246832A2 (fr) * 1986-05-19 1987-11-25 Marconi Instruments Limited Générateur pour l'alignement de motifs
DE4027002A1 (de) * 1990-08-27 1992-03-12 Jena Engineering Gmbh Verfahren und anordnung zur kontrolle des inhaltes von bildern

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3681054D1 (de) * 1985-03-29 1991-10-02 Siemens Ag Einrichtung zur detektion von kanten.

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4642813A (en) * 1983-04-18 1987-02-10 Object Recognition Systems, Inc. Electro-optical quality control inspection of elements on a product
EP0159859A2 (fr) * 1984-04-10 1985-10-30 Motion Analysis Corporation Détecteur orthogonal de contour sur signal vidéo
EP0246832A2 (fr) * 1986-05-19 1987-11-25 Marconi Instruments Limited Générateur pour l'alignement de motifs
DE4027002A1 (de) * 1990-08-27 1992-03-12 Jena Engineering Gmbh Verfahren und anordnung zur kontrolle des inhaltes von bildern

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DE4027002A1 (de) 1992-03-12

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