WO1993010505A1

WO1993010505A1 - Process and device for inspecting the content of images

Info

Publication number: WO1993010505A1
Application number: PCT/DE1991/000876
Authority: WO
Inventors: Karl Ramlow; Peter Schneider; Heinz Stahn
Original assignee: Karl Ramlow; Peter Schneider; Heinz Stahn
Priority date: 1990-08-27
Filing date: 1991-11-13
Publication date: 1993-05-27
Also published as: DE4027002C2; DE4027002A1

Abstract

In order to inspect the content of images, in particular masks used to produce integrated circuits, a process and device are disclosed. A real image and an ideal image which are both decomposed in picture elements arranged in columns and rows are scanned along x and y coordinates. An x and a y marginal images are thus produced then scanned in the y and x directions to form x/y and y/x marginal images. By calculating the differences between the y/x and x/y marginal images of the real image on the one hand and of the ideal image on the other hand, a real differential image and an ideal differential image are produced. A real comparison image is produced by comparing the real differential image with the ideal differential image. Finally, the ideal differential image is scanned in itself and a defects-containing image is generated that makes it possible to decide whether the real image may be further used or not.

Description

Method and arrangement for checking the content of images

The invention relates to a method and an arrangement for checking the content of images by comparing a real image with an ideal image, both of which relate to the same image content, the images to be compared being broken down into elements arranged according to rows and columns, analog elements of the real image and of the ideal image are scanned in x and y coordinates, preferably directed at right angles to one another, compared with one another and the comparison result is further processed. The application relates to all cases in which two nominally identical images have to be examined for differences in their equality. The equality relates to the different image parameters, such as the pattern (lay-out), the gray value, the light length, the phase, the transmittance, the reflectance, the intensity, etc. Which of these parameters are to be compared in the two images depends on the converter with which the two templates should be examined. The invention can be used in particular to control masks in the manufacturing process of integrated circuits.

As is known, according to planar technology, integrated circuits are produced in layers on a disk made of semiconducting material by photolithography (see H. Völz, Electronics for Natural Scientists, Akademie-Verlag, Berlin 1974, pp. 425-427) .Each level in the layer structure on the surface of the semiconducting material corresponds to a process step. The projection of the Image content (lay-out) of a mask on the photochemically sensitized surface of the disc made of semiconducting material. The masks are also produced in a photolithographic process. Either an electron beam exposure system (EBA) or a light-optical pattern generator (OPG) is used. In this process, the non-optical data developed on a CAD (Computer Aided Design) system is converted into the mask layout using the EBA or the OPG. In this way, 10: 1 reticles, 5: 1 reticles and 5: 1 block reticles can be produced. The 10: 1 and 5: 1 reticles only contain the layout of a circuit level once. In a correspondingly reducing repeater camera (H. Völz, op. P. 446 ff), these reticles can be used to create 1: 1 masks for the production of integrated circuits (IC), which are repeated in a regular arrangement and accordingly reduce the lay-out of the reticle contain. The lay-out of the corresponding IC level is contained several times in the 5: 1 block reticle. A wide variety of errors occur in the manufacture of the masks. Defects result from dirt particles, bridges, interruptions, indentations, bulges and pinholes. In addition, picture elements are missing or parasitic picture elements are generated. These errors can lead to the failure of the IC and must therefore be determined. The defect control devices (DKG) used for this purpose exist in two basic variants, see US Pat. Nos. 4,247,203, 4,347,001, 4,532,650, 4,614,430, 4,809,341.

In a first variant, two nominally identical lay-out points of two different single images of one and the same mask are successively scanned via two optically identical channels. The single images are the real image and that Ideal image of the mask. If the information obtained at the end of the optical channels with the aid of an optical-electronic converter (OEW) each shows differences, there are differences in the image content and thus defects. The advantages of this variant can be seen in the high working speed and the high resolving power (up to 0.35 μm). Their drawbacks lie in the fact that defects which are present in both individual images, so-called repeat defects, are not recognized. Furthermore, it is not possible to check individual images for completeness using CAD data. Reticles with only a single image cannot be checked at all.

According to a second variant, the image content of the mask to be checked is recorded with an optical channel and a downstream OEW (real image) and compared with the correspondingly processed image from the CAD data (ideal image). The advantages of the second variant can be seen in the fact that all types of templates can be checked. Their disadvantages are due to the low working speed, the low resolution (0.8 μm) and the high technical effort.

Both variants break down the optically obtained image of the mask with the aid of a CCD (Charge Coupled Devices) arrangement, a flying spot or the like into individual elements, so-called pixels. Each pixel is assigned an intensity value, which is usually subjected to an AD (Analog Digital) conversion and processed by subsequent electronics. In order to avoid the registration of so-called pseudo defects, a number of problems must be taken into account for the systems. These problems concern:

- Residual errors in the illumination of the optical channels and differences in illumination between the two optical channels Channels with each other,

Tolerances in the object, such as structure width fluctuations, position error differences of corresponding structures and the individual images with respect to one another,

- residual errors in the imaging system,

- mechanical inaccuracies of the table system and the automatic focusing,

- residual errors in the alignment of the mask axis to the axes of the systems,

- OEW and AD converter errors,

- Processing electronics noise.

For systems that are used in accordance with the second variant, there is also the fact that a metrically correct image with ideal edge transitions from the CAD data (ideal image) can be compared with a real image. To take these facts into account, a considerable amount of equipment has to be used in systems for realizing both variants.

Finally, it is known from US Pat. No. 4,669,123 to divide an image present with a few bit image depth into three intensity levels pixel by pixel. Vectors are constructed that indicate changes between the intensity planes in eight excellent directions. Defect detection is done by summing the vectors of the same direction. If there are deviations between the sums for the real and ideal images, there is a defect. In addition to the considerable implementation effort, there is no uniqueness of the defect location for a specific position.

The invention is intended to avoid the disadvantages of the prior art, so that high accuracy and speed of operation are ensured, as is low apparatus and financial expenditure.

The invention is therefore based on the object of designing and processing the individual images in such a way that pseudo defects are avoided and the possibility of comparing a real image with an ideal image is given regardless of whether the ideal image is present optically or as a stored data block.

According to the invention, this object is achieved in that an x-edge image and a y-edge image are produced from the real image and from the ideal image, which scans through each x-edge image in the y-direction and each y-edge image in the x direction, and in this way an x / y- and a y / x-edge image are generated that a real difference image or an ideal difference image is generated by the difference between the y / x and x / y edge images of the real image or the ideal image that by comparing the real difference image with a real comparison image is ascertained from the ideal difference image and that the ideal difference image is scanned for itself and, as a result of the survey, a defect image is created on the basis of the non-zero corners of the ideal difference image. When the x-edge image is created, the scanning is carried out line by line parallel to the x-direction. Similarly, the y-edge image is made by progressively scanning columns parallel to the y-axis. To process the geometrically present images, a single-threshold criterion is used to detect the edge transitions light / dark and dark / light. The intensity value of the preceding picture element is subtracted from that of the following picture element. This creates geometrically dissimilar, electronically processable edge formations. For the universal applicability of the It is advantageous if the method according to the invention is in the ideal image in non-optical form.

Due to tolerance-related x-y offsets between the real and the ideal image or the real and ideal difference image, there is generally the corresponding picture elements do not match between the two pictures (raster errors). Therefore, a sufficiently large environment of the corresponding picture elements in the respective ideal picture must be searched for the required value of the picture elements of the real picture. Depending on the permissible raster error, these can be the eight immediately adjacent picture elements of the corresponding picture element in the case of an 8 environment or the 24 further image elements in the case of a 24 environment, etc. If the value searched for is found in the respective environment, it is a non-defective structure. The starting value and the sought value must match both in terms of amount and sign. If this value is not found, it is a defect that is recorded in the defect memory.

To carry out the method according to the invention, an arrangement is used in which a circuit block is arranged between the units supplying the data of the real image and the ideal image and an evaluation unit, which contains a column selection circuit and an interface, between which parallel processing columns are located. The column selection circuit forwards the data coming from an OEW (4 bits wide) to the respective free processing column, forms the required threshold value and counts the picture elements scanned in an image for the sequence control. Each processing column contains a memory for the x-edge image and the y-edge image as well as for the x / y-edge image and that y / x edge image, a subtraction device for the latter two edge images and an output memory. There is a direct connection to the interface from the sequence control counter of the column selection circuit. By means of a suitable interconnection within a processing column, it is also possible to use only two memories, each of which is used for storing the x or y values, the x or y edge image. This simple arrangement which can be implemented with little effort is characterized by the features set out in the characterizing part of claim 5.

The invention enables the best previously known result parameters, in particular the working speed and the resolving power, to be at least maintained, with a significant reduction in the expenditure on process, production and computing technology.

The invention is explained below with reference to the schematic drawings. Show it:

1 shows the block diagram of the conversion process of a real image into a defect image,

FIG. 2 shows a section of the conversion process shown in FIG. 1,

FIG. 3 shows a mask fitted into a coordinate system,

FIG. 4 shows the pixel arrangement of a partial image,

Figure 5 shows the block diagram of an inventive

Arrangement,

6 shows a detail from FIGS. 5 and

FIG. 7 shows a simplified basic circuit diagram of a processing column.

Figure 1 shows that a real image 1 first in a Real difference image 2 and in the same way an ideal image 3 can be converted into an ideal difference image 4. A real comparison image 5 is derived from the real difference image 2 and the ideal difference image 4, which represents the basis for a defect image 6. In order to arrive at the defect image 6, it is necessary to influence the real comparison image by the ideal difference image 4. The basic conversion process of the real image 1 and, in the same way, of the ideal image 3 into the real difference image 2 or ideal difference image 4 is shown in FIG. An x-edge image 7 and a y-edge image 8 are first produced from the real image 1, and an x / y-edge image 9 and a y / x-edge image 10 are made therefrom. The real difference image 2 is then derived from the edge images 9 and 10. In the same way, the ideal difference image 4 results from the ideal image 3.

For a detailed representation of the derivation of the defect image 6 from the real image 1 and the ideal image 3, reference is made to FIG. 3, in which a mask 11 which is fitted into an xy coordinate system is shown. In the field 12 to be checked, it contains a grid of individual images 13, the edges of which run parallel to the coordinate directions. Each individual or partial image consists of 1024 in the x direction and 64 elements (pixels) 14 according to FIG. 4 in the y direction, which are up to ten times smaller than the smallest structure to be expected. Each field of the mask 11 is scanned with a CCD line with 1024 pixels by 64 times this line in the y direction. is placed one below the other. The blanking at the next line position is carried out by a device control (not shown) when the line has covered the path from the edge length of a pixel 14 to the mask 11. In the explanation of the forming process it is assumed that the 1024 * 64 pixels with 4-bit depth are stored in a correspondingly large memory. A single-threshold criterion for the edge transitions light / dark and dark / light is used to process the present real image 1. The intensity value of the nth pixel is subtracted from that of the (n-1) th pixel. If the difference formed in this way exceeds a predetermined threshold value S, an edge is present. If this threshold value is exceeded several times at the edge, for example S = 2 and n- (n-1)> S, (n + 1) -n> S, then it is ensured that the "edge" signal is only set in one pixel becomes. In the case of an edge with a positive difference (leading edge), the character "1" is set in the pixel of the minute end, at which the threshold is exceeded for the first time. In the example given, "1" is set in pixel n. In the case of an edge with a negative difference (trailing edge), by definition, the character "2" is placed in the pixel of the subtrahent, for which the difference in amount last exceeds the threshold S. For example, if S = 2 and | n- (n-1) |> S, | (n + 1) -n |> S and | (n + 2) - (n + 1) | <S the character " 2 "in the pixel n + 1.

Starting from the real image in the dimensions 1024 * 64 pixels, the single-threshold criterion described is applied twice to this real image, namely

- for the first time in the + x direction, starting in the 64th line at the first pixel up to the 1024th pixel and then progressing line by line up to line 1. The x-edge image is created.

- the second time in the + y direction, starting at 64.

Row at pixel 1 to pixel 64 and then progressing in columns to the 1024th column, 64th pixel. The y-edge image is created. In the x and y edge image only the characters "1" and "2" appear on the x and y edges of the image elements. The difference in intensity is thus digitized. If only one pixel is assigned a value ≠ O in a procedure, the characters for the leading and trailing edge should be added. The character "3" thus appears in this pixel. Parallel to the screening of the real image or after completion of the same, all pixels with the character "3" are to be determined, zero is set, and a character is to be set in the defect memory at the location of the corresponding pixel (for example "9"). To mark the defect, the combination of this character can be used by specifying the xy coordinates of the occurrence of this character in absolute coordinates of the mask or relative coordinates of the partial image by specifying the position of the partial image.

For the further procedure, the above-mentioned Threshold criterion used, with the value zero being set as the threshold value. The above-mentioned rules for placing the characters for the leading and trailing edges are also retained. The x-edge image is now screened in the y-direction using the modified single-threshold criterion. The y / x edge image is created. In the same way, the y-edge image is scanned in the direction x; the x / y edge image is created.

In the next step, the values of the corresponding pixels 14 of the x / y edge image are subtracted from those of the y / x edge image, which results in the real difference image.

The procedure described above for obtaining the real difference image is also applied to the formation of the ideal difference image. It does not matter whether the ideal image is available as an optical image or in CAD data. In the latter case, the ideal image must first be brought into the pixel shape before it can be transformed into an ideal difference image 4.

The preparation of the real difference image (starting point is the completely filled field memory with 4-bit image depth) and the ideal difference image is carried out with an arrangement to be described.

The defect and image difference extraction takes place in the context of the method according to the invention as follows:

1. The real difference image is searched completely for those pixels 14 which have a non-zero value. If such a pixel is determined, the corresponding pixel of the ideal difference image is checked to determine whether the value and the sign of its value correspond to the value of the pixel in the real difference image. Due to tolerance-related x-y offsets between the real and ideal image, which are also of the same size between the real and ideal difference image, the corresponding pixels are generally the same. not to be expected; So-called raster errors occur, even if one assumes non-defective picture elements.

Therefore, a sufficiently large environment of a corresponding pixel in the ideal difference image must be searched for the required value of the pixel from the real difference image. Depending on the permissible raster error, these can be the 8 or 24 immediately adjacent pixels of the corresponding pixel in the ideal difference image. It could also be a block from one more larger number of pixels are used in which the corresponding pixel is located. If the searched pixel is found in the given environment, it is a non-defective structure. If the pixel is not found, then there is a defect. In the defect memory, which is used to record all defects, a character, for example "5", appears at the same position that the non-zero pixel has in the real difference image.

2. If the value sought is found in the vicinity or at the position of the ideal difference image pixel, it is set to zero in the real difference image.

3. If all pixels of the real difference image have been processed in accordance with points 1 and 2 above, the pixels of the ideal difference image are examined to determine whether they are different from zero. If a pixel shows a value other than zero, a character is set at the corresponding location in the defect memory, e.g. "7".

With the method steps mentioned under 1. and the zeroing of all corners of the real difference image after the corner finding process, parasitic, too many picture elements and defects are determined. The method steps described under 3. lead to the detection of missing picture elements, the ideal difference image being used without taking into account the regular corners of the real difference image to carry out this defect detection step.

While the method for checking the content of images was explained in detail with reference to FIGS. 1-4, the arrangement required for this is described with reference to FIGS. 5-7.

In FIG. 5, 15 means a real mask (real image) or a partial image of this mask. A CCD line 16, which functions as an AD converter, is used to scan the mask. The signals generated in the CCD line 16 when the mask 15 is scanned are fed to a circuit block 17 which is connected to a control and evaluation computer 18. Analogous to the real mask row, there is the ideal mask row, which begins with the ideal mask 19 and is connected to the control and evaluation computer 18 via a CCD line 20, a switch 21 and a circuit block 22. Finally, a CAD data store 23 can be coupled into the ideal mask row via a CAD data converter 24 and the switch 21. The switch 21 can be flipped so that it either allows the data flow from the ideal mask row or the CAD data flow to the control and evaluation computer 18, which evaluates and controls the entire control process.

6 shows the basic structure of a circuit block 17 or 22. A column selection circuit 25 is connected on the one hand to the CCD line 16 or 20 or to the CAD data conversion 24 and on the other hand to columns 26, 27, 28, 29. In addition to means for selecting the correct column, the column selection circuit 25 has a threshold value circuit and a counter for sequence control. Each of the processing columns 26 to 29 successively has an input 30, mutually parallel memories for x and y, which are denoted by 31 and 32, for the edge image x and the edge image y, which are denoted by 33 and 34, and the edge image x / y and the edge image y / x, which are designated by 35 and 36. In the further course of each processing column, an image subtraction stage 37 for forming the real or ideal difference image and an initial Memory 38 provided.

Each of the processing columns 26 to 29 is connected to a DMA (Direct Memory Access) interface 39 via the output memory 38. In addition, there is a direct connection 40 between the column selection circuit 25 and the DMA interface 39 for the control signals which cause the DMA interface 39 to empty the respective 16 * 16-bit memory 38.

FIG. 7 shows the individual elements of one of the processing columns 26 to 29 and their interconnections, which allow the various edge and difference images to be produced in a simple manner by advantageously interconnecting their individual elements and multiple use.

The input 30 is connected to the x memory 31 and the y memory 32 via switches 41 and 42, respectively. Each of the switches 41 and 42 has switch positions a, b, c and corresponds to a switch 43 downstream of the memory 31 or a switch 44 downstream of the memory 32, which have the corresponding switch positions b, c, d. In the switching position b, the memory 31 is connected to a comparator 45 and this is connected to an evaluation logic 46. The evaluation logic 46 has two outputs. One output leads to a switch 47 with switch positions b and c, which correspond to the aforementioned switch positions b and c. Switch position b of switch 47 is connected to switch position b of switch 41 via a line 49. Switch position c of switch 47 is connected to switch position c of switch 42 via a line 48. The second output of the evaluation logic 46 is one Switch 50 performed, which allows the connection 51 between the counter 52 of the column selection circuit 25 and a 16 * 16 bit memory 53 to close or open. In its switching position b, the switch 44 establishes a connection between the memory 32 and a comparator 54, which in turn is connected to an evaluation logic 55 which, like the evaluation logic 46, has two outputs. One output leads to a switch 56, which in turn has two switch positions b and c, which correspond to the switch positions b and c of the switch 47 already mentioned. The switch position b of the switch 56 is connected to the switch position b of the switch 42 via a line 58. Likewise, the switch position c of the switch 56 is connected to the switch position c of the switch 41 via a line 57. A line 59 leads from the switch position c of the switch 43 to the comparator 54. In an analogous manner, there is a connection 60 between the switch position c of the switch 44 and the comparator 45. From the switch position d of the switch 43, a line 61 leads to a component component 62, which is connected to the output memory 38 via an adder 63. There is also a line 64 between the switch position d of the switch 44 and the adder 63.

The second output of the evaluation logic 55 acts on a switch 65, which is located in the connection 51 between the counter 52 and a 16 * 16 bit memory 66.

A 20 MHz clock 67 is used to clock the counter 52 for the sequence control. There is a direct connection 40 between the counter 52 and the DMA interface 39. The output memory 38 and the 16 * 16 are also directly connected to the DMA interface 39 bit memory 53 and 66. The signals coming from the CCD line 16 or the CAD data converter 24 via the switch 21 (FIG. 5) are fed by the column selection circuit 25 to the respective free column, for example the column 26, via the input 30 (FIG. 6) . The threshold value circuit integrated in the column selection circuit 25 ensures that only edge transitions above a certain, practice-oriented intensity limit (a threshold value) are effective and are written into the memories 31, 32 for x and y via the switches 41, 42 in the switch positions a. Since in the exemplary embodiment a CCD line 16 of 1024 pixels each experiences 64 line shifts, 1024, 64 * 64 picture elements are written into each of the memories 41, 42 before a transition to the next memory or to the next processing column 27, 28 or 29 takes place. The transition is initiated by a central control unit 18 (FIG. 5), which generates the CCD line detection and shift, is itself influenced by this detection and shift and ends the old count after every 1024 * 64 pixels (picture elements) and that opening the new memory and initiating the new count. It acts on the AD converter 16 or 20 or on the CAD data conversion 24. With the transition, the counter 52 in the column selection circuit 25 is started, from the counter reading of which the sequence control, the addressing of the memories 31, 32 and possibly result in further activities. The values are read line by line from the memory 31 and column by column from the memory 32, buffered, fed to the comparators 45 and 54 in the switch position b via the switches 43, 44 and compared there with the corresponding previous values. The difference in the intensities between the nth and the (n-1) th pixel and thus the signal is formed. det, which shows whether it is an edge or not or what type of edge (leading or trailing edge) it is. This signal is temporarily stored in a flip-flop integrated in the evaluation logic 46 or 55 and subjected to an evaluation with the signal from the previous comparison. This evaluation ensures that if the same edge signal occurs several times, the corresponding edge information is only set in one memory location. It is also determined in the evaluation logic 46 or 55 whether the signals from the front and rear edges fall in the same pixel (on the same sensor). If this occurs, it is a defect that affects only one sensor, in which a zero (no edge) is written into the relevant memory location and the associated status of the counter 52 of the sequence control with the aid of the connection of the evaluation logic 46 or 55 with the 16 * 16-bit memory 53 or 66 by briefly opening the switch 50 or 65 (FIG. 7) in this 16 * 16-bit memory 53 or 56. The 16 * 16-bit memory 53 or 66 is emptied by the DMA interface 39 and subjected to the defect extraction. After the 1024 * 64 pixels (sensors, memory manufacturers) have been processed in rows and columns, lines 49 and 58 and switch positions b of switches 47, 41 and 56, 42 form the x-edge image in memory 31 and in memory 32 the y-edge image.

Thereafter, switches 43 and 44 are switched to switch position c, so that comparator 54 is connected to memory 31 via line 59 and comparator 45 is connected to memory 32 via line 60. The x-edge image contained in the memory 31 becomes columns by column and the one written in the memory 32 The y-edge image is read out line by line, fed to the comparator 45 or 54 and the evaluation logic 46 or 55. The result is the x / y edge image, which is stored in the memory 31 via the line 57 and the position c of the switches 56 and 41, and the y / x edge image which is stored on the line 48 and the position c of the switches 47 and 42 is stored in the memory 32.

Finally, the image subtraction is carried out by forming differences. For this purpose, the x / y and the y / x edge image are read out sequentially from the respective memory 31 or 32, the switches 43, 44 being in the switch position d. The picture elements of the x / y edge image pass through the line 61 one after the other to the two's complement 62, where each signal is negated with a subsequent addition with a one in the last position. The picture elements of the y / x edge picture are led via line 64 to the 4-bit full adder 63, in which the two's complement of the x / y edge picture is subtracted from the y / x edge picture and transferred into the output memory 38. When the subtraction has been completed for the entire field, the DMA interface 39 is activated by the computer 52 of the column selection circuit 25, which empties the output memory 38 and the 16 * 16-bit buffer memories 53 and 66 and the memory contents in the control and evaluation computer 18 (Fig. 5) transfers integrated memory. After the counter 52 has been reset, the evaluation column 26 is thus again available for recording pixel values. The control and evaluation computer 18 serves on the one hand for the coordinated interaction of all parts of the control process with regard to the content of the images or partial images and on the other hand for displaying the coordinates of the defect locations (pixels) in the images or partial images. After that it is possible Lich, individually inspect the defects in a known manner and decide on the need to correct the respective defect or to reject an entire image or mask.

The process described for FIGS. 5 to 7 applies both to the formation of real difference images 2 and ideal difference images 4. On the basis of the real difference image 2 (FIG. 1), all parasitic, surplus and defective structures are determined after its production by setting the basic values to zero in a first defect detection step. In a second defect detection step, missing structures are determined on the basis of the ideal difference image, in that the ideal difference image is processed independently without reference to the regular corners of the real difference image. In this way, the real comparison image 5 and the defect image 6 (FIG. 1) are created in the control and evaluation computer 18 (FIG. 5).

Claims

1. Method for checking the content of images by comparing a real image with an ideal image, both of which relate to the same image content, the images to be compared being broken down into elements arranged according to rows and columns, analog elements of the real image and the ideal image in x and y coordinates are scanned, compared with one another and the comparison result is further processed, characterized in that an x-edge image and a y-edge image are generated from the real image and from the ideal image, that each x-edge image in the y-direction and each y - Edge image scanned in the x direction and an x / y and a y / x edge image are generated therefrom that by subtracting the element values of the y / x edge image from the corresponding element values of the x / y edge image of the real image or of the ideal image, a real difference image or an ideal difference image is generated that by comparing the real difference image with the ideal difference image, a real comparison image It is determined that the ideal difference image is scanned for itself and that a defect image is derived from the result of the scanning of the ideal difference image and the real comparison image.

2. The method according to claim 1, characterized in that the ideal image is in non-optical form.

3. The method according to claim 2, characterized in that. that in order to find the picture element corresponding to the picture element in the real difference picture in the ideal difference picture, a plurality of picture elements lying on all sides in a block are scanned.

4. Arrangement for performing the method according to at least one of claims 1 to 3, in which a circuit block is arranged between the data of the real image and the ideal image supplying units and an evaluation unit, characterized in that the circuit block successively a column selection circuit, processing columns connected in parallel and comprises an interface, of which the column selection circuit includes a thresholding device and a counter for the sequence control, each processing column a memory for the x-edge image and the y-edge image as well as the x / y-edge image and the y / x-edge image and a subtraction device and contains an output memory, and the interface is connected on the one hand via the processing columns and on the other hand via a direct line to the column selection circuit.

5. Arrangement according to claim 4, characterized in that each processing column has two parallel signal paths, each with a memory arranged between a first and a second switch, a comparator and an evaluation logic with two outputs, which is arranged after a third switch that in each signal path with the help of different switch positions of the switches, there is a connection from the evaluation logic to the memory, from the memory of one signal path to the comparator of the other signal path and after passing through the other signal path from the first output of the evaluation logic in the other signal carriage to the memory in one signal path, that from the second switch of each signal path there is a connection to a subtraction element which is connected to a Output memory is connected, that between the computer of the column selection circuit and the interface two mutually parallel catch memories are provided, each of which is preceded by a fourth switch, which is briefly switched by a signal emanating from the other output of the evaluation logic of the associated signal path.