Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
  • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
  • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
  • G06F1/06—Clock generators producing several clock signals
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C8/00—Arrangements for selecting an address in a digital store
  • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
  • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
  • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
  • H03K5/15026—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages
  • H03K5/1504—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with asynchronously driven series connected output stages using a chain of active delay devices

Definitions

• the present invention relates to a semiconductor integrated circuit that outputs predetermined information stored in a storage means via a plurality of latch circuits. In order to drive each of the latch circuits, a predetermined clock is used.
• the present invention relates to a clock buffer for generating a plurality of clock signals having a predetermined time difference based on a clock signal, that is, a semiconductor integrated circuit having clock signal generating means.
• each circuit formed in the semiconductor integrated circuit except for the memory cell and its peripheral circuit is Some are controlled in synchronization with a predetermined clock signal.
• a plurality of different clock signals are used simultaneously or through a predetermined delay time. It is preferable that a predetermined and certain delay time is provided for the user.
• the background in which an accurate delay is required between each clock pulse signal will be described with reference to the conventional semiconductor memory device shown in FIG. 1 as an example.
• the address buffer 1 reads the address selection signal AD from the address buffer 1.
• An address signal is output to the decoder 2 and the input / output sense amplifier and the column decoder 3. Based on the address signal (ADD '), the input signal is output from the mouth decoder 2, the input / output sense amplifier, and the column decoder 3.
• the memory cell of the address in the cell area 4 is selected based on the address.
• the input data Din input to the input buffer 5 is input to the input control circuit 6, and the input control circuit 6 supplies the chip select noise to the input control circuit 6.
• the input control circuit 6 supplies the chip select noise to the input control circuit 6.
• the data When data is read from a predetermined memory cell in the cell area 4, the data constitutes a data transfer circuit from the memory cell selected as described above via the input / output sense amplifier and the column decoder 3.
• the latches are sequentially latched by the first and second latch circuits 9 and 10, and output from the first latch circuit 9 as output data D 0 ut from the output circuit 31.
• a reference clock signal CLK is input from an external circuit to a clock buffer that outputs a clock pulse signal that defines the operation timing of each of the circuits, that is, the clock generation means 11.
• the first clock signal C'L K1 and the second clock signal CLK2 delayed by a certain time from the first clock signal are output.
• the first The latch circuit 9 operates based on the first clock signal CLK1
• the second latch circuit 10 operates based on the second clock signal CLK2, and performs a read operation.
• the first and second latch circuits 9, 10 sequentially operate and output based on the second clock signal CLK2 output following the first clock signal CL ⁇ 1. Data D 0 ut is sequentially output.
• the address buffer 1, the input buffer 5, the chip select buffer 7, the write control buffer 8, and the first latch circuit 9 operate based on the first clock signal CLK1
• the second latch circuit 10 operates based on the second clock signal CLK2.
• the address buffer 1, the input buffer 5, the chip select buffer 7, the write control buffer 8, and the first latch are based on the first clock signal CLK1.
• the clock buffer 11 is configured to operate, for example, as shown in FIG. 2, and the reference clock signal CLK is supplied to the first and second delay circuits 12 and 13.
• the clock signals CLK 1 and CLK 2 are output from the first and second pulse generation circuits 14 and 15, respectively, based on the output signals of the delay circuits 12 and 13, respectively. Then, by setting the delay time of the first delay circuit 12 to be longer than the delay time of the second delay circuit 13, the second clock signal CLK 1 is output and then the second delay signal is output.
• FIG. 1 shows an example in which a completely synchronous STRAM is used. The principle of reading is shown in FIG.
• FIG. 3 shows the waveforms of the clock signal, the external input, and the information output of the RR type fully synchronous STRAM.
• the clock signal is When the signal rises up to the level of, the address N, which is an external input, and the information N of the data input Din are fetched, and the fetched N is output in response to the time T3 when the next clock signal rises. . That is, at the time of the rising edge of each clock signal, the information acquired by the immediately preceding clock signal is output.
• each circuit is controlled by a plurality of clock signals having a predetermined time difference, so that these clock signals are based on a reference clock signal.
• Multiple clock signals are formed by the clock buffer. Therefore, it is necessary to form a clock buffer that generates a plurality of clock signals each having a predetermined time difference based on the reference clock signal.
• the first latch circuit takes in the information of the second latch circuit by the first first clock signal, and outputs the information to the output circuit at the same time.
• the second clock signal New information is read from the memory and taken into the second latch circuit.
• the information is taken into the first latch circuit, and the information is outputted to the output circuit.
• the synchronous semiconductor memory device using the two-stage latch circuit captures data (information) only at one point at the rising edge of the clock signal. This has the advantage that the cycle of the ⁇ clock signal can be shortened, and the time from the input of the clock signal to the output of the data can be shortened.
• the input data is latched in the internal latch circuit, there is an advantage that even if there is some skew in the input data, the specified data can be taken in without error. .
• the first clock signal and the second clock signal have a predetermined delay time between them. If the signals overlap, if the second latch circuit in FIG. 1 is still at 0 ° while the second latch circuit is at 0 °, the second The information newly acquired by the latch circuit passes through the first latch circuit as it is and is output to the output circuit. As a result, incorrect information is output and causes a malfunction.
• the clock buffer 11 has a large number of delay circuits 12 and 13 due to variations in the manufacturing process. May change, and the difference between the delay times of the two delay circuits 12 and 13 may become small.In such a case, the first and second latch circuits 9 and 10 malfunction. Sometimes.
• An object of the present invention is to provide a clock buffer capable of stably outputting a plurality of clock signals having a predetermined time difference from a reference clock signal.
• the present invention basically provides a semiconductor integrated circuit having a technical configuration as described below.
• the first and second pulse signal generation circuits that receive a rising edge or a falling edge of an input signal, start outputting a pulse signal and output a pulse signal having a predetermined pulse width, and Pulse generation of the second pulse signal]
• the U path receives the end of the first pulse signal output from the first pulse signal generation circuit in response to the input signal, and outputs the second pulse signal.
• a semiconductor integrated circuit to start, and more specifically, reads and reads a plurality of pieces of information stored in a predetermined storage means in synchronization with a predetermined clock bus transmitted from the clock generation means. After sequentially transmitting the outputted information to each latch circuit of the latch means composed of a plurality of latch circuits arranged in series while synchronizing with the predetermined clock pulse, the information is transmitted.
• the clock generation means is configured to output the clock signal based on an input reference clock signal (CLK).
• CLK 1 for outputting a first clock signal (CLK 1), and a second clock signal (CLK 2) in response to the first clock signal (CLK 1).
• CLK 2 a second pulse generating circuit that outputs the same.
• a feature of the semiconductor integrated circuit according to the present invention is that when the first pulse changes at a predetermined time, a second pulse having a predetermined pulse width is generated in response to the change in the first pulse. Things.
• FIG. 1 is a diagram showing an example of a conventional semiconductor integrated circuit which includes semiconductor storage means.
• FIG. 2 is a diagram showing an example of a clock generation means conventionally used in a semiconductor integrated circuit.
• FIG. 3 is a diagram for explaining the operation of STRAM memory used for conventional semiconductor storage means.
• FIG. 4 is a diagram for explaining the principle of the clock generation means according to the present invention.
• FIG. 5 is a diagram showing a specific example of the clock generation means according to the present invention.
• FIG. 6 is a diagram for explaining the operation of the clock generation means according to the present invention shown in FIG.
• FIG. 7 shows a semiconductor including a clock generating means according to the present invention.
• FIG. 3 is a diagram illustrating an example of an integrated circuit.
• FIG. 8 is a diagram for explaining the operation of the semiconductor integrated circuit of FIG.
• FIG. 9 is a diagram showing a circuit configuration example of a sense amplifier connected to the storage means of the semiconductor integrated circuit according to the present invention.
• FIG. 10 is a diagram showing a circuit configuration example of a level conversion circuit connected to a sense amplifier of a semiconductor integrated circuit according to the present invention.
• FIG. 11 is a diagram showing another example of the circuit configuration of the level conversion circuit connected to the sense amplifier of the semiconductor integrated circuit according to the present invention.
• FIG. 12 is a diagram showing another configuration example of the first and second latch circuits used in the semiconductor integrated circuit according to the present invention.
• a first pulse generation circuit 19 that outputs a first clock signal CLK 1 based on the input reference clock signal CLK, and the first clock signal CLK 1
• a clock buffer is configured by the second pulse generation circuit 20 that outputs the second clock signal CLK2.
• the second pulse generation circuit 20 detects the end of the first clock signal CLK1 and outputs the second clock signal CLK2, so that the first pulse signal is output. There is always a predetermined time difference between the clock signal CLK1 and the second clock signal CLK2. Secured.
• the reference input signal CLK is input to one input terminal of the NAND circuit 18a via the two-stage inverters 17a and 17b. From ⁇ b, the signal is input to the other input terminal of the NAND circuit 18a via three-stage inverters 17c, 17d, and 17e. Then, the first clock signal CLK1 is output from the output terminal of the -NAND circuit 18a via the inverter 1 ⁇ f. Therefore, the inverter 1 ⁇ a to l 7 f and the NAND circuit 18 a constitute a first pulse generation circuit 19.
• the output signal of the inverter 17 f is input to one input terminal of the NAND circuits 18 b and 18 c via the inverter 1 ⁇ g, and the output signal of the inverter 17 g is output to the inverter 17 h. , 17i to the other input terminal of the NAND circuit 18c.
• the output signal of the N A N D circuit 18 c is the inverter 17 j, 1
• the second pulse generating circuit 20 is constituted by 8c.
• the in-phase output signal SG1 is input from the inverter 17b to one input terminal of the NAND circuit 18a with a time difference, and the output signal SG1 is input to the other input terminal of the NAND circuit 18a.
• the output signal SG 2 of the opposite phase is output from the inverter 17 e later than 1.
• the NAND circuit 18a outputs the output signal SG3 which becomes L level only when both the output signals SG1 and SG2 become H level, and the output signal obtained by inverting the output signal SG3 is inverted. It is output as the first clock signal CLK 1 from 17 f.
• an output signal SG 4 obtained by inverting the first clock signal CLK 1 by the inverter 1 g is output to one input terminal of the NAND circuits 18 b and 18 c, and the NAND circuit 1
• An output signal SG5 having the same phase as the output signal SG4 and having a time difference is output to the other input terminal of 8c via the inverters 17h and 17i.
• the NAND circuit 18c outputs an output signal SG6 which becomes H level when one of the output signals SG4 and SG5 is at L level, and the output signal is the inverters 17j, 17
• the output signal SGT is output to the other input terminal of the NAND circuit 18b via k.
• the NAND circuit 18b outputs an output signal SG8 which becomes L level when both of the output signals SG4 and 307 become 11 level, that is, this output signal SG8 is the rising edge of the first clock signal CLK1. Falling based on falling.
• the output signal SG 8 is inverted by the inverter 17 m and output as the second clock signal CLK 2.
• the clock clock 16 outputs the first clock signal CLK1 based on the reference clock signal CLK and outputs the first clock signal CLK1.
• the second clock signal CLK2 is output based on the fall. Therefore, a fixed time difference can always be secured between the first clock signal CLK1 and the second clock signal CLK2, so that the clock buffer 16 is connected to the semiconductor memory device. In this case, the malfunction of the first and second latch circuits 9 and 10 can be reliably prevented.
• the pulse generation circuit of the present invention As described above, after the first clock signal is generated, the signal becomes 0FF, that is, the first clock signal disappears.
• the second clock signal is generated after confirming the fact, there are various methods for confirming the disappearance of the first clock signal.
• the transition state of the first clock signal (CLK 1) generated by the first pulse generation circuit reaches a predetermined level, the second clock signal responds to the state.
• Clock signal (CLK 2) may be output, or the first clock signal (CLK 1) generated by the first pulse generation circuit may fall. It may be configured to detect and output the second clock signal (CLK 2).
• the second clock signal is generated after the first clock signal has fallen without fail, and therefore the second clock signal is generated. Clock signal is incorrect There is no danger of being generated during the generation of the clock signal.
• the first clock signal captures predetermined information from the second latch circuit, latches the information, and outputs the information to the output circuit.
• the width of the first clock signal may be relatively short because only the switching circuit needs to operate. Further, in the present invention, it is preferable to provide a write pulse generating circuit for operating the latch circuit.
• the second clock signal has a function of reading out predetermined information from the memory of the storage means, but the information handled in the memory is analog-like, Takes a predetermined time.
• the signal width of the second clock signal is preferably set to be longer than the signal width of the first clock signal so that the information can be reliably read from the memory. .
• the second pulse generator circuit generates the second clock signal (CLK1) having a signal width longer than the signal width of the first clock signal (CLK1). 2) is preferably output.
• the latch means includes at least two latch circuits arranged in series.
• the latch circuit is arranged close to the output means, and the second latch circuit is arranged close to the storage means.
• the first latch circuit includes the first latch circuit.
• the second latch circuit is controlled by the second clock signal (CLK2).
• the second latch circuit is controlled by the second clock signal (CLK2).
• the storage means used in the semiconductor integrated circuit according to the present invention is composed of, for example, a row 'decoder, a column' decoder, a memory 'cell, and a sense amplifier Z-write,' buffer '.
• the row decoder and the column decoder are controlled by an address buffer controlled by the first clock signal (CLK1), and the sense amplifier / decoder is controlled by an address buffer.
• the write buffer is configured to be controlled by the input buffer and controlled by a write pulse generator circuit that generates a write pulse in response to a write buffer and a chip select buffer.
• the output of the sense amplifier buffer is connected to the latch means via a level conversion means.
• FIG. 7 shows a specific example of the semiconductor integrated circuit according to the present invention in correspondence with the conventional example of FIG.
• a plurality of pieces of information stored in the predetermined storage means 4 are read out in synchronization with a predetermined clock pulse transmitted from the clock generation means 11 and read out.
• the information is sequentially transferred to each latch circuit of the latch means 30 composed of a plurality of latch circuits 9 and 10 arranged in series while synchronizing with the predetermined clock pulse.
• the information is output to another arithmetic processing circuit via a predetermined output means 31.
• the clock generating means 11 generates a first pulse signal for outputting a first clock signal (CLK 1) based on the input reference clock signal (CLK).
• a semiconductor including a circuit and a second pulse generating circuit for outputting a second clock signal in response to the first clock signal; An integrated circuit is shown.
• FIG. 7 differs from FIG. 1 in that a column decoder 3 'and a sense amplifier / write buffer 3 "are provided separately, and a write pulse generation circuit 6 is provided instead of the input control circuit 6. Is provided.
• a level conversion circuit 32 is provided after the sense amplifier, and further, the write control buffer (WE) 8 is connected to a chip selector and a buffer (CS) 7 by an AND circuit.
• a gate circuit 33 and an output control circuit 34 disposed between the AND gate circuit 33 and the output circuit 31 are provided.
• the AND gate circuit 33 is a logic gate for controlling the circuit 34 and takes the logic of CS and WE. When CS is "H” or WE is “L”, the output control circuit is activated so that the output becomes high impedance.
• the circuit 34 is a general circuit which is also used in a normal memory and performs an operation to set the output transistor Tr to 0 FF.
• FIG. 9 shows an example of a circuit that can be used as a sense amplifier according to the present invention.
• the configuration of the sense amplifier shown in FIG. The information output from the memory cell is input to in A and in B in the figure, is subjected to predetermined amplification, and is output from A and B in the figure to a subsequent level conversion circuit.
• FIG. 10 shows an example of a level conversion circuit that can be used in the present invention, and is composed of a circuit A, a circuit B, and a circuit C in the figure.
• Each of the circuits A, B, and C is a circuit known as a person used in the level conversion circuit.
• the information output from the outputs A and B of the sense amplifier is input to the inputs A and B of the circuit shown in FIG. 10 (A) and output from the outputs LVA and LVB.
• the output LVA is input to the input LVA and LVB of the picture shown in FIG. 10 (B-1) and FIG. 10 (B-2), respectively, and the circuit of FIG. 10 (B-1) is used.
• the LOA output is obtained from the output of the circuit, and the L0B output is obtained from the output of the circuit shown in Fig. 10 (B-2).
• the outputs LOA and LOB are input to the fixed inputs LOA and LOB shown in FIG. 10 (C), respectively, and the signals LCOA and LCOB are obtained from the output—LCOA and LCOB of the circuit.
• a level conversion circuit as shown in FIG. 11 can be used.
• FIG. 12 shows the latch means used in the present invention. Another configuration is shown.
• Each of the latch circuits of the latch means includes an M 0 SFET transistor 91, 101 which receives a clock signal and performs a switching operation. And four MOSFET transistors 92 to 95 and 102 to 105 arranged as shown in the figure.
• two such latch means are arranged in parallel, and one output signal LCOA output from the level conversion circuit is input to one input image path of the latch circuit means, Also, the other output signal LC 0 B output from the level conversion circuit is input to the other input circuit of the latch circuit means.
• Waveforms c and d are formed with a delay time of
• waveform of the data output from the memory cell by the above address data is shown in waveform diagram e, and the data is output from the sense amplifier and the level conversion circuit.
• Waveform diagrams are shown in f and g, respectively.
• the first latch circuit 9 and the second latch circuit of the latch means according to the present invention shown at the lower end of FIG.
• the first clock signal CLK1 and the second clock signal CLK2 are applied to 10 respectively, and the output data N—1, N, N + 1, + 2 ⁇ 'The force that latches and outputs to the output circuit'.
• the first latch circuit 9 is activated ((R-1) of waveform j), and the second latch circuit 10 outputs data (N-- 1) is output to the output D out via the first latch circuit 9 and the data is latched in the first latch circuit 9 (2 of the waveform k).
• the first clock signal CLK becomes zero.
• the latch circuit 9 When the latch circuit 9 is closed, the second latch circuit 10 operates as shown in R-2 of the waveform h, and the second latch circuit 10 and the waveform i As shown in (3), the output data N output from the level conversion circuit is taken in and latched to that state.
• the first clock signal CLK1 becomes 0N again.
• the first latch circuit 9 operates and the data N taken in the second latch circuit 10 is output to the output D out via the first latch circuit 9.
• the data is output and the data is latched in the first latch circuit 9 (4 of the waveform k).
• the first clock signal CLK falls.
• the second clock signal CL is turned on at time t6 after detecting that the first latch circuit 9 is closed, the first latch circuit 9 is switched to R-4 of the waveform h in the closed state.
• the second latch circuit 10 is operated, and the second latch circuit 10 outputs the output data output from the level conversion circuit as shown by 5 in the waveform i. N + 1 is taken in and latched to that state.
• predetermined information can be read from memory and output.
• the present invention has an excellent effect that it is possible to provide a clock buffer capable of stably outputting a plurality of clock signals having a predetermined time difference from a reference clock signal. Can be demonstrated.
• the semiconductor integrated circuit of the present invention is applicable not only to a completely synchronous memory but also to an asynchronous memory.

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• Physics & Mathematics (AREA)
• Nonlinear Science (AREA)
• Engineering & Computer Science (AREA)
• Theoretical Computer Science (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Dram (AREA)
• Static Random-Access Memory (AREA)

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Citations (7)

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• 1991
  • 1991-09-04 WO PCT/JP1991/001181 patent/WO1992004774A1/ja not_active Ceased
  • 1991-09-04 EP EP91915599A patent/EP0498895A1/en not_active Withdrawn
  • 1991-09-04 KR KR1019920701065A patent/KR920702574A/ko not_active Ceased

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