Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/01—Modifications for accelerating switching
  • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
  • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
  • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
  • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
  • H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
  • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
  • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
  • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
  • H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
  • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
  • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
  • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
  • H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
  • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
  • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
  • H03K3/03—Astable circuits
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
  • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
  • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
  • H03K3/356—Bistable circuits
  • H03K3/356104—Bistable circuits using complementary field-effect transistors
  • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
  • H03K3/356147—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit using pass gates
  • H03K3/356156—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit using pass gates with synchronous operation
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
  • H10D84/401—Combinations of FETs or IGBTs with BJTs
  • H10D84/403—Combinations of FETs or IGBTs with BJTs and with one or more of diodes, resistors or capacitors
  • H10D84/406—Combinations of FETs or IGBTs with vertical BJTs and with one or more of diodes, resistors or capacitors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/90—Masterslice integrated circuits
  • H10D84/998—Input and output buffer/driver structures

Definitions

• This invention relates to logic and memory circuits and more particularly to logic and memory circuits which are designed to be integrated into high density integrated circuit chips and to operate at high speed.
• bipolar transistors or field effect transistors FET
• FET field effect transistors
• logic families such as emitter coupled logic (ECL) and transistor- transistor logic (TTL) have been designed.
• ECL emitter coupled logic
• TTL transistor- transistor logic
• the basic drawback of bipolar transistor technology is the high power consumed by the circuits and the speed limitation of these circuits.
• the art has also explored the use of FET based technologies. Most popular is the
• CMOS complementary metal oxide semiconductor
• CMOS technology has great appeal because of the lack of DC power dissipation.
• logic and memory circuits only dissipate power when they are switching from one logic state to another but not when they are idling at a given logic state.
• CMOS circuits are also easy to manufacture using well developed silicon based technology.
• the basic drawback of CMOS is its operating speed. Accordingly, the art has thoroughly investigated techniques for increasing the speed of CMOS circuits while still providing the basic advantages of CMOS. See for example U.S. Patent 4,541,076 to Bowers et al.
• Buffers have been used in logic and memory circuits in an attempt to enhance the operation thereof. See for example U.S. Patent 4,802,132 to Ohsawa which discloses the use of buffers in a memory cell.
• U.S. Patent 4,680,491 to Yokouchi et al. discloses a CMOS circuit having an output buffer for bidirectional input/output signals.
• U.S. Patent 4,802,127 to Akaogi et al. discloses the use of plural inverters as an output buffer to reduce transient current multiplication by those output stages which would otherwise cause a significant rise in the potential level of the power source line in a semiconductor memory device.
• the art has also investigated the use of inverters in logic and memory circuits to accomplish various purposes. See for example U.S. Patent
• Schmitt triggers and memory addressing See also U.S. Patent 4,185,209 to Street which discloses the use of inverters to convert negative logic
• CMOS circuits are limited to speeds of about 70 mHz.
• the art has also investigated exotic materials other than silicon, such as compound semiconductors like gallium arsenide and indium phosphide.
• these exotic materials often require discarding or reworking the large investment in silicon based processing equipment and
• the Ring Segment Buffer is used to couple logic gates to one another on an integrated circuit chip and to couple a memory cell to other circuits to provide shift registers, triggers, clock pulse generators, and other circuits which are necessary to implement a microprocessor.
• the Ring Segment Buffer of the present invention will first be described. Then, the logic circuit family and memory circuit family of the present invention using the Ring Segment Buffer will be described.
• Segment Buffer comprises one or more serially connected, complementary field effect transistor (FET) inverter stages.
• Each of the complementary FET inverter stages includes a serially connected N- channel FET and P-channel FET.
• Each stage has an input and an output, with the output of an
• the immediately preceding stage is connected to the input of an immediately succeeding stage.
• the output of the last inverter stage is connected to a capacitive load which is to be driven by the Ring Segment Buffer.
• the capacitive load may include other logic gates, other memory circuits,
• interconnection wiring both on and off chip
• combinations of these and other loads are possible.
• the N-channel N-channel
• FET and P-channel FET in each inverter stage have channel widths which are less than a predetermined factor times the width of the corresponding
• the Ring Segment Buffer can drive the capacitive load at very high speeds, such as 300mHz or more.
• the factor referred to as "K" is defined by:
• I* sat is the channel saturation current of a square channel FET having width and length of L 0 and gate voltage at V dd ;
• T rise is the desired rise time of the Ring Segment Buffer;
• ⁇ is the ratio of electron mobility in the N-channel to electron mobility in the P-channel;
• C 8 * is the effective gate capacity per unit area of the
• L 0 is the channel length for the complementary field effect transistors in the Ring Segment Buffer stages; V dd is the power supply voltage applied to the Ring Segment Buffer; L c is the interconnecting conductor length between inverter stages; and ⁇ 0 is equal to Cg* (1+ ⁇ ) /C i ⁇ , where C i is equal to field oxide insulator capacity per unit area; and ⁇ is equal to the ratio of the width of the interconnecting conductor at the output of the inverter and the width of the first N-channel in the Ring Segment Buffer.
• the Ring Segment Buffer may be used to couple a logic or memory circuit to an arbitrary size capacitive load without degrading the inherent response time of the logic or memory circuit.
• the channel widths in the last Ring Segment Buffer stage are determined by the size of the load to be driven.
• the channel widths of the first stage are determined by the N-channel width of the logic or memory cell.
• the N-channel width of the first stage must be less than K times the N-channel width of the logic or memory cell, with the P-channel width being ⁇ times the N-channel width.
• the number of stages in the Ring Segment Buffer is determined by the number of stages required to allow the transistors of each stage to have a width which is less than K times the channel width of the previous stage. Accordingly, the larger the capacitive load, the more stages in the Ring Segment Buffer which will be necessary, each stage observing the
• the Ring Segment Buffer may be used to provide a predetermined delay, in addition to driving an arbitrarily large capacitive load.
• the Ring Segment Buffer may provide the desired delay by varying the channel lengths of the P-channel and N-channel devices in the Ring Segment Buffer to define a desired rise time which controls delay.
• a desired delay may be obtained by using the following equation:
• T d 0. 65nT rlse
• n the number of stages in the Ring Segment Buffer and T rise in the rise time selected for the inverters comprising the Ring Segment Buffer.
• the length L 0 of the P-channel and N-channel FETs in the Ring Segment Buffer may be chosen to satisfy a desired rise time as according to the following equation:
• a predetermined delay and speed may be obtained.
• the FETs in the last stage of the Ring Segment Buffer become very wide.
• the last stage FETs may be replaced with an integrated bipolar-FET circuit.
• the minority carrier lifetime within the silicon base region of the bipolar transistors must be lowered from typical values of 5e-7 seconds to 8e-9 seconds or less.
• the critical step of lowering carrier lifetime may be accomplished by doping the base region of the bipolar transistors with gold.
• the gold doping introduces paired donor and acceptor recombination centers within the base region with energy states within the middle of the bandgap.
• the Lifetime Controlled integrated bipolar and FET device may be used as a last stage of a Ring Segment Buffer.
• Segment Buffer at the output of each logic gate in an integrated circuit logic chip, to couple each logic gate to its capacitive load and provide
• Buffer Cell Logic The load may be other logic gates and gate interconnections, either on chip or off chip.
• the Ring Segment Buffer is designed as described above. Accordingly, a Buffer Cell Logic chip according to the present invention will include a Ring Segment Buffer between the output of each logic gate and its associated load, with each Ring Segment Buffer having the number of stages n which allows factor K to be observed, to thereby drive the effective capacitive load at the desired logic chip speed.
• the number of stages in the Ring Segment Buffer for each logic gate will vary depending upon the load for that gate. However, each Ring Segment Buffer will observe the relationship described above and will be designed for operation at the desired logic speed.
• CMOS logic gate typically includes serially connected FETs of a first
• a CMOS logic gate degenerates to a complementary inverter when m equals 1.
• An inverter has a
• the channel width of each of the serially connected FETs is made larger than the equivalent inverter channel width by the number m of FETs connected in series or in parallel.
• the channel widths of the serially connected FETs are m times wider than the appropriate P-channel or N-channel width of an equivalent inverter. This produces a symmetrical transfer function for the logic gate, and allows high speed operation of the gate itself.
• the CMOS logic gate may be coupled to other gates using a Ring Segment Buffer.
• CMOS logic circuits according to the invention will operate at speeds of 300 mHz using standard device processing dimensions and parameters, in which ordinary CMOS logic will operate at 70 mHz or less. Accordingly, a factor of 4 or more in speed may be attained without introducing exotic materials or dissipating DC power.
• high speed memory circuits are also required.
• a limiting factor in present day memory circuits is that they require two clock pulses for operation.
• a standard shift register circuit in which a number of memory stages are serially connected so that the contents of a previous stage can be shifted to a succeeding stage.
• two clock pulses are required; i.e. a first clock pulse to shift the data to a temporary stage and the second clock pulse for then shifting the data from the temporary stage into the next shift register. If a single clock pulse is used, the new data which is shifted into a shift register stage overwrites the old data before it can be shifted into the next stage.
• a Ring Segment Buffer may be coupled to the output of a memory cell to provide a predetermined delay and to drive the next stage at high speed regardless of its load capacitance, in a "Delay Storage" technology. Since the Ring Segment Buffer provides a
• a single clock pulse may be used, with the memory cell providing its own
• shift registers, triggers, clock pulse generators and other memory- based circuits necessary to form a high speed microprocessor may be provided using Delay Storage technology.
• a basic memory element may be provided according to the invention by coupling the output of a CMOS memory cell (comprising a well known pair of cross-coupled complementary FET inverters), to a Ring Segment Buffer.
• the Ring Segment Buffer is designed (1) to provide a desired delay, by controlling the channel length of the transistors therein, and (2) to drive the necessary capacitive load by controlling channel width to observe the factor K. Accordingly, the output of the Ring Segment Buffer provides the new shift register contents after a predetermined delay.
• the output of the Ring Segment Buffer may be coupled to a next memory cell to provide a shift register which uses only a single clock pulse.
• a clock generator or multivibrator circuit may also be provided using a Ring Segment Buffer at the output of a cross coupled memory cell by feeding the output of the Ring Segment Buffer back to the input of the memory cell.
• the delay in the Ring Segment Buffer will determine the ultimate clock (vibrator) frequency.
• Synchronous or asynchronous clock pulses may be provided.
• Buffer of the present invention may be coupled to CMOS memory cells to provide the memory circuits needed for high speed microprocessor operation, using a single clock pulse. At least a fourfold increase in operating speed may be attained without loss of functional density on the chip while using standard silicon FET fabrication processes.
• Performance at 300 mHz or more may be provided using silicon technology.
• Figure 1 graphically illustrates N-channel normalized drain current in an inverter as a
• Figure 2 graphically illustrates the capacitive discharge time factor as a function of drain voltage for an inverter.
• Figure 3 graphically illustrates normalized output voltage of an inverter as a function of time.
• Figure 4 graphically illustrates drain current of an inverter as a function of time during capacitive discharge.
• Figure 5 graphically illustrates an input signal having a finite rise time.
• Figure 6 graphically illustrates an inverter output as a function of time during
• Figure 7 illustrates a thirteen stage CMOS ring counter.
• Figure 8 graphically illustrates a
• Figure 9 illustrates a Ring Segment Buffer according to the present invention.
• Figure 10 illustrates a BICMOS buffer according to the present invention.
• Figure 11 illustrates a cross section of an integrated circuit P-channel BIFET driver
• Figure 12 illustrates a cross section of an integrated circuit N-channel BIFET driver
• Figure 13 illustrates a top view of an integrated circuit BICMOS buffer according to the present invention.
• Figure 14 graphically illustrates the fall time of the BICMOS buffer of Figure 10.
• Figure 15 graphically illustrates the drain-base current of the BICMOS buffer of Figure 10.
• Figure 16 graphically illustrates the emitter current of the BICMOS buffer of Figure 10.
• Figure 17 illustrates a Ring Segment
• Buffer having a BICMOS buffer as its last stage, according to the present invention.
• Figure 18 illustrates a CMOS logic gate having symmetrical transfer function according to the present invention.
• Figure 19 illustrates a Buffer Cell Logic chip according to the present invention.
• Figures 20-23 illustrate CMOS logic gates having BICMOS outputs according to the present invention.
• Figure 24 illustrates a Delay Ring Segment
• FIG. 25 illustrates a Delay Storage Technology circuit according to the present
• Figure 26a illustrates a delay trigger stage according to the present invention.
• Figure 26b illustrates a delay latch according to the present invention.
• Figure 27 illustrates a shift register according to the present invention.
• Figure 28 illustrates a four stage binary counter according to the present invention.
• FIG. 29 illustrates a clock
• FIGS 30-31 illustrate asynchronous clock pulse generators according to the present invention.
• a Ring Segment Buffer may be used in combination with logic gates and memory cells to provide a high speed logic and memory family.
• the design of the Ring Segment Buffer according to the present invention will first be described. Then, the use of the Ring Segment Buffer to produce a Buffer Cell Logic family will be described. Finally, the use of a Ring Segment
• the Ring Segment Buffer of the present invention may be used for driving a broad range of capacitive loads at high speeds.
• the Ring Segment Buffer comprises one or more serially connected complementary field effect transistor (FET) inverter stages, each of which comprises a serially connected N-channel and P- channel FET.
• FET complementary field effect transistor
• Each inverter has an input and an output, with the output of an immediately preceding inverter being connected to the output of an
• the Ring Segment Buffer may be designed to drive an arbitrarily sized capacitive load with a specific signal rise time, by making the channel width of each N-channel and P- channel field effect transistor in the Ring Segment Buffer less than a factor K times the width of the corresponding N-channel or P-channel transistor of the immediately preceding inverter stage.
• a factor K is determined which governs the maximum increase in channel width of the devices in succeeding stages of the Ring Segment Buffer.
• the channel of the P- channel FET is wider than the channel of the
• a Ring Segment Buffer having the requisite number of stages to drive the capacitive load, with the relationship between stages defined by the factor K, may thereby be provided.
• This Ring Segment Buffer may be used in integrated circuit logic and memory circuits as described below.
• a complementary FET inverter comprises an N-channel FET and a P-channel FET, the sources and drains of which are serially connected between two voltage potentials, typically a power supply voltage and ground, with the gates of the serially connected FETs being connected together to provide an inverter input, and the common connection point between the serially connected FETs being the output of the inverter.
• the gate voltage reaches the maximum value in accordance with a step function. Then the effects of input rise time are accounted for.
• the maximum drain current- voltage profile as a function of drain voltage is defined and then solved to obtain the time
• M is typically 200 and depends on saturation velocity, ionization field, and carrier mobility.
• V d drain voltage
• V p pinch-off voltage
• I d is the drain current
• Equations (4) and (5) are used to find an expression for drain voltage as a function of time, V d (t). This analysis requires use of log identities. The result is given below as Equation (6) for the discharge case. Equation (7) gives the expression for charging the load capacitance:
• drain discharge current as a function of time is:
• Equation (8) is plotted in Figure 4. Note that 50% of the saturation drain current flows at the discharge or charge time produced by an ideal step function drain current.
• symmetrically designed buffering inverter must be designed by increasing the P-channel and N-channel widths that will deliver a saturation current of 6.2ma when V d is close to the supply voltage V dd .
• 6.2ma current requires an N-channel FET device with channel width of about 20 ⁇ m and the width of a P-channel device of about 50 ⁇ m.
• channel length is assumed to be l ⁇ m.
• load capacitance greater than lpF channel dimensions are proportionately increased to achieve the same rise time. These large channel dimensions are required to drive large load capacitance, and consume chip real estate that might otherwise be used for logic functions.
• Equation (2) Equation (2)
• Equation (11) The solution to Equation (11) is:
• the output signal response due to a step function input signal is shown in Figure 3.
• V total charge voltage (Volts)
• Z in channel width of the N-channel device in the inverter.
• Equation (18) is a basic equation. To simplify design procedures, it is convenient to express load capacity C in terms of gate
• L o is the minimum channel length in cm.
• Z in and Z L can have any dimension. It is appropriate to define Z in and Z L in microns. Z L is the total sum of all effective gate widths being driven.
• the permissible reduction factor F R for the FET inverter stage channel width Z in is given by (21) below; i.e., Z in F R RZ L .
• Equation (21) depends directly on the square of the minimum channel length L o , directly with gate capacitance per square centimeter, C* 8 , and inversely with square channel saturation current
• Fermi Threshold Field Effect Transistor allows gate capacitance to be reduced compared to the MOSFET, so that shorter channels can be achieved while increasing the square channel saturation current. Fermi FET technology can lower the channel reduction factor F R at least one order of magnitude compared to MOSFET devices.
• Equation (21) will now be evaluated for conventional MOSFET devices and for Fermi FET devices.
• C* 8 1.5e-7 Farads/cm 2 ,
• V dd 5 Volts
• V dd 5 Volts
• a ring counter consists of an odd number (13 in Figure 7) of CMOS inverters.
• the inverters are interconnected such that the output of an inverter stage (i.e. the common connection point between the serially connected FETs) is connected to the input of the following inverter stage.
• the output of the final stage 13 is connected to the gate inputs of the first stage 1.
• the P-channel transistors have a channel width which is ⁇ times that of the N-channel transistor due to lower hole mobility.
• the hole mobility in the P-channel FET is ⁇ times lower than the hole mobility of the N-channel FET.
• the channel width of the P-channel devices is increased by ⁇ .
• the effective gate width of an inverter is (1+ ⁇ )Z n .
• V dd Power supply voltage
• Load capacity C on each inverter output stage consists of gate, diffusion, and interconnect capacity and is written as follows:
• W o and L o are interconnecting conductor width and total effective conductor length
• Z o and L o are the width and length of the N- channel transistors comprising the inverters forming the ring counter.
• Equation (30) is independent of the P- or N-channel width used in constructing the ring counter inverters. This fact comes about by the definition of conductor width, W o in Equation (24).
• the rise time of a typical Ring Segment Buffer may be calculated for the following
• the minimum inverter rise time for these circumstances is 0.21ns given no distributed load capacitance.
• the rise time of a ring counter inverter stage is primarily controlled by the length of the FET channel L o 2 . This can be seen by examining
• Each stage of the ring counter of Figure 7 consists of identical CMOS inverters each of which should have a symmetric voltage transfer function.
• the voltage transfer function for a CMOS inverter with symmetrical design is illustrated in Figure 8.
• the ordinate of Figure 8 is inverter output voltage at the common drain connection.
• the abscissa is gate voltage common to both gates of the P-channel and N-channel transistors forming the inverter.
• Figure 8 illustrates the fact that the input gate voltage must reach more than 50% of the drain supply voltage before the inverter can
• the process of sampling the ring counter toggle frequency may be used to illustrate the reasoning behind the need for the Ring Segment
• a fundamental problem is how to measure or sample the electrical signals occurring within the ring counter without disturbing its intrinsic toggle frequency (Equation (31)).
• Any sampling means attached to the output terminal of the ring counter introduces capacitive loading.
• the same conditions apply to sampling a logic cell or memory cell to extract its signal.
• the result of sampling the ring counter is an increase in rise time at the sample point resulting from the capacitive loading effects of the sampling means.
• This increase in rise or fall time at the sampling point proportionately increases delay in turning the next stage of the ring counter on or off. Accordingly, the ring counter toggle frequency is slowed down by twice the increase in rise time at the sample point.
• Z o and L o are the channel width and length of the N-channel transistor in the ring counter
• ⁇ is the factor that accounts for the larger gate area of the P- channel device forming the CMOS structure.
• the P- channel gate area is larger because hole mobility is less than electron mobility in the N-channel device.
• a suitable sampling means for the ring counter is a CMOS inverter.
• the Ring Segment Buffer samples fast logic signals with nominal loading effects of the intrinsic logic signal response time while maintaining flexibility in driving large capacitive loads.
• the Ring Segment Buffer is illustrated in Figure 9.
• Segment Buffer 20 of the present invention comprises a plurality of serially connected complementary FET inverter stages 21a...21n, each of which comprises a P-channel FET 22 and an N-channel FET 23 the sources and drains of which serially connected between a first electrical potential 28 (for example, power supply potential +V dd ) and a second electrical potential 29 (for example ground potential) .
• the input 24 of each inverter formed by connecting together the gates of the complementary FET inverter, is connected to the output 25 of the immediately preceding inverter, where the inverter output 25 is the connection point between the serially connected complementary FETs 22 and 23.
• the input 24 of the first stage is connected to the logic or memory cell 26, the output of which is to be driven by the Ring Segment Buffer 20.
• the output 25n of the last stage 2In of the Ring Segment Buffer is connected to the output connections 30 for the logic or memory cell 26.
• Segment Buffer 20 is placed between logic or memory cell 26 and its output connection 30.
• the load at output 30 is represented by an effective capacitance C 27.
• the Ring Segment Buffer 20 is designed to drive load capacitance 27 at the desired toggle frequency. This may be achieved according to the invention, by designing the channel width of each N-channel FET 23 to be a factor K or less, greater than the N-channel width of the immediately preceding N-channel FET.
• the logic or memory cell is constructed of N-channel FETs having channel width Z in .
• the N-channel FET 23a of the first buffer stage 21a also has width Z in .
• the second stage 23b has width KZ in
• the third stage has width K 2 Z in
• the final stage 21n has width K n Z in .
• the corresponding P-channel FETs 22a...22n have width ⁇ Z in , K ⁇ Z n and K n ⁇ Z n with ⁇ being the mobility difference factor. This guarantees that each stage has a symmetric voltage transfer function.
• the Ring Segment Buffer can drive an arbitrarily sized capacitive load C, with the desired high speed operation of the logic or memory cell circuit.
• the analysis begins by finding the
• the N-channel width of each inverter stage in the Ring Segment Buffer will be a factor K greater than the previous stage. All channel lengths can be the minimum value L o .
• the required output signal rise time, T riae , the channel width Z o in the logic cell and the Ring Segment Buffer polarity determine the value of K and the number of stages n required by the buffer cell.
• I* sat is the square channel saturation current
• T rise is the desired rise time
• ⁇ is the hole mobility difference
• L o is the channel length
• V dd is the power supply voltage
• L o is interstage conductor length
• ⁇ o is the effective interconnect
• V dd 5 Volts
• the width Z o of the N-channel transistor in the logic cell or memory cell in order to drive the N stage Ring Segment Buffer may be calculated using Equations (33) and (34) :
• V dd 5 Volts
• a 2pF load capacity can be driven with a rise or fall time of Ins, with nominal effect on the originating logic cell or memory cell signal response time. If the N-channel width of the logic cell transistor has the same value computed for Z in , the rise time of the input signal of the Ring Segment Buffer corresponds to that value computed for a ring counter (Equation (16)).
• This input rise time will be approximately K times faster than the output response time of the Ring Segment Buffer driving load capacitance C.
• the N-channel width of the driving logic cell should never be less than factor 1/K times the width Z in of the first stage of the Ring Segment Buffer.
• factor K determines the relationship between the channel width of N-channel device in the first stage of the Ring Segment Buffer and the channel width of the N-channel device in the memory or logic circuit being driven by the Ring Segment Buffer.
• Segment Buffer to couple the output of a memory cell or logic cell to a load capacity and K is greater than that defined by Equation (37), then the rise time or fall time is increased approximately by the ratio of Z n /Z o based on the rise time of the
• the output signal will have a rise time 20 times as long as the intrinsic rise time of the unsampled logic cell.
• Step 1 The minimum gate width of the N- channel device in the last stage of the Ring Segment Buffer to drive the effective capacitance C is determined. This width is Z n of Equation (34).
• Step 2 The maximum value of K is
• Step 3 The maximum gate width (Z in ) of the N-channel device in the first stage of the Ring Segment Buffer is determined by using Equation (39). This is the nominal KN CELL where N CELL is the N-channel width of the logic or memory cell driving the Ring Segment Buffer.
• Step 4 Based upon the channel width of the first stage (Step 3) the last stage (Step 1) and K (Step 2), the number of stages N necessary for the Ring Segment Buffer is determined.
• Step 5 The P-channel width for each stage is ⁇ times the corresponding N-channel width.
• the devices described below can handle large loads such as off chip loads or long clock buss lines having capacitance in excess of lpF.
• the BIFET can be used as a single stage Ring Segment Buffer or in combination with a multistage Ring Segment Buffer. When used in combination with the Ring Segment Buffer, the BIFET preferably forms the last stage of the Ring Segment Buffer.
• the BIFET buffer is a non-inverting device.
• a typical BIFET driver can enhance the load driving capabilities of the Ring Segment Buffer at rise or fall times of Ins or less by a factor of about six. Accordingly, a fourfold reduction in channel width, from that described above for the Ring Segment Buffer, may be obtained.
• the delay introduced by the BIFET driver is about 20% of the input rise or fall time.
• a pair of complementary BIFET drivers may be integrated into a BICMOS driver.
• the bipolar transistors in BIFET and BICMOS drivers must be a "Lifetime Controlled" bipolar transistor as
• a BICMOS buffer 50 comprises a complementary FET inverter 40, the output 52 of which is connected to the input 51 of a Lifetime Controlled complementary bipolar transistor emitter follower 41. Both FET inverter 40 and emitter follower 41 are connected between first potential source 46 (e.g. +5V) and second potential source 47 (eg. ground). Input 49 is applied to the common gates of FETs 42 and 43, while output 54 is obtained from the common emitters 55 of bipolar transistors 44 and 45, via optional current limiting resistor 48. It will be seen that BICMOS driver 50 as configured is inverting from input 49 to output 54. BICMOS driver 50 comprises P-channel BIFET driver 42 and 44 and N-channel BIFET driver 43 and 45.
• FIG. 11A the cross section of the P-channel BIFET driver comprising P- channel FET 42 and NPN transistor 44 is shown.
• the P-channel FET's drain diffusion 56 is coupled directly to the base 57 of an NPN,
• Figure 12A illustrates the cross section of the N-channel BIFET driver comprising the N-channel FET 43 and PNP transistor 45 of Figure 10.
• the N- channel FET's drain diffusion 58 is coupled directly to the base 59 of a PNP, Lifetime Controlled bipolar transistor.
• the substrate 60, 61 for the FETs is the collector of the bipolar
• Figures 11B and 12B show the
• FIG. 13 illustrates the top view of the BICMOS integration of the N-channel and P-channel BIFETs.
• the BICMOS buffer is capable of driving high capacitive loads while greatly minimizing chip real estate needed to achieve this goal.
• the theory behind the BIFET/BICMOS buffer will be presented below.
• bipolar transistors must be lowered from the typical value of 5e-7 sec to 8e-9 sec or less. Narrow base techniques are also required. Reduction in lifetime must be achieved while maintaining a current gain ⁇ of 20 or more.
• the critical step of lowering carrier lifetime is accomplished during wafer fabrication by doping the base regions 57, 59 of the bipolar transistors with gold.
• the purpose of the gold is to introduce paired donor and acceptor recombination centers within the base regions 57, 59 with energy states within the middle of the bandgap.
• total load capacitance C is expressed as follows:
• the time-constant ⁇ o for the BICMOS structure is:
• Emitter current is expressed as:
• Time constant ⁇ o described by Equation (41) must be used in this expression.
• Figure 14 is a computer generated plot of Equation (6) with Equation (41) used for the time constant ⁇ o with a range of values for the Lifetime Controlled base recombination lifetime ⁇ p as a running parameter. It is shown in Figure 14 that the fall time of the BICMOS buffer is about 6 times less than the value attained by the inverter alone given the same capacitive loading and lma drain current. A Ins fall time can be achieved given a drain-base current of lma, a bipolar
• Figure 15 is a plot of drain-base current as a function of time t for the BICMOS buffer with lifetime as the running parameter.
• Figure 16 is a plot of emitter current as a function of time with lifetime ⁇ p as the running parameter for the same base drive current of lma and a load capacity of lpF. It is apparent from Figure 14 that there is a rise and fall delay time
• a symmetric complementary inverter introduces a delay time equal to 65% of the gate signal rise-time.
• the peak emitter current increases rapidly for decreasing lifetime ⁇ p .
• the peak emitter current is about 6 times as great as base current.
• the BICMOS buffer offers significant benefits when driving large capacitive loads and response times of Ins or less are required.
• capacitive loads of about lpF
• the N-channel gate area of the driving logic circuit need not be greater than 3x10 -8 square cm.
• Controlled bipolar transistor's base region must have a value no greater than 10 times the desired rise or fall time of the output signal. Optimum BICMOS buffering occurs when rise-time and lifetime are equal.
• gold doping the lifetime controller bipolar transistor base region is used to linearly control recombination lifetime.
• a minimum gold doping density of 10e 15 is preferred. Lifetimes as low as 2x10 -10 sec may be achieved with gold density of 10el7 cm-3.
• CMOS inverter designed to do the same job.
• the BICMOS buffer technology is totally consistent with the basic premise that no DC power dissipation is permitted in the logic system at any toggle rate.
• the BICMOS buffer technology described above may be used by itself as a one stage Ring Segment Buffer, with the channel width of the N- channel transistor being derived from Equation (34) as follows:
• the BICMOS buffer technology may also be used as the last stage of a Ring Segment Buffer, for driving large capacitive loads. In that case, the channel width (Z n ) of the last stage N-channel device is reduced by a factor of about 6. This is
• Figure 17 illustrates an Ring Segment Buffer 70 with a BICMOS driver as the last stage.
• the width of the last stage N-channel FET 43 is reduced to K n Z in /6 and the width of the last stage P-channel FET 42 is reduced to K n ⁇ Z in /6, a factor of 6 in both cases. More manageable device sizes are thereby obtained.
• CMOS logic gate having a symmetrical transfer function
• Logic gate 100 is configured as a well known CMOS three input NAND gate having three parallel P-channel MOSFETS 101A, 10IB and 101C, connected between a first potential source 102 (e.g. power supply potential V DD ) and a common output point 103.
• a first potential source 102 e.g. power supply potential V DD
• Three N-channel MOSFETs 104A, 104B and 104C are serially connected between common point 103 and a second potential source 105 (e.g. ground potential).
• Each of inputs A, B, C is connected to the gate of a corresponding one of the parallel transistors 101A, 10IB and 101C
• the width of the P- channel devices 101 is increased over the N-channel devices by ⁇ , the hole mobility factor.
• the channel width Z of the N-channel is increased by 3 to 3Z.
• the channel width of the serially connected P-channel devices is
• CMOS logic is limited to speeds of about 70 mHz.
• a Buffer Cell Logic is provided.
• Figure 19 illustrates an overview of Buffer Cell Logic.
• an integrated circuit logic chip 110 includes a plurality of interconnected logic gates 111 each of which has a predetermined number of logic gate inputs and a logic gate output, where the logic gate output of each gate is connected to the logic gate inputs of other gates to perform a predetermined logic
• each logic gate 111 includes a Ring Segment Buffer 112, coupled between the gate output and the load which the logic gate must drive.
• each logic gate may be represented by an effective capacitance, where the effective capacitance varies with the number of gate interconnections (Fan-Out), the length of the interconnection lines, the materials used for interconnections, whether the logic gate must drive an off chip logic gate or an on chip logic gate, and a number of other factors.
• each of the Ring Segment Buffers 112 are configured to drive the associated effective capacitance at a desired logic chip speed. Accordingly, the logic chip may perform the
• each Ring Segment Buffer 112 will be uniquely designed for each logic gate to drive the associated effective capacitance
• Ring Segment Buffer 112 may be a multistage Ring Segment Buffer as illustrated in Figure 9, with the logic cell 111 of Figure 19 corresponding to the logic cell 26 of Figure 9.
• a single stage Ring Segment Buffer may also be provided, depending upon the associated effective capacitance which is to be driven, so as to satisfy the factor K for the Ring Segment Buffer design.
• a single stage Ring Segment Buffer may be sufficient.
• a multistage Ring Segment Buffer may be needed.
• an odd or even number of stages may be provided in the Ring Segment Buffer in order to provide an inverted logic signal or a non- inverted logic signal, respectively, at the Ring Segment Buffer output.
• negative logic (NAND/NOR) CMOS may be converted to positive logic (AND/OR).
• a BICMOS Ring Segment Buffer may be provided as buffer 112 Figure 19.
• the BICMOS buffer is illustrated in Figure 10, with the input 49 of Figure 10 being coupled to the logic gate outputs of Figure 19.
• the buffer of Figure 19 may be a Ring Segment Buffer having a BICMOS buffer for its last stage, as illustrated in Figure 17.
• the Ring Segment Buffer with a BICMOS output driver may be used with the highest capacitive loads.
• Figure 20 illustrates a CMOS NAND gate which is directly coupled to a complementary Lifetime
• Controlled bipolar junction transistor emitter follower buffers the logic cell output from effective
• FIG. 11A illustrates a Lifetime Controlled bipolar transistor emitter follower buffered NOR gate.
• Figure 22 illustrates a BICMOS buffered AND gate. The buffer cell in this circuit is inverting.
• Figure 23 illustrates a BICMOS buffered OR gate.
• Figures 20-23 are all capable of driving heavy capacitive loads with zero DC power dissipation, while maintaining a rise and fall time of 1
• the channel width of the series connected transistors should be increased by a factor proportional to the number of
• the unique delay and power driving capabilities of the Ring Segment Buffer may be utilized in conjunction with memory circuits to provide a single clock pulse memory cell, as described below.
• a single clock pulse provides for shifting a new logic value into the memory cell while reading out the old logical value before the end of a predetermined delay governed by the Ring Segment Buffer.
• memory based circuits that utilize the Ring Segment Buffer as a delay and load driving means for clock generators, delay latches and binary counters.
• the combination of a memory cell and a Ring Segment Buffer is referred to as "Delay Storage" technology.
• the Delay Storage technology of the present invention allows single sampling clock pulses to be used internal or external of the Delay Storage cell.
• the internal clock approach is very powerful since much of the logic circuitry used by external clocking schemes is eliminated, offering a significant reduction in chip real estate while still providing a very high speed operation.
• the Ring Segment Buffer of the present invention may be used as a well controlled time delay device referred to as a "Delay Ring Segment Buffer".
• the Delay Ring Segment Buffer not only provides delay but is also designed as a power driving means using the design methodology described above. This feature is uniquely utilized in the Delay Storage technology described below.
• Equation (37) n is the number of Ring Segment Buffer stages.
• Figure 24 illustrates a three stage Ring Segment Buffer configured to function as a time delay device. This delay device is also capable of driving substantial capacitive loading at both output terminals while maintaining Ins rise or fall times.
• Figure 24 corresponds to the Ring Segment Buffer illustrated in Figure 9, except that an extra inverter 204, comprising P-channel FET 201 and N- channel FET 202, is coupled to the Ring Segment Buffer output 25C, to provide complementary signal outputs 30 and 203.
• Buffer delay cell may be clock pulses, an input from a random access memory (RAM) cell, or some other digital signal.
• the input signal rise time should be in the low
• T d 0.65NT rise (45) where n is the number of stages in the Ring Segment Buffer (3 in Figure 24) and T rise is the rise time selected for the inverters comprising the Ring
• the length L o of the P-channel and N- channel devices in the Ring Segment Buffer delay cell may be chosen to define a desired rise time to control delay for a given K. Or, for a given rise time, channel length L o may be chosen to obtain the desired value for K. The number n of stages may also be used to control delay time. Another virtue of the Ring Segment Buffer delay cell is that delay time is quite tolerant of supply voltage variations if the inverters are designed with symmetric voltage transfer functions, in a manner already described.
• FIG. 25 illustrates the basic use of the
• Ring Segment Buffer as a delay device in combination with a RAM cell.
• RAM cell 210 comprises cross coupled pairs of FETs 211-214 to form a static memory cell in the manner well known to those having skill in the art.
• Complementary logic inputs 215 and 216 are provided, in the manner well known to those having skill in the art.
• the output 213 of the memory cell 210 is connected to the input 24a of the Delay Ring Segment Buffer (Delay Ring Segment Buffer) 200 (Figure 24).
• Output terminals A (203) and B (30) are shown in Figure 25.
• the A terminal must follow positive logic ground rules and the B terminal, negative logic ground rules independent of n. For example, if a rising input signal of the RAM cell is coupled to the input of the Delay Ring
• the contents of the RAM cell 210 are provided at the outputs 203, 30 of the Delay Ring Segment Buffer 200 after a predetermined delay T d , defined by Equation (45). Accordingly, if the contents of the memory cell 210 are changed at a time T o , the output of the Delay Ring Segment Buffer 200 will not change until time T o +T d . Until time T o +T d , the old contents of the memory cell will be present at the outputs 203, 30 of the Delay Ring Segment Buffer. This allows the contents of the memory cell 203 to be changed with the old contents of the cell being available up to a time T d later.
• a shift register responsive to a single clock pulse may thereby be provided. In contrast with known shift registers, the output of which must be sampled before a new input value is stored therein, the shift registers of the present invention allow storing the new value first, while sampling the old value simultaneously, all using a single clock pulse.
• Trigger stage 250 includes memory cell 210 coupled to Delay Ring Segment Buffer 200. Clocking is provided by N-channel transistors 251a and 251b, and a "reset" function is provided by transistor 252. The common binary input 253 is provided to cell 210 via transistors 254a and 254b. As is well known to those having skill in the art, the trigger stage can be modified to function as a binary shift register. The shift register is shown in Figure 26b.
• Figure 27 illustrates a four-stage shift register configured using shift register stages
• Figure 28 illustrates a four-stage binary counter.
• the counter couples the complementary "B" output 30 to the next stage's input 253 using CMOS AND gates 260 as necessary.
• the outputs 203 and 30 of Delay Ring Segment Buffer 200 are fed back to memory cell 210 via transistors 261 and 262 respectively. Both delay output signals are coupled to the input logic terminals that control the state of the RAM cell. This digital feedback causes the RAM cell to oscillate from one binary state to the other.
• the toggle rate of this clock generator is the inverse of twice the delay T d of the Ring Segment Buffer.
• the Delay Ring Segment Buffer 200 may also be used to construct an asynchronous clock pulse generator.
• Figure 30 illustrates the control logic required to generate clock pulses at each rising edge of a stream of digital signal pulses.
• Figure 31
• the output logic gate 270 in Figures 29 and 30 is a "power AND" gate consisting of a two-input CMOS NAND gate buffered by a suitable Ring Segment Buffer to drive the anticipated load.
• Block I (271) is an inverter.

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• 1990
  • 1990-03-21 US US07/497,103 patent/US5030853A/en not_active Expired - Lifetime
• 1991
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