WO1991009367A1 - Ameliorations de systemes informatiques - Google Patents

Ameliorations de systemes informatiques Download PDF

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Publication number
WO1991009367A1
WO1991009367A1 PCT/GB1990/001817 GB9001817W WO9109367A1 WO 1991009367 A1 WO1991009367 A1 WO 1991009367A1 GB 9001817 W GB9001817 W GB 9001817W WO 9109367 A1 WO9109367 A1 WO 9109367A1
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WO
WIPO (PCT)
Prior art keywords
address
computer system
chip
coding
changed
Prior art date
Application number
PCT/GB1990/001817
Other languages
English (en)
Inventor
David Flynn
Original Assignee
Eo Computer Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eo Computer Limited filed Critical Eo Computer Limited
Publication of WO1991009367A1 publication Critical patent/WO1991009367A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/14—Conversion to or from non-weighted codes
    • H03M7/16—Conversion to or from unit-distance codes, e.g. Gray code, reflected binary code

Definitions

  • This invention relates generally to computer systems and in particular to methods by which the principal CPU chip accesses other chips, more especially but not exclusively a separate or an external memory chip, within the system.
  • CISCs Complicated Instruction Set Computers
  • RISCs Reduced Instruction Set Computers
  • CISCs Complicated Instruction Set Computers
  • RISCs Reduced Instruction Set Computers
  • CISCs are older and their main characteristic is that their native instruction set is such that one instruction can perform several operations to achieve a complicated operation. This approach was satisfactory when machines were programmed at a fairly low level, but began to break down as compiler technology advanced. Under these circumstances it was noted that compilers hardly ever made use of the more complicated instructions and RISCs were introduced.
  • RISC computers have a simple instruction set so that a compiler is able to make much better use of it.
  • a consequence of the simpler instruction set is that more instructions are required for a given program than that required by a CISC program. This increases the rate at which instructions are fetched from memory and also increases the length of sequential instruction fetches between branches in the program.
  • the power consumption of the whole system is dictated by the rate at which memory is accessed and how wide the memory buses are (the number of data and address bits). It is well known that power can be reduced by integrating the computer and the memory onto the same chip. This is because power does not have to be expended changing the state of address or data bus lines.
  • the integration of memory onto the same chip as the computer generally also means that the computer can operate faster.
  • the amount of memory that can be integrated onto a chip is limited and for all but the simplest applications it is necessary to store programs and data in memory that is not on the same chip as the computer (principal chip). Under these circumstances any reduction in the rate at which instructions or data are accessed in memory will reduce the power requirement. Similarly if the number of lines (wires) that have to change between different accesses is reduced then the power requirement will also be reduced.
  • a method of accessing a separate chip from the principal CPU chip in a computer system according to which the principal CPU chip is address line encoded so that, on the address bus and for at least one group of the address lines, the address codes are changed sequentially so that at each step only one address code is changed.
  • a computer system having a principal CPU chip (computer) and at least one separate or external chip such as a memory chip, wherein, the principal CPU chip is address line encoded so that in use, on the address bus and for at least one group of the address lines, the address codes are changed sequentially so that at each step only one address code is changed.
  • the principal CPU chip is address line encoded so that in use, on the address bus and for at least one group of the address lines, the address codes are changed sequentially so that at each step only one address code is changed.
  • the invention is also applicable to the accessing of data on the data bus, e.g., in a true Harvard architecture system.
  • the technique can be applied to both address (where the information is in memory) and data (what the information is) lines of memory.
  • the encoding used for addresses will be different to the encoding used for data because the manner in which the lines are used is different.
  • the technique can be applied to both standard processors and custom designed processors, in order to reduce power consumption.
  • Gray coding is efficient because for sequential accesses only one address line transitions between each address change.
  • the invention thus also extends to the combination with the computer system of an input device and a floppy disc or other magnetic storage device bearing a program which enables the principal CPU chip to perform sequential accessing on the address or data bus as aforesaid.
  • Gray coding is not directly possible for a standard, off the shelf, processor because unencoded address lines come from the chip.
  • the processor has some memory on chip (whether ROM, RAM or cache memory) a small program can be devised to perform the coding. In this case the processor would run the instructions more slowly than the customised case.
  • a more radical approach is to analyse a large number of programs and devise a coding scheme for the native instruction bit patterns of the processor itself, so as to reduce the number of transitions between instructions and thereby achieve the objective of the invention - ie power reduction.
  • data line coding could provide power reduction as well, although it requires more work than address line encoding since data is controlled by the user and therefore "random",
  • Figure 1 is a block diagram showing conventional computer architecture
  • Figure 2 is a block diagram showing a revised architecture employing address line encoding for power saving
  • Figure 3 is a block diagram showing a modification of the architecture of Figure 2.
  • Addresses are output binary coded conventionally and because the address-lines must be driven off-chip to all memory devices and some input/output peripherals (with fairly heavy capacitive loading normally), in systems where power or system noise is to be reduced, in accordance with the invention the addresses are coded to exploit the sequential characteristic in favour of reduced address line transitions over conventional binary coding.
  • Gray coding was devised in the late nineteenth century for use in telegraph systems. Gray coding in digital electronics design is synonymous with "reflected binary" counting. In a binary up-counter the count bit pattern is alternate O's and l's (010101010) whilst the Gray counter bit pattern has the 0 and 1 sequence then reflected the next two counts as 1 and 0 (01100110).
  • Gray coding of address lines is in a paged memory system.
  • Such a system with a page size of 256 bytes for example, benefits from the coding of the low 8 address lines before the addresses are broadcast to the memory system.
  • the fast Gray-coding hardware tends to generate spikes from a synchronous binary count, so in practice addresses are re-latched and driven off-chip only when a coded address is stable.
  • LDM/STM Load and Store Multiple instructions within pages, as well as executable code with sequential runs, can all benefit from a system such as that exemplified above, with the potential saving of up to one half of the address driver power.
  • LDM/STM Load and Store Multiple instructions
  • ARM Acorn RISC machine
  • executable code with sequential access runs can all benefit from a system such as that exemplified above, with the potential saving of up to one half of the address driver power.
  • Figure 1 shows the architecture of a conventional computer system
  • Figure 2 shows the modified architecture of a system in accordance with the invention. Both figures are self-explanatory and will be clear without further description. It should be mentioned, however, that the system of Figure 2 will generally include a data code decoder on the data bus leading to the CPU.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

Système informatique possédant une puce d'unité centrale (UC) principale et une puce de mémoire séparée, la puce d'unité centrale principale est encodée par lignes d'adresses, par exemple grâce au code Gray. Ainsi lors de l'utilisation, les codes d'adresses sur le bus d'adresses sont modifiés séquentiellement de telle sorte qu'à chaque étape d'accès un code d'adresse seulement est modifié. On peut encoder de façon analogue l'information sur le bus de données.
PCT/GB1990/001817 1989-12-15 1990-11-23 Ameliorations de systemes informatiques WO1991009367A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8928409.5 1989-12-15
GB8928409A GB2239113B (en) 1989-12-15 1989-12-15 Power reduction in computer systems

Publications (1)

Publication Number Publication Date
WO1991009367A1 true WO1991009367A1 (fr) 1991-06-27

Family

ID=10668027

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB1990/001817 WO1991009367A1 (fr) 1989-12-15 1990-11-23 Ameliorations de systemes informatiques

Country Status (5)

Country Link
EP (1) EP0505383A1 (fr)
JP (1) JPH05502312A (fr)
AU (1) AU6747690A (fr)
GB (1) GB2239113B (fr)
WO (1) WO1991009367A1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69521640T2 (de) * 1994-03-29 2002-05-29 Matsushita Electric Industrial Co., Ltd. Datenübertragungsvorrichtung und -verfahren zur Verminderung elektrischer Wechsel
EP0713173A1 (fr) * 1994-09-30 1996-05-22 Texas Instruments Incorporated Système de traitement de données
US6061276A (en) 1997-02-07 2000-05-09 Fujitsu Limited Semiconductor memory device and a semiconductor integrated circuit
US6134168A (en) * 1997-04-25 2000-10-17 Texas Instruments Incorporated Circuit and method for internal refresh counter
GB2366634B (en) * 2000-09-11 2003-03-12 Lucent Technologies Inc Memory addressing
GB2375625B (en) 2001-05-18 2005-08-31 At & T Lab Cambridge Ltd Microprocessors with improved power efficiency

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4532587A (en) * 1981-08-26 1985-07-30 Texas Instruments Incorporated Single chip processor connected to an external memory chip

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4556960A (en) * 1982-12-13 1985-12-03 Sperry Corporation Address sequencer for overwrite avoidance

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4532587A (en) * 1981-08-26 1985-07-30 Texas Instruments Incorporated Single chip processor connected to an external memory chip

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
EDN ELECTRICAL DESIGN NEWS vol. 30, no. 13, 13 June 1985, BOSTON,MASSACHUSSETS US pages 196 - 199; D.G.SPOREA: "Program provides gray/binary conversion" see the whole document *
IBM TECHNICAL DISCLOSURE BULLETIN. vol. 13, no. 5, October 1970, NEW YORK US pages 1397 - 1398; P.B.SHATTUCK: "GRAY CODE COUNTER AND DECODER" see the whole document *
IBM TECHNICAL DISCLOSURE BULLETIN. vol. 32, no. 4A, September 1989, NEW YORK US pages 161 - 165; "DUAL BUS PROCESSOR ARCHITECTURE" see page 161, line 1 - page 163, line 19; figures 1-3 *

Also Published As

Publication number Publication date
AU6747690A (en) 1991-07-18
GB8928409D0 (en) 1990-02-21
JPH05502312A (ja) 1993-04-22
GB2239113A (en) 1991-06-19
EP0505383A1 (fr) 1992-09-30
GB2239113B (en) 1994-02-23

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