EP0101718B1 - Ordinateur avec topographie automatique du contenu de la memoire dans des registres - Google Patents

Ordinateur avec topographie automatique du contenu de la memoire dans des registres Download PDF

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Publication number
EP0101718B1
EP0101718B1 EP83901027A EP83901027A EP0101718B1 EP 0101718 B1 EP0101718 B1 EP 0101718B1 EP 83901027 A EP83901027 A EP 83901027A EP 83901027 A EP83901027 A EP 83901027A EP 0101718 B1 EP0101718 B1 EP 0101718B1
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EP
European Patent Office
Prior art keywords
stack
registers
stack pointer
address
cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP83901027A
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German (de)
English (en)
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EP0101718A1 (fr
Inventor
David Roger Ditzel
Hubert Rae Mclellan, Jr.
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
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Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of EP0101718A1 publication Critical patent/EP0101718A1/fr
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30134—Register stacks; shift registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4482—Procedural
    • G06F9/4484—Executing subprograms
    • G06F9/4486—Formation of subprogram jump address
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/451—Stack data

Definitions

  • This invention relates to digital computers and, in particular, to the automatic allocation of machine registers.
  • registers have faster access time than main memory, but, because of cost, are few in number.
  • the use of registers was at one time controlled directly by the machine language programmer.
  • the use of registers is now controlled principally by another computer program, the compiler.
  • the compiler transforms an easier to understand high level source language into the lower level object language of the machine. Part of this transformation task performed by the compiler is to place currently active data items in registers as much as possible. In this fashion, references to main memory are reduced, leading to faster overall performance.
  • This task, called register allocation is burdensome to the compiler program, resulting in compilers that are large and complex, awkward to maintain, and costly to prepare.
  • Computer instructions specify the data operands to be used in an arithmetic or logical operation through the use of addressing modes.
  • An address is the common term used to describe the location in storage of a particular piece of data or an instruction.
  • An addressing mode may, for example, specify that the data is to be found in a register, at an address specified in the instruction, or at an address contained in a particular register specified in the instruction.
  • a particularly common' addressing mode called "relative addressing" and found in many computers, is to form the address of an operand by adding the contents of a register to a constant specified in the instruction. This addressing mode is frequently used in the implementation of what is called a stack data structure. Because of this common use, the term “stack relative addressing" is frequently employed, and the particular register is called the stack pointer register.
  • Stack relative addressing is commonly used by compilers, using a data structure called a stack to allocate space.in the computer's memory for local program variables, parameters, and temporary storage. Allocating space on a stack is advantageous because it provides a very simple and efficient technique for allocating space. The details of such a stack and how it is used by the compiler will not be discussed in more detail here; such details are common enough to be found in nearly any text on compiler design.
  • One such book is "Principles of Compiler Design”. by Messrs. A. V. Aho and J. D. Ullman, Addison-Wesley Publishing Co., (1977).
  • both the speed advantages of register-oriented computers and the compiler simplifications resulting from memory-to-memory oriented computers are realized in a single machine by providing a mechanism in which memory contents are automatically mapped into machine registers during program execution. This process called "binding", was preferably performed in the prior art during compilation of the program and not during execution.
  • instructions are partially decoded before being placed in an instruction cache.
  • operand identifiers with stack relative addresses i.e. the value of a stack pointer plus an offset, are operated upon to form an absolute memory address. This memory address is stored in the instruction cache.
  • These operand addresses in the instruction cache are checked to see if they fall within the range of addresses for which the corresponding data are currently stored in the register set. If so, then the addressing mode is changed so that the address may be used as a register index. In this fashion, registers are automatically allocated by hardware, rather than by traditional compiler methods.
  • registers take the form of a circular buffer in order that the lower order bits of the absolute memory address can also be used as the register address in the buffer.
  • IBM Technical Disclosure Bulletin, Vol. 15, No. 4, Sept. 1972, pages 1100 and 1101 describes a computer with slow and high speed (cache) stores. It has instruction prefetch and decode means for partial instruction decoding, which means are operative during execution of an object program for automatically (i.e. not during compilation) allocating variables from the slow main memory into the high speed cache stores. There is an instruction cache for receiving partially decoded instructions. Contrary to the present invention according to the IBM disclosure the high speed stores are not necessarily registers, and variables are always provided by the high speed cache stores. According to the present invention variables are allocated by the execution of a specific instruction (catch) in the instruction prefetch and decode unit.
  • the address mode is automatically adapted.
  • FIG. 1 there is shown a block diagram of the relevant parts of a digital computer which are useful in implementing the present invention.
  • Data and instructions are stored in main memory 1.
  • Data operands are fetched from memory 1 under control of the execution unit 4 over bus 8 and stored in the execution unit 4, to be described more fully below.
  • Instructions are fetched from memory 1 over bus 5 by the instruction prefetch and decode unit 2.
  • the instructions are partially decoded, as will be described more fully below, in the prefetch and decode unit 2.
  • the partially decoded instructions are then placed in the instruction cache 3 over bus 6. From instruction cache 3, the partially decoded instructions are read by the execution unit 4 over bus 7.
  • the instructions are executed in the execution unit 4 using the aforesaid operands.
  • Stack pointer register 10 performs the traditional function of delimiting the boundary between free and used space in the allocation of program variables.
  • Stack pointer register 10 with the maximum stack pointer register 11 also perform the functions of head and tail pointers, respectively, in implementing traditional circular buffers which contain the top data elements of the stack.
  • the data for the circular buffers is contained in stack caches 18 and 19, these stack caches being memory register devices.
  • Stack pointer in register 10 points to the lowest address of data currently maintained in stack caches 18 and 19.
  • the maximum stack pointer in register 11 points to the highest address of data currently maintained in stack caches 18 and 19.
  • Instruction cache 3 is a conventional cache memory device which saves the most recently used instructions.
  • the instruction cache 3 may hold many instructions, and for each instruction there exist several fields: the instruction opcode field 16, the left address field 15, the right address field 17, and the tag which is composed of the instruction address field 13 and the value of the stack pointer associated with the particular instruction 14.
  • the left address field 15 and the right address field 17 hold the addresses for accessing the operands which may be sent to the left and right inputs, respectively, to the ALU 24.
  • the addressing mode e.g., main memory 1 or stack caches 18 and 19, of each operand is held in the instruction opcode field 16 of the cache.
  • a prefetch unit In most computers with a cache, a prefetch unit would fetch instructions from memory 1 and place them directly in instruction cache 3 without any intervening conversions. In accordance with the present invention, however, the prefetch and decode unit 2 will decode stack relative addressing modes before proceeding to place the instruction in instruction cache 3. This method is possible because the calling sequence and instruction set, as will be described more fully below, guarantee that the stack pointer in register 10 will not change except at procedure call and return.
  • the value of the stack pointer in register 10 is added to the value of the offset specified in the instruction to form the absolute memory address of the operand.
  • This modified instruction using the computed memory address of the operand, will be placed in the instruction cache 3 in the left or right address fields 15 or 17, respectively.
  • the prefetch and decode unit 2 converts a stack relative address to that of a memory address, that memory address is also checked to see if the data resides in the stack cache registers 18 and 19 or in main memory 1. This check is accomplished by comparing, in comparator 9, the memory address to the stack pointer in register 10 and the maximum stack pointer in register 11.
  • the data will be resident in stack caches 18 and 19 and the addressing mode of the instruction is changed to the register addressing mode. If the memory address does not lie between the address of the stack pointer 10 and the maximum stack pointer 11, inclusive, then the data will be resident in main memory 1, and the addressing mode of the instruction is changed to main memory address mode.
  • the left operand for the arithmetic and logic unit 24 is obtained by addressing memory over bus 25. If the addressing mode of the left operand is that of a main memory address, then the address sent over bus 25 will cause main memory 1 to send the requested operand to the left ALU input over bus 32. If the addressing mode of the left operand is that of a register, then the low order bits of the word part of the address from bus 25 is sent to stack cache registers 18 over bus 28 and the data is presented on bus 36.
  • the word part of the address is that part which contains no bits for addressing bytes within a memory word.
  • bus 28 for the low order bits of the word part of the address from bus 25 is the base two logarithm of the number of the stack cache registers 18.
  • the size of registers 18 and 19 should be a power of two. For example, if 1024 registers were to be provided, then bus 28 would consist of 10 signal lines.
  • the address on bus 28 functions as an automatically computed register address to registers 18.
  • Byte addressing for example with a four byte wordsize, is provided by sending the low two bits of the byte address from bus 25 to multiplexer 20 over bus 29. In this fashion, full words, half-words, or bytes may be read, though full words and half-words may not cross word boundaries.
  • Multiplexor 20 provides the necessary alignment and sign extension of operands for byte addressing.
  • the data is supplied to the left ALU input over bus 38.
  • the right operands are developed in a symmetric fashion to the left operands with registers 19, multiplexor 21, busses 30 and 31.
  • the advantage of duplicating the registers 18 and 19, and the multiplexors 20 and 21, resides in permitting faster access to both left and right ALU operands through parallelism.
  • the ALU 24 has computed the result, the result is sent via bus 32 back to either registers 18 and 19 or to main memory 1, in accordance with the addressing mode specified for the destination.
  • Execution control unit 22 operates based upon the value of the program counter 40 and the instruction presented on bus 26. The logically sequential instruction from the instruction cache 3 is requested from execution control unit 22 over bus 33.
  • the registers in stack cache 18 and 19 hold contiguous words of memory, and are far less costly to implement in terms of complexity and circuit density than traditional caches. Re-entrancy for cached instructions is guaranteed by including the stack pointer in field 14 and the instruction address in field 13 as part of the tag in the instruction cache 3.
  • the CALL instruction takes the return address, usually, the value of the program counter 40, and saves it on the stack, then branches to the target address.
  • a stack frame as used in the present invention is shown in Fig. 3.
  • the target of a CALL instruction is an ENTER instruction.
  • the ENTER instruction is used to allocate space for the new procedure's stack frame by subtracting its operand, that is, the size of the new stack frame in machine words, from the stack pointer in register 10.
  • the RETURN instruction deallocates the space for the current stack frame by adding its operand to the stack pointer in register 10, then branching to the return address on the stack.
  • the CATCH instruction is always the next instruction executed following a RETURN instruction and is used to guarantee that the stack cache registers 18 and 19 are ⁇ filled at least as deep as the number of entries specified by the operand of the CATCH instruction.
  • ENTER and CATCH instructions are also used to handle the cases where the registers of stack caches 18 and 19 are not large enough to hold the entire stack.
  • the ENTER instruction attempts to allocate a new set of registers in the stack caches 18 and 19 equal to the size of the new stack frame. If free register space exists in the stack caches 18 and 19 for the entire new stack frame, all that needs be done is to modify the stack pointer in register 10.
  • the entries nearest the address pointed to by the maximum stack pointer in register 11 of stack caches 18 and 19 are flushed back to memory 1 over bus 32 under the control of stack cache control unit 23.
  • the size of the new stack frame is less than the size of stack caches 18 and 19, only the size of the new stack frame minus the number of free entries must be flushed back to memory 1.
  • the size of the new stack frame is greater than the size of the entire stack cache 18 or 19, all active entries then preexisting in stack cache registers 18 and 19 are flushed back to memory 1 under control of stack cache control unit 23 over bus 32. Furthermore, only the part of the new frame nearest the address pointed to by the stack pointer in register 10, that is, the top entries, is kept in the stack caches 18 and 19.
  • stack cache references can be bound to register numbers and accessed as would be traditional registers without having to check to see if the data is actually resident in the stack caches 18 and 19.
  • a stack cache reference will never miss.
  • An advantage of the present invention is that the access time of stack cache registers 18 and 19 will be substantially equal to that of registers in a general register machine (not shown).
  • 'stack cache' has been used, as described above, to name the circular buffer registers 18 and 19 because of the early binding of stack offsets and in assigning register numbers automatically. There is no restriction from using a similar mechanism to "cache" any other particular piece of memory. Substantial benefits can be gained from allocating a small number of registers for global variables.
  • registers in stack caches 18 and 19 may be used for mapping therein global variables from the memory 1. These registers would cover a static area of memory and therefore not require the use of circular buffers. Even large programs tend to use relatively few scalar global variables; a small percentage of these account for most of the dynamic usage of global variables.
  • VLSI very large scale integrated

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)

Claims (6)

1. Un ordinateur ayant une mémoire centrale (1) destinée à conserver des variables dans une pile (figure 3), caractérisé par des registres de machine (18,19) constituant une antémémoire de pile destinée à conserver des variables, des moyens (22) destinés à transférer automatiquement les variables de procédure entre la pile de mémoire centrale et les registres de machine pendant l'exécution d'un programme objet, des moyens définissant un pointeur de pile (10) et un pointeur de position maximale de pile (11), pour délimiter les positions d'enregistrement inférieure et supérieure dans les registres de machine (18, 19), des moyens (2) destinés à décoder partiellement des instructions en additionnant des déplacements au pointeur de pile, des moyens (9) qui fonctionnent sous la dépendance du pointeur de pile et du pointeur de position maximale de pile de façon à déterminer si une variable de procédure est enregistrée dans la mémoire centrale (1) ou dans les registres de machine (18, 19); et des moyens (2) destinés à changer le mode d'adressage d'une instruction partiellement décodée, afin d'adresser les registres de machine (18, 19) dans le cas de la détermination du fait qu'une variable respective est enregistrée dans les registres.
2. Un ordinateur selon la revendication 1, dans lequel l'antémémoire de pile consiste en une mémoire tampon circulaire.
3. Un ordinateur selon la" revendication 1 ou 2, dans lequel l'adresse d'antémémoire de pile est constituée par les bits d'ordre inférieur de l'adresse pour la mémoire centrale.
4. Un ordinateur selon l'une quelconque des revendications précédentes, comprenant des moyens destinés à retourner un ensemble de variables de l'antémémoire de pile vers la mémoire centrale, sous l'effet de la détermination du fait que l'espace d'enregistrement exigé pour des variables de procédure dépasse la capacité d'enregistrement disponible de l'antémémoire de pile.
5. Un ordinateur selon l'une quelconque des revendications précédentes, comprenant une antémémoire d'instruction destinée à enregistrer les instructions.
6. Un procédé d'utilisation de registres de machine pour l'enregistrement de variables de procédure, caractérisé en ce que: on transfère automatiquement les variables de procédure entre une pile en mémoire centrale et les registres de machine pendant l'exécution d'un programme objet, on utilise un pointeur de pile (10) et un pointeur de position maximale de pile (11) pour délimiter les positions d'enregistrement inférieure et supérieure dans les registres de machine (18, 19), on décode partiellement des instructions en additionnant des déplacements au pointeur de pile, on détermine, sous la dépendance du pointeur de pile et du pointeur de position maximale de pile, si une variable de procédure est enregistrée dans la mémoire centrale (1) ou dans les registres de machine (18, 19); et on change le mode d'adressage d'une instruction partiellement décodée, de façon à adresser les registres de machine (18, 19) lorsqu'on a déterminé qu'une variable respective est enregistrée dans les registres.
EP83901027A 1982-02-24 1983-02-15 Ordinateur avec topographie automatique du contenu de la memoire dans des registres Expired EP0101718B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US35165682A 1982-02-24 1982-02-24
US351656 1982-02-24

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EP0101718A1 EP0101718A1 (fr) 1984-03-07
EP0101718B1 true EP0101718B1 (fr) 1986-05-07

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EP (1) EP0101718B1 (fr)
JP (1) JPH0666052B2 (fr)
CA (1) CA1187200A (fr)
DE (1) DE3363340D1 (fr)
GB (1) GB2115963B (fr)
WO (1) WO1983003017A1 (fr)

Families Citing this family (4)

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Publication number Priority date Publication date Assignee Title
US4811208A (en) * 1986-05-16 1989-03-07 Intel Corporation Stack frame cache on a microprocessor chip
DE3726192A1 (de) * 1987-08-06 1989-02-16 Otto Mueller Stacksteuerung
CN102141905B (zh) * 2010-01-29 2015-02-25 上海芯豪微电子有限公司 一种处理器体系结构
GB2622286A (en) * 2022-09-02 2024-03-13 Advanced Risc Mach Ltd Synchronization of load/store operations

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US3736566A (en) * 1971-08-18 1973-05-29 Ibm Central processing unit with hardware controlled checkpoint and retry facilities
JPS5474651A (en) * 1977-11-28 1979-06-14 Toshiba Corp Stack control system
JPS5543136A (en) * 1978-09-20 1980-03-26 Hikari Hodo Kk Production of asphalten mixture for pavement
JPS5725069A (en) * 1980-07-21 1982-02-09 Hitachi Ltd Vector data processing equipment

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
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IBM Technical Disclosure Bulletin, vol. 15, no. 4, Sept. 1972, pp. 1100-1101 *

Also Published As

Publication number Publication date
EP0101718A1 (fr) 1984-03-07
DE3363340D1 (en) 1986-06-12
GB2115963B (en) 1985-10-30
CA1187200A (fr) 1985-05-14
JPS59500241A (ja) 1984-02-16
GB8304709D0 (en) 1983-03-23
WO1983003017A1 (fr) 1983-09-01
JPH0666052B2 (ja) 1994-08-24
GB2115963A (en) 1983-09-14

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