WO1991004213A1 - Systeme automatique de transport de tranches - Google Patents

Systeme automatique de transport de tranches Download PDF

Info

Publication number
WO1991004213A1
WO1991004213A1 PCT/US1990/004877 US9004877W WO9104213A1 WO 1991004213 A1 WO1991004213 A1 WO 1991004213A1 US 9004877 W US9004877 W US 9004877W WO 9104213 A1 WO9104213 A1 WO 9104213A1
Authority
WO
WIPO (PCT)
Prior art keywords
coupled
staging
meanε
gates
robotic
Prior art date
Application number
PCT/US1990/004877
Other languages
English (en)
Inventor
Fred Wong
George E. Zilberman
Wilhelmus H. Holtkamp
Original Assignee
Rapro Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rapro Technology, Inc. filed Critical Rapro Technology, Inc.
Publication of WO1991004213A1 publication Critical patent/WO1991004213A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67161—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
    • H01L21/67178—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers vertical arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
    • H01L21/67184—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the presence of more than one transfer chamber

Definitions

  • the present invention relates to automated wafer transport systems used for processing semiconductor wafers during the manufacture of integrated circuits.
  • Automated single wafer transport systems are utilized in the manufacture of integrated circuits, to transport wafers of semiconductor material between process chambers, such as chemical vapor deposition chambers, annealing chambers, and etching chambers .
  • the wafers are typically transported in a cassette that contains a number of wafers in a clean room environment from one process chamber to the next.
  • Some systems consist of a cassette loadlock and a robotic transfer chamber with a robotic arm which removes individual wafers from the loadlock and transports them to one or more process chambers coupled with the robotic transfer chamber.
  • the present invention provides an apparatus for automated transport of wafers, or other process substrates, among a plurality of reaction chambers.
  • the apparatus comprises two cassette docks for docking a cassette holding a plurality of wafers.
  • a first robotic transfer chamber having a first plurality of gates, two of which are coupled to respective cassette docks, transports wafers through the plurality of gates.
  • a second robotic transfer chamber having a second plurality of gates, transports wafers through the second plurality of gates.
  • a plurality of process stations is mounted with the apparatus, each coupled to one or more of the second pl ⁇ rality of gates of the second robotic chamber.
  • a staging chamber is coupled to one of the first plurality of gates on the first robotic transfer chamber, and to one of the second plurality of gates on the second robotic chamber.
  • the staging chamber includes a plurality of stations for staging the wafers and is used for transportation of wafers from the first robotic transfer chamber into the second robotic transfer chamber. Accordingly, at least one of the stations in the staging chamber can be used for incoming pre-process wafers while another of the stations can be used for outgoing post-process wafers.
  • a monitor system and/or preparing/finishing apparatus is mounted with the staging chamber, for monitoring and/or preparing/finishing a characteristic of wafers in either a pre-process or post-process station.
  • a programmable control console which is coupled to the wafer transport system and the process stations, controls the transportation of single wafers through the stations in the staging chamber, the process stations, and the cassette.
  • the programmable control console may also be coupled to the monitor mounted with the staging chamber, for providing further input to the transportation control process.
  • the staging chamber provides for a modular interface between the robotic chambers that allows for unlimited expansion of the system.
  • the system referred to above could have a second staging chamber coupled to one of the gates in the second robotic chamber.
  • a third robotic transfer chamber is coupled to the second staging chamber and to a plurality of other process stations.
  • the second staging chamber also includes at least two staging stations, so that wafers moving into the third robotic chamber are not blocked by wafers being moved out and vice-versa. This aspect allows for vertical expansion of the system.
  • a second staging chamber is coupled to one of the first plurality of gates of the first robotic transfer chamber and to a third robotic transfer chamber.
  • the third robotic chamber may be coupled to a second transportation system through a similar second staging chamber.
  • Fig. 1 is a schematic diagram of a single wafer transportation system according to the present invention.
  • Fig. 2 is a schematic diagram of a single wafer transportation system according to the present invention which has been vertically expanded using the modular staging chamber and robotic transfer chamber.
  • Fig. 3 is a schematic diagram of a single wafer transportation system according to the present invention which has been horizontally expanded.
  • Fig. 4 is a flow chart illustrating the control algorithm followed in moving a wafer from an entry stage through a process station and back to the exit elevator.
  • Fig. 5 is a flow chart illustrating operation of the "place wafer on entry stage" step shown in Fig. 4.
  • Fig. 6 is a flow chart illustrating operation of the "place wafer on IA (inner arm)" step of Fig. 4.
  • Fig. 7 is a flow chart illustrating operation of the "place wafer in PI (process station one)" step of Fig . 4 .
  • Fig. 8 is a flow chart illustrating operation of the "remove wafer from PI" step of Fig. 4.
  • Fig. 9 is a flow chart illustrating operation of the "place wafer on exit stage, then on OA (outer arm)" step of Fig. 4.
  • Fig. 10 is a flow chart illustrating operation of the "place wafer in EX ELEV (exit elevator)" of Fig. 4.
  • a single wafer transport system is set out in Fig. 1.
  • the system includes a first cassette dock 10 for staging a cassette 11 of semiconductor wafers 12 into the system.
  • the dock 10 may be adapted for ' single wafers, SMIF compartments, or for other process substrates.
  • the cassette dock 10 is coupled at gate 13 with a first robotic transfer chamber 14.
  • the gate may or may not include a valve for isolating the cassette dock 10 from the transfer chamber 14.
  • the cassette dock includes an elevator inside a loadlock.
  • the system includes a second cassette dock 15 for staging wafers in a cassette 16 through a gate 17 which is coupled to the first robotic transfer chamber 14.
  • the first robotic transfer chamber 14 includes a robotic arm 18 for transporting wafers through the valve gates 13 and 17, and through a third gate 19 into a staging chamber 20.
  • the staging chamber 20 includes a plurality of stations for staging wafers into the process modules.
  • a pre-process station 21 and a post- process station 22 are provided for supporting wafers in the staging chamber 20.
  • the staging chamber 20 is coupled to a gate 23 of a second robotic transfer chamber 24.
  • the second robotic transfer chamber includes a plurality of valve gates 25, 26, 27 which are coupled to process chambers 28, 29, 30.
  • a robotic arm 31 in the second robotic transfer chamber 24 transfers wafers from the pre-process station into individual process chambers 28, 29, 30, and out of the process chambers 28, 29, 30, into the post-process station 22 of the staging chamber 20.
  • the robotic arm 18 in the first robotic transfer chamber 14 then completes the transportation of the wafer from the staging chamber 20 into a cassette in a cassette dock 10 or 15.
  • a process support module 32, 33, 34 which is particularly adapted to support a given process in a respective process chamber.
  • a control console 35 made up of a programmable computer, is coupled to the robotic arms 18, 31, the gates 13, 17, 19, 23, 25, 26, 27, the pre- and post- process stations 21, 22, the cassette docks 10, 15, a variety of sensors not shown here, and to the process support modules 32, 33, 34, and controls the transportation of single wafers through the system under program control.
  • a preferred control algorithm is described below with reference to Figs. 4-10.
  • the staging chamber 20 having a plurality of staging stations facilitates the transportation of wafers into the process chambers while avoiding gridlock between ingoing and outgoing wafers.
  • a mechanism 36 comprising monitoring, preparation and/or finishing apparatus is coupled with the staging chamber 20.
  • the mechanism ' 36 is schematically illustrated in Fig. 1, but may comprise any of a variety of systems for monitoring a characteristic of a wafer, preparing the wafer or finishing a process of the wafer sitting in one of the plurality of stations 21, 22 of the staging chamber 20.
  • the apparatus 36 could be a system for detecting cleanliness of the wafer, a system for reading an identifying marker on the wafer for inventory processes, an eyepiece for visual inspection of the wafer, or other characteristic monitoring apparatus known in the art.
  • Examples of "preparation” steps that could be done by mechanism 36 include preparing the wafer to a designated location or orientation, and conditioning or cleaning of the surface of the wafer. Examples of "post" or
  • finishing processes include measuring the result of process, and heating or cooling of the substrate.
  • the mechanism 36 is coupled to the control console 35 providing input to the transportation control system.
  • Fig. 2 illustrates a vertical expansion of the wafer transport system shown in Fig. 1. The reference numbers used in Fig. 1 are repeated for similar elements.
  • the system shown in Fig. 2 includes a first cassette dock 10 and a second cassette dock 15.
  • the cassette 11 of semiconductor wafers 12 is loaded in the cassette dock 10. Also, a cassette 16 of wafers is loaded in dock 15.
  • a first robotic transfer chamber 14 supports a robotic arm 18 which is used to transfer wafers through the gates 13, 18, and 19 of the first robotic transfer chamber 14.
  • the gate 19 is coupled to the staging chamber 20 which includes a plurality 21,
  • the staging chamber 20 is coupled to gate 23 of a second robotic transfer chamber
  • the second robotic transfer chamber 24 includes gates 25, 27 which are coupled to process chambers 28,
  • a gate 100 on the second robotic transfer chamber 24 is coupled to a second staging chamber 101.
  • the staging chamber 101 includes a plurality of staging stations 102, 103.
  • the staging chamber 101 is coupled to a gate 104 on third robotic transfer chamber 105.
  • a robotic arm 106 in the third robotic transfer chamber 105 transfers wafers from the second staging chamber 101 through a plurality of gates 104, 107, 108, 109 to respective process chambers 110, 111, 112.
  • the control console 35 is coupled to the first, second and third robotic transfer chambers 105, 24, 14, other elements of the system, and to the process modules (not shown) which are coupled to each of the process chambers. ' Under program control, wafers are transported through the transportation system to the appropriate process chambers.
  • a wafer can enter from cassette dock 10 and be placed on a pre-process station 21. From station 21, the wafer can be placed in process chamber 28. After processing in chamber 28, the wafer can be transported to staging station 102. From staging station 102, the wafer can be moved into process chamber 110, then process chamber 111, then process chamber 112. From chamber 112, the wafer can be transported to the staging station 103. From staging station 103, the robotic arm 31 in the second robotic transfer chamber 24 can transport the wafer into process chamber 30. From chamber 30, the wafer can be transported to staging station 22. From staging station 22, the wafer can be transported to the outgoing cassette 16 in the cassette dock 15.
  • the wafer transport system includes a cassette dock 200 for supporting a cassette 201 of semiconductor wafers.
  • the cassette dock 200 is coupled to gate 202 of a first robotic transfer chamber 203.
  • First robotic transfer chamber 203 includes a second gate 204 and a third gate
  • the third gate 205 is coupled to a staging chamber 206 having a plurality of wafer staging stations 207, 208.
  • the staging chamber 206 is coupled to gate 209 of a second robotic transfer chamber 210.
  • the second robotic transfer chamber 210 includes a plurality of gates 211, 212, 213 to which respective process chambers 214, 215, 216 are coupled.
  • a robotic arm 217 in the first robotic transfer chamber 203 transfers wafers through the plurality of gates 202, 204, 205 of the first robotic transfer chamber 203.
  • a robotic arm 218 of the second robotic transfer chamber 210 is used to transfer wafers from the staging stations 207, 208 into the process chambers
  • a staging chamber 220 including a staging station 221.
  • the staging chamber 220 is coupled to gate 222 of a third robotic transfer chamber 223.
  • Third robotic transfer chamber 223 includes a second gate 224 coupled to a staging chamber 225 on a second wafer transfer system.
  • the staging chamber 225 includes a staging station 226 for receiving wafers from the third robotic transfer chamber 223.
  • a ' fourth robotic transfer chamber 227 is coupled through gate 228 to the staging chamber 225, and through gate 230 to the cassette dock 229.
  • the staging chamber 231 and fifth robotic transfer chamber 232 are mounted as is described with reference to the parallel system.
  • the control console 240 is coupled to the first system and controls the first, second, and third transfer chambers 203, 210, 223.
  • a second control console 241 is coupled to the third, fourth, and fifth transfer chambers 223, 227, 232.
  • a simple contention algorithm may control operation of the third transfer chamber 223 in order to coordinate the activity of the two parallel systems.
  • a single control console could operate both systems.
  • Figs. 4-10 set out a description of a preferred embodiment of a control algorithm based on petri net theory.
  • Fig. 4 shows the master structure of the control net for moving a wafer from an entry elevator through a process station and back out to the exit elevator.
  • Figs. 5-10 show additional detail of the activities set out in Fig. 4.
  • FIG. 4 an overall view of the control net is shown.
  • the net is begun at Start_Petri point 400 which is passed to the Place Wafer on Entry Stage activity 401 to place the wafer on the entry stage.
  • the output of the activity 401 is a Wafer on the EN STAGE signal 402.
  • the Wafer on EN STAGE signal 402 is passed to the Place Wafer on IA activity 403 of placing the wafer on the inner arm (corresponding to the robotic arm 31 of Fig. 1).
  • the Place Wafer on IA activity 403 is linked to an
  • the Wafer on IA, IA Retracted output 404 of the activity 403 indicates that a wafer is on the inner arm and the inner arm has been retracted. This signal 404 is passed to Place Wafer in PI & Process activity 407 by which the wafer is moved into a process station and processed.
  • the Place Wafer in PI & Process activity 407 is linked to the IA_Free semaphore 408 indicating that the inner arm is free. This semaphore is linked back to activities 403 and 410.
  • the result of Place Wafer in PI & Process activity 407 is a PI Finished Process signal 409 indicating that process station ' l has finished processing the wafer. Signal 409 is passed to Remove Wafer from PI activity 410.
  • This activity 410 is linked to a Pl_Free semaphore 411 which is linked back to the activity 403.
  • the output of the Remove Wafer from PI activity 410 is a Wafer on IA signal 412 indicating that the wafer is on the inner arm. This signal 412 is passed to Place Wafer on Exit Stage then on OA activity 13.
  • the Wafer on OA signal 414 is passed to the Place
  • the Place Wafer on EX ELEV activity 415 is linked to the Ye ⁇ _More_Slot ⁇ semaphore 417 which is linked back to activity 413, and the EX_STG_Free semaphore 418 which is linked back to activity 410. Also, it is linked to the OA_Free semaphore 406.
  • the IA_Free semaphore 408 is linked back to both activities 403 and 410.
  • the OA_Free semaphore 406 is linked back to both activities 401 and 413.
  • Fig. 5 illustrates the Place Wafer on Entry Stage activity 401.
  • Inputs include the Start_Petri signal
  • the output is the Wafer on EN STAGE signal 402.
  • OA Free 406 are supplied to the Ext__OA_EN_ELV0 activity 500. This activity generates an output at point 501 which is coupled to the Stp_Dn_EN_ELEV activity 502.
  • the activity 502 is linked to the Yes_More_Wfrs semaphore 503 and the EN_ELEV_at_Slt semaphore 504.
  • the output of the activity 502 is the Wafer on OA signal 505.
  • the Wafer on OA signal 505 is passed to the Rtr_OA_EN_ELVl activity 506.
  • a signal 507 is passed to the Ext_OA_EN_STGl activity 508.
  • signal 509 is passed to the Rse_EN_STGE activity 510.
  • the Wafer on EN STAGE signal 402 is generated. Fig.
  • Inputs include the Wafer on EN STAGE signal 402, the Pl_Free semaphore 411, and the IA_Free semaphore 408.
  • Outputs include a link to the OA_Free semaphore 406, a link to the EN_STAGE Free semaphore 405, and the Wafer on IA, IA Retracted signal 404.
  • the Wafer on EN STAGE signal 402 is supplied to the Rtr_OA_EN_STG0 activity 600. After the outer arm is retracted from the entry stage, signal 601 is passed to the Ext_IA_EN_STG0 activity 602 and the OA_Free semaphore 406 is updated. If process 1 is free and the inner arm is free as indicated by the respective semaphores 411 and 408, the inner arm is extended to the Entry Stage and the signal 603 is passed to the
  • the entry stage is lowered to pass the wafer to the inner arm and the Wafer on IA signal 605 is passed to the Rtr_IA_EN_STGl activity
  • Fig. 7 illustrates the Place Wafer on PI activity
  • Inputs include the Wafer on IA, IA Retracted signal 404.
  • Outputs include the PI Finished Process signal 409 and a link to the IA_Free semaphore 408.
  • the Wafer on IA, IA Retracted signal 404 is passed to the Opn_P1_GTE_VLV activity 700.
  • Fig. 8 illustrates the Remove Wafer from PI activity 410.
  • the inputs include the PI Finished Process signal 409, the EX_STG_Free semaphore 418, and the IA_Free semaphore 408.
  • Outputs include the Wafer on IA signal 412 and a link to the Pl_Free semaphore
  • the PI Finished Process signal 409 is passed to the Opn_Pl_GTE_VLV activity 800.
  • the signal 801 is passed to the Ext_IA_P10 activity 802. If the Exit Stage is free, and the inner arm is free, then the inner arm is extended into the Process Station to pick up the wafer. When extended, the signal 803 is passed to the Lwr_Pl activity 804. After PI stage is lowered, placing the wafer on the inner arm, the signal 805 is passed to the Rtr_IA_Pll activity 806. After the inner arm is retracted from the Process Station, signal 007 is passed to the Cls_Pl_GTE_VLV activity 808. When the gate valve of Process Station 1 is closed, the Wafer on IA signal 412 is generated. Also, the Pl_Free semaphore 411 is updated.
  • Fig. 9 illustrates the Place Wafer on Exit Stage, then on OA activity 413.
  • Inputs include the Wafer on IA signal 412, the Yes_More_Slots semaphore 417 and the OA_Free semaphore 406.
  • Outputs include the Wafer on OA signal 414 and a lini to the IA_Free semaphore 408.
  • the Wafer on IA signal is passed to the
  • Ext_IA_EX_STG1 activity 900 Once the inner arm is extended to the Exit Stage in the staging chamber, a signal 901 is passed to the Rse_EX_STGE activity 902.
  • the Wafer on EX STAGE signal 905 is passed to the Ext_OA_EX_STG0 activity 906, and the IA_Free semaphore 408 is updated.
  • the outer arm is extended to the Exit Stage and a signal 907 is passed by activity 906 to the Lwr_EX_STGE activity 908.
  • the Exit Stage has been lowered to place the wafer on the outer arm, the Wafer on OA signal 414 is generated.
  • Fig. 10 illustrates the Place Wafer in EX ELEV activity 415.
  • the input includes the Wafer on OA signal 414.
  • Outputs include the End Petri signal 416, a link to the EX_STGE_Free semaphore 418, a link to the Ye ⁇ _More_Slot ⁇ semaphore 417 and a link to the
  • the Wafer on OA signal 414 is passed to the
  • Elevator is raised to lift the wafer off of the outer arm, and the Ye ⁇ _More_Slots semaphore 417 and the Ex_ELEV_at_Slt semaphore 1003 are updated. Also, the End_Petri signal 416 is generated. In addition, a signal 1006 is passed to the Rtr_OA_EX_ELV0 activity 1007. Once the outer arm is retracted from the Exit Elevator, leaving the wafer in the elevator, the OA_Free semaphore 406 is updated.
  • control algorithm is based on the classical Petri net control flow using activities, semaphores, and links between activities and semaphores.
  • the combination of the Petri net control flow and the wafer handling apparatus illustrated with respect to Figs. 1-3, provide a wafer handling system which can maximize the use of the available resources by avoiding gridlock, providing precise control for each activity, and allowing a modular approach to modifying control algorithm to meet the needs of specific process sequences and specific wafer routes to one or more process chambers.
  • an automated single wafer transport system can be used to interface with several process specific chambers, such that a common transport ⁇ y ⁇ tem can be ⁇ hared.
  • the modularity allow ⁇ interchange of process specific chambers on a single transportation system.
  • the flexibility and expansion modularity can be used to accommodate a wide variety of processes.
  • the pre- and post-process stations maximize handling through-put, eliminate gridlock, offer options for material and proce ⁇ verification monitoring, and offer convenient locations for the preparation and/or finishing of wafers in the process sequence.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

Transport commandé par programme de tranches semi-conductrices (12) ou d'autres substrats entre une pluralité de chambres de réaction (28, 29, 30). L'appareil comprend un sas de chargement (10) de cassettes servant à faire entrer une cassette (11) qui contient une pluralité de tranches (12). Une première chambre de transfert (14) possédant une pluralité de portes (13 17 19), dont une est couplée au sas de chargement de cassettes (10), transporte des tranches (12) à travers la pluralité de portes (13, 17, 19). Une deuxième chambre de transfert (24) possède une pluralité de portes (23, 25, 26, 27) reliées à des postes de traitement (28, 29, 30). Une chambre de passage (20) comprend des postes (21, 22) qui servent à faire entrer et sortir les tranches et est reliée par les portes (19, 23) aux premier et deuxième postes de transfert (14, 24). Un premier et un deuxième bras robotiques (18, 31) sont disposés dans les première et deuxième chambres de transfert (14, 24) afin de transporter des tranches (12) entre le sas de chargement (10), la chambre de passage (20) et les postes de traitement (28, 39, 30). Un système de contrôle (36) est monté avec la chambre de passage (20). Le système est modulaire et peut être agrandi verticalement ou horizontalement.
PCT/US1990/004877 1989-09-12 1990-08-28 Systeme automatique de transport de tranches WO1991004213A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US40609889A 1989-09-12 1989-09-12
US406,098 1989-09-12

Publications (1)

Publication Number Publication Date
WO1991004213A1 true WO1991004213A1 (fr) 1991-04-04

Family

ID=23606534

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1990/004877 WO1991004213A1 (fr) 1989-09-12 1990-08-28 Systeme automatique de transport de tranches

Country Status (1)

Country Link
WO (1) WO1991004213A1 (fr)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5364225A (en) * 1992-06-19 1994-11-15 Ibm Method of printed circuit panel manufacture
US5404894A (en) * 1992-05-20 1995-04-11 Tokyo Electron Kabushiki Kaisha Conveyor apparatus
US5445491A (en) * 1991-08-27 1995-08-29 Toshiba Kikai Kabushiki Kaisha Method for multichamber sheet-after-sheet type treatment
US5486080A (en) * 1994-06-30 1996-01-23 Diamond Semiconductor Group, Inc. High speed movement of workpieces in vacuum processing
US5509772A (en) * 1992-01-16 1996-04-23 Commissariat A L'energie Atomique System for the handling and confinement of flat objects in individual boxes
US5558482A (en) * 1992-07-29 1996-09-24 Tokyo Electron Limited Multi-chamber system
EP0904597A1 (fr) * 1996-06-13 1999-03-31 Brooks Automation, Inc. Dispositif a plusieurs niveaux pour traiter un substrat
WO2001059815A2 (fr) * 2000-02-09 2001-08-16 Semitool, Inc. Dispositif et procede de traitement a temperature elevee d'une piece ouvree de micro-electronique
US6420864B1 (en) 2000-04-13 2002-07-16 Nanophotonics Ag Modular substrate measurement system
US6471913B1 (en) 2000-02-09 2002-10-29 Semitool, Inc. Method and apparatus for processing a microelectronic workpiece including an apparatus and method for executing a processing step at an elevated temperature
US6748293B1 (en) 2003-03-24 2004-06-08 Varian Semiconductor Equipment Associates, Inc. Methods and apparatus for high speed object handling
US6780374B2 (en) 2000-12-08 2004-08-24 Semitool, Inc. Method and apparatus for processing a microelectronic workpiece at an elevated temperature
US7244086B2 (en) * 2002-11-15 2007-07-17 Oc Oerlikon Balzers Ag Apparatus for vacuum treating two dimensionally extended substrates and method for manufacturing such substrates
US7347656B2 (en) * 1995-07-19 2008-03-25 Hitachi, Ltd. Vacuum processing apparatus and semiconductor manufacturing line using the same

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4385837A (en) * 1978-05-22 1983-05-31 Irvine Optical Corporation Apparatus and system for linewidth measurements
US4405435A (en) * 1980-08-27 1983-09-20 Hitachi, Ltd. Apparatus for performing continuous treatment in vacuum
US4643629A (en) * 1984-10-30 1987-02-17 Anelva Corporation Automatic loader
US4670126A (en) * 1986-04-28 1987-06-02 Varian Associates, Inc. Sputter module for modular wafer processing system
US4674621A (en) * 1984-10-31 1987-06-23 Anelva Corporation Substrate processing apparatus
US4687542A (en) * 1985-10-24 1987-08-18 Texas Instruments Incorporated Vacuum processing system
US4715764A (en) * 1986-04-28 1987-12-29 Varian Associates, Inc. Gate valve for wafer processing system
US4722298A (en) * 1986-05-19 1988-02-02 Machine Technology, Inc. Modular processing apparatus for processing semiconductor wafers
US4818169A (en) * 1985-05-17 1989-04-04 Schram Richard R Automated wafer inspection system
US4824309A (en) * 1983-11-28 1989-04-25 Hitachi, Ltd. Vacuum processing unit and apparatus
US4825808A (en) * 1986-12-19 1989-05-02 Anelva Corporation Substrate processing apparatus

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4385837A (en) * 1978-05-22 1983-05-31 Irvine Optical Corporation Apparatus and system for linewidth measurements
US4405435A (en) * 1980-08-27 1983-09-20 Hitachi, Ltd. Apparatus for performing continuous treatment in vacuum
US4824309A (en) * 1983-11-28 1989-04-25 Hitachi, Ltd. Vacuum processing unit and apparatus
US4643629A (en) * 1984-10-30 1987-02-17 Anelva Corporation Automatic loader
US4674621A (en) * 1984-10-31 1987-06-23 Anelva Corporation Substrate processing apparatus
US4818169A (en) * 1985-05-17 1989-04-04 Schram Richard R Automated wafer inspection system
US4687542A (en) * 1985-10-24 1987-08-18 Texas Instruments Incorporated Vacuum processing system
US4670126A (en) * 1986-04-28 1987-06-02 Varian Associates, Inc. Sputter module for modular wafer processing system
US4715764A (en) * 1986-04-28 1987-12-29 Varian Associates, Inc. Gate valve for wafer processing system
US4722298A (en) * 1986-05-19 1988-02-02 Machine Technology, Inc. Modular processing apparatus for processing semiconductor wafers
US4825808A (en) * 1986-12-19 1989-05-02 Anelva Corporation Substrate processing apparatus

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5445491A (en) * 1991-08-27 1995-08-29 Toshiba Kikai Kabushiki Kaisha Method for multichamber sheet-after-sheet type treatment
US5509772A (en) * 1992-01-16 1996-04-23 Commissariat A L'energie Atomique System for the handling and confinement of flat objects in individual boxes
US5404894A (en) * 1992-05-20 1995-04-11 Tokyo Electron Kabushiki Kaisha Conveyor apparatus
US5364225A (en) * 1992-06-19 1994-11-15 Ibm Method of printed circuit panel manufacture
US5558482A (en) * 1992-07-29 1996-09-24 Tokyo Electron Limited Multi-chamber system
US5486080A (en) * 1994-06-30 1996-01-23 Diamond Semiconductor Group, Inc. High speed movement of workpieces in vacuum processing
US7347656B2 (en) * 1995-07-19 2008-03-25 Hitachi, Ltd. Vacuum processing apparatus and semiconductor manufacturing line using the same
EP0904597A4 (fr) * 1996-06-13 2007-07-04 Brooks Automation Inc Dispositif a plusieurs niveaux pour traiter un substrat
EP0904597A1 (fr) * 1996-06-13 1999-03-31 Brooks Automation, Inc. Dispositif a plusieurs niveaux pour traiter un substrat
WO2001059815A3 (fr) * 2000-02-09 2002-02-21 Semitool Inc Dispositif et procede de traitement a temperature elevee d'une piece ouvree de micro-electronique
US6471913B1 (en) 2000-02-09 2002-10-29 Semitool, Inc. Method and apparatus for processing a microelectronic workpiece including an apparatus and method for executing a processing step at an elevated temperature
US6861027B2 (en) 2000-02-09 2005-03-01 Semitool, Inc. Method and apparatus for processing a microelectronic workpiece including an apparatus and method for executing a processing step at an elevated temperature
WO2001059815A2 (fr) * 2000-02-09 2001-08-16 Semitool, Inc. Dispositif et procede de traitement a temperature elevee d'une piece ouvree de micro-electronique
US6420864B1 (en) 2000-04-13 2002-07-16 Nanophotonics Ag Modular substrate measurement system
US6780374B2 (en) 2000-12-08 2004-08-24 Semitool, Inc. Method and apparatus for processing a microelectronic workpiece at an elevated temperature
US7244086B2 (en) * 2002-11-15 2007-07-17 Oc Oerlikon Balzers Ag Apparatus for vacuum treating two dimensionally extended substrates and method for manufacturing such substrates
US6748293B1 (en) 2003-03-24 2004-06-08 Varian Semiconductor Equipment Associates, Inc. Methods and apparatus for high speed object handling

Similar Documents

Publication Publication Date Title
WO1991004213A1 (fr) Systeme automatique de transport de tranches
KR100493989B1 (ko) 레지스트처리시스템및레지스트처리방법
US8292563B2 (en) Nonproductive wafer buffer module for substrate processing apparatus
US9884726B2 (en) Semiconductor wafer handling transport
EP0756316B1 (fr) Dispositif de traitement sous vide et ligne de fabrication de semi-conducteurs utilisant ce dispositif
US9417529B2 (en) Coating and developing apparatus and method
EP1860693B1 (fr) Système de traitement de substrat, et procédé de transfert de substrat
KR101184789B1 (ko) 도포, 현상 장치
JP2011049585A (ja) 基板搬送装置及び方法
US8480346B2 (en) Apparatus for loading and unloading semiconductor substrate platelets
EP1096550A1 (fr) Amelioration d'un système de fabrication de semiconducteurs
US7032739B2 (en) Intermediate product carrying apparatus, and intermediate product carrying method
KR100666346B1 (ko) 기판세정장치 및 그 방법
KR100555893B1 (ko) 기판세정장치
JP7347658B2 (ja) 基板処理装置及び基板処理方法
JP3512404B2 (ja) 真空処理装置および試料の真空処理方法
TW202137380A (zh) 基板處理裝置及基板處理方法
TW202234561A (zh) 基板處理裝置及基板處理方法
US6427095B1 (en) Universal multi-tool adapter for reconfiguring a wafer processing line
JPH0722488A (ja) 半導体装置製造工場のウエハ搬送システム
JPH01179413A (ja) 拡散炉ウエハハンドラ装置
US20020154988A1 (en) Microelectronic fabrication tool loading method providing enhanced microelectronic fabrication tool operating efficiency

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP KR

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FR GB IT LU NL SE