WO1991001557A3 - Memoire a acces selectif dynamique avec detection et regeneration ameliorees - Google Patents

Memoire a acces selectif dynamique avec detection et regeneration ameliorees Download PDF

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Publication number
WO1991001557A3
WO1991001557A3 PCT/US1990/003800 US9003800W WO9101557A3 WO 1991001557 A3 WO1991001557 A3 WO 1991001557A3 US 9003800 W US9003800 W US 9003800W WO 9101557 A3 WO9101557 A3 WO 9101557A3
Authority
WO
WIPO (PCT)
Prior art keywords
bit line
transistors
pair
refreshing
random access
Prior art date
Application number
PCT/US1990/003800
Other languages
English (en)
Other versions
WO1991001557A2 (fr
Inventor
Chen Y Wang
Original Assignee
Samsung Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Semiconductor Inc filed Critical Samsung Semiconductor Inc
Priority to KR1019910700301A priority Critical patent/KR0139787B1/ko
Publication of WO1991001557A2 publication Critical patent/WO1991001557A2/fr
Publication of WO1991001557A3 publication Critical patent/WO1991001557A3/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

On utilise dans la présente invention deux paires de transistors amplificateurs de détection à canal n à couplage croisé, fixé entre deux moitiés électriquement équilibrées d'une ligne binaire. Entre chaque paire de transistors amplificateurs de détection à canal n à couplage croisé est disposée uniquement une paire de transistors de rétablissement à canal p, fixés entre la ligne binaire et une ligne binaire de complément. En outre, sur la ligne binaire et sur la ligne binaire de complément, entre une paire de transistors amplificateurs de détection à canal n à couplage croisé et la paire de transistors de rétablissement à canal p, se trouvent des transistors isolants du type à appauvrissement qui isolent encore davantage les moitiés de la ligne binaire et de la ligne binaire de complément.
PCT/US1990/003800 1989-07-20 1990-07-11 Memoire a acces selectif dynamique avec detection et regeneration ameliorees WO1991001557A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910700301A KR0139787B1 (ko) 1989-07-20 1990-07-11 검지 및 리프레시가 개선된 다이내믹 랜덤 액세스 메모리

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/382,581 US4991142A (en) 1989-07-20 1989-07-20 Dynamic random access memory with improved sensing and refreshing
US382,581 1989-07-20

Publications (2)

Publication Number Publication Date
WO1991001557A2 WO1991001557A2 (fr) 1991-02-07
WO1991001557A3 true WO1991001557A3 (fr) 1991-03-07

Family

ID=23509600

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1990/003800 WO1991001557A2 (fr) 1989-07-20 1990-07-11 Memoire a acces selectif dynamique avec detection et regeneration ameliorees

Country Status (5)

Country Link
US (1) US4991142A (fr)
EP (1) EP0435997A1 (fr)
JP (1) JPH04501631A (fr)
KR (1) KR0139787B1 (fr)
WO (1) WO1991001557A2 (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE40552E1 (en) 1990-04-06 2008-10-28 Mosaid Technologies, Inc. Dynamic random access memory using imperfect isolating transistors
GB9007789D0 (en) 1990-04-06 1990-06-06 Foss Richard C Method for dram sensing current control
KR950009234B1 (ko) * 1992-02-19 1995-08-18 삼성전자주식회사 반도체 메모리장치의 비트라인 분리클럭 발생장치
US5388072A (en) * 1992-04-10 1995-02-07 International Business Machines Corporation Bit line switch array for electronic computer memory
US5475642A (en) * 1992-06-23 1995-12-12 Taylor; David L. Dynamic random access memory with bit line preamp/driver
US5907516A (en) * 1994-07-07 1999-05-25 Hyundai Electronics Industries Co., Ltd. Semiconductor memory device with reduced data bus line load
US5796671A (en) 1996-03-01 1998-08-18 Wahlstrom; Sven E. Dynamic random access memory
US5835433A (en) * 1997-06-09 1998-11-10 Micron Technology, Inc. Floating isolation gate from DRAM sensing
US5862089A (en) * 1997-08-14 1999-01-19 Micron Technology, Inc. Method and memory device for dynamic cell plate sensing with ac equilibrate
US5875141A (en) * 1997-08-14 1999-02-23 Micron Technology, Inc. Circuit and method for a memory device with P-channel isolation gates
DE102007042879B3 (de) * 2007-09-08 2009-06-10 Qimonda Ag Speichervorrichtung mit Bewertungsschaltung für die elektrische Ladung einer Speicherzelle

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0239225A2 (fr) * 1986-02-26 1987-09-30 Mitsubishi Denki Kabushiki Kaisha Dispositif de mémoire semi-conductrice
EP0278155A2 (fr) * 1987-02-10 1988-08-17 Mitsubishi Denki Kabushiki Kaisha Mémoire RAM-dynamique

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4658877A (en) * 1985-03-11 1987-04-21 The Scott & Fetzer Company Lock mechanism for retractable awning
JPH07111823B2 (ja) * 1986-03-18 1995-11-29 三菱電機株式会社 半導体記憶装置
JPS63898A (ja) * 1986-06-19 1988-01-05 Fujitsu Ltd 半導体記憶装置
US4819207A (en) * 1986-09-30 1989-04-04 Kabushiki Kaisha Toshiba High-speed refreshing rechnique for highly-integrated random-access memory
KR890002812B1 (ko) * 1986-11-28 1989-07-31 삼성전자 주식회사 씨모오스 디램에서 레이아웃이 최적화된 감지증폭기
JPS63309265A (ja) * 1987-06-11 1988-12-16 Shionogi & Co Ltd カプセル充填重量制御方法および制御装置
US4816706A (en) * 1987-09-10 1989-03-28 International Business Machines Corporation Sense amplifier with improved bitline precharging for dynamic random access memory

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0239225A2 (fr) * 1986-02-26 1987-09-30 Mitsubishi Denki Kabushiki Kaisha Dispositif de mémoire semi-conductrice
EP0278155A2 (fr) * 1987-02-10 1988-08-17 Mitsubishi Denki Kabushiki Kaisha Mémoire RAM-dynamique

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IEEE Journal of Solid-State Circuits, Vol. SC-21, No. 3, June 1986, IEEE, (New York, US), K. KIMURA et al.: "Power Reduction Techniques in Megabit DRAM's", pages 381-389, see page 382, right-hand column, line 30 - page 383, right-hand column, line 2; figure 4 *
IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 5, October 1987, IEEE, (New York, US), H. MIYAMOTO et al.: "A Fast 256K X 4 CMOS DRAM with a Distributed Sense and Unique Restore Circuit", pages 861-867, see page 862, left-hand column, line 10 - page 863, left-hand column, line 25; figure 4 *

Also Published As

Publication number Publication date
JPH04501631A (ja) 1992-03-19
KR0139787B1 (ko) 1998-07-15
KR920701977A (ko) 1992-08-12
EP0435997A1 (fr) 1991-07-10
US4991142A (en) 1991-02-05
WO1991001557A2 (fr) 1991-02-07

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