WO1990005951A1 - Methode de traitement des interruptions anormales de logiciel involontaires - Google Patents

Methode de traitement des interruptions anormales de logiciel involontaires Download PDF

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Publication number
WO1990005951A1
WO1990005951A1 PCT/US1988/004061 US8804061W WO9005951A1 WO 1990005951 A1 WO1990005951 A1 WO 1990005951A1 US 8804061 W US8804061 W US 8804061W WO 9005951 A1 WO9005951 A1 WO 9005951A1
Authority
WO
WIPO (PCT)
Prior art keywords
task
interrupt
program
user
exception
Prior art date
Application number
PCT/US1988/004061
Other languages
English (en)
Inventor
Heinrich Hummel
Original Assignee
Heinrich Hummel
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Heinrich Hummel filed Critical Heinrich Hummel
Priority to PCT/US1988/004061 priority Critical patent/WO1990005951A1/fr
Publication of WO1990005951A1 publication Critical patent/WO1990005951A1/fr

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1441—Resetting or repowering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers

Definitions

  • the invention refers to a method of handling software interrupt exceptions which are not caused on purpose but occur due to errorprone programs that are particularly processed on the INTEL-8028B (TM) or INTEL-80386 (TM) processor in case these processors operate in the so called PROTECTED MODE, whereby its basic principle can also be applied to the exception handling of unintended (software interrupt) exceptions of any other existing exception-detecting processor e.g. like MOTOROLA'S 68020 (TM) and whereby the method may even give the incentive for creating enhanced hardware processors that do support this method as well.
  • TM INTEL-8028B
  • TM INTEL-80386
  • TM INTEL 80286
  • TM INTEL 80286
  • interrupt 0 - Division by zero
  • interrupt 4 - INTO -detected overflow
  • interrupt 5 - exceeding a boundary range
  • interrupt 8 - double faults
  • interrupt 12 - stack errors
  • interrupt 13 all kind of errors that can be categorized as general protection errors (known as interrupt 13),
  • interrupt 16 - processor extension errors
  • this invention pursues to call a user task specific exception handler (see literature "INTEL 286 Operating System Writer's Guide” page 6-7 to 6-9) however claiming novelty for the way to do so highlighted by the execution of the interrupt return instruction before the user task specific exception handler has even been called.
  • the task gate may refer to a task descriptor in the global descriptor table, which will refer to a task state segment, which will refer to an interrupt task program.
  • This interrupt task program may save all data about the occurance of the exception, like the total stack segment of the interrupted task as well as the contents of its task state segment (which means essentially all register values), for a later failure report - which is reasonable but not significant for this invention -, then using the ALIAS-descriptor technique modify the task state segment of the interrupted task, particularly - the fields for CS and IP so that by executing the interrupt return instruction the interrupted task would continue at a system central address, let's call it Z,
  • the interrupt task program must also clear the TASK_SWITCHED bit in the machine status word.
  • the interrupt task program or programs that is or that are reached via the task gates for exception 6, 12, 13 must also pop the error code from the stack of the interrupt task prior switching back to the previously interrupted task.
  • the user task specific exception handler is to be called (its address may be stored in the registers BX and CX), eventually provided with the input (parameter) of the address of the datasegment that contains the data about the occurance of the exception, unless the user task hasn't been assigned the address of a specific exception handler.
  • a system master exception handler program may be called, by using a task gate, to provide more general reaction service.
  • the user task specific exception handler is supposed to investigate the current situation and deal with the problem appropriately, to do this in the adequate logical level (normally in the used high level programming language), then to determine the best suitable point of the task's program, let's call it a recovery point, and to "dump" there, not oust by setting code segment register (CS) and instruction pointer register (IP) to that point's address but by loading all stack data and all register values (inclusively CS and IP at last) as has been actual when the task's program flow passed that point the last time.
  • This kind of "dump" must have been supported by the user's program when it passed that program address in the regular processing by writing all the data, i.e.
  • Operating System service routines that are to be provided to the user, e.g. to "define a recovery point", which essentially means to save the actual register and stack values in a retrievable way, or to “dump to a recovery point”, which means to retrieve and load these values into registers and stack, or to initialize involved data.

Abstract

Des interruptions anormales de logiciel involontaires détectées par les microprocesseurs INTEL-80286 (R) ou INTEL-80386 (R) fonctionnant en mode protégées et connues sous la forme d'interruptions 0, 4, 5, 6, 8, 12, 13, 16 sont traitées en utilisant exclusivement des portes-tâches, en modifiant le segment-état-tâche de la tâche interrompue pendant que se déroule celle-ci, de sorte qu'APRES exécution de l'instruction de retour à un central du système, on peut faire intervenir le programme de traitement d'anomalies spécifiques à la tâche de l'utilisateur, et en utilisant une méthode pour sortir du programme de traitement d'anomalies spécifiques à la tâche de l'utilisateur afin de reprendre le fonctionnement normal à un stade approprié dans le programme que la tâche a déjà dépassé avant que se produise l'anomalie, qui consiste essentiellement à sauvegarder et à rapatrier toutes les valeurs de registre et les données empilées qui existaient au moment où la tâche a dépassé ce stade lors du traitement normal. Le même principe s'applique à d'autres processeurs dotés de capacité de détection d'anomalies. Un processeur futuriste est conçu qui fournit des instructions pour affecter des programmes de traitement d'anomalies spécifiques à la tâche de l'utilisateur pour créer et revenir à un stade ou point de récupération.
PCT/US1988/004061 1988-11-14 1988-11-14 Methode de traitement des interruptions anormales de logiciel involontaires WO1990005951A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/US1988/004061 WO1990005951A1 (fr) 1988-11-14 1988-11-14 Methode de traitement des interruptions anormales de logiciel involontaires

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1988/004061 WO1990005951A1 (fr) 1988-11-14 1988-11-14 Methode de traitement des interruptions anormales de logiciel involontaires

Publications (1)

Publication Number Publication Date
WO1990005951A1 true WO1990005951A1 (fr) 1990-05-31

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1988/004061 WO1990005951A1 (fr) 1988-11-14 1988-11-14 Methode de traitement des interruptions anormales de logiciel involontaires

Country Status (1)

Country Link
WO (1) WO1990005951A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0532334A2 (fr) * 1991-09-11 1993-03-17 International Business Machines Corporation Redressement d'erreur dans un système de traitement de l'information
US7305712B2 (en) 2002-11-18 2007-12-04 Arm Limited Security mode switching via an exception vector
US7849310B2 (en) 2002-11-18 2010-12-07 Arm Limited Switching between secure and non-secure processing modes

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4205370A (en) * 1975-04-16 1980-05-27 Honeywell Information Systems Inc. Trace method and apparatus for use in a data processing system
US4535456A (en) * 1982-02-26 1985-08-13 Robert Bosch Gmbh Method of detecting execution errors in program-controlled apparatus

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4205370A (en) * 1975-04-16 1980-05-27 Honeywell Information Systems Inc. Trace method and apparatus for use in a data processing system
US4535456A (en) * 1982-02-26 1985-08-13 Robert Bosch Gmbh Method of detecting execution errors in program-controlled apparatus

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0532334A2 (fr) * 1991-09-11 1993-03-17 International Business Machines Corporation Redressement d'erreur dans un système de traitement de l'information
EP0532334A3 (en) * 1991-09-11 1993-11-24 Ibm Error recovery in an information processing system
US7305712B2 (en) 2002-11-18 2007-12-04 Arm Limited Security mode switching via an exception vector
US7849310B2 (en) 2002-11-18 2010-12-07 Arm Limited Switching between secure and non-secure processing modes

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