Classifications

• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
  • G09G3/3611—Control of matrices with row and column drivers
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
  • H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
  • H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
  • H04N3/12—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by switched stationary formation of lamps, photocells or light relays
  • H04N3/127—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by switched stationary formation of lamps, photocells or light relays using liquid crystals
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2320/00—Control of display operating conditions
  • G09G2320/02—Improving the quality of display appearance
  • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/2007—Display of intermediate tones
  • G09G3/2011—Display of intermediate tones by amplitude modulation
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/2007—Display of intermediate tones
  • G09G3/2014—Display of intermediate tones by modulation of the duration of a single pulse during which the logic level remains constant
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/2007—Display of intermediate tones
  • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
  • G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
  • G09G3/2025—Display of intermediate tones by time modulation using two or more time intervals using sub-frames the sub-frames having all the same time duration

Definitions

• This invention relates to a method for gen ⁇ erating gray scales for a flat panel display.
• gray scales are generated by turning the pixels in a display on for at least a baseline time in order to reduce flicker at a monochrome display.
• Fig. 1A Personal computing systems, such as the one shown in Fig. 1A, employ an ever increasing number and types of display devices. Those systems commonly in ⁇ clude a central processing unit 4 which drives a video controller 6. Controller 6 interacts with a memory 8 to generate video control information. The video con ⁇ trol information is usually coupled through a digital to analog converter 10 to drive an analog display 14 or through a buffer 12 to drive a digital display 16.
• U.S. Patent No. 4, 688,031 describes the use of color masks having different repetitive dot patterns for even and odd number rows to generate gray scales corresponding to different colors.
• U.S. Patent No. 4,703,318 describes a method of forming a monochromatic image from a digital rep- resentation by replacing background and foreground colors with patterns of light and dark dots.
• the invention is a controller and method for providing 0 to N gray scales at a monochrome display.
• the monochrome display is of the type having an array of pixels energized by a display voltage over time to generate the gray scales.
• the controller generates a baseline time and uses the baseline time to provide gray scales at the display.
• each pixel is energized at least the baseline time for any gray scale above level 0 to reduce flicker in the display.
• the baseline time corresponds to a point on the intensity response curve for the display at which the display exhibits a linear intensity response for a given display voltage versus time.
• Figs. IB-ID are stylized illustrations of methods for generating gray scales according to the prior art
• Fig. 5 illustrates the pixel on/off pattern using frame rate control according to one embodiment of the invention.
• Fig. 6 is a block diagram of a pulse width modulation circuit for generating gray scales according to one embodiment of the invention.
• Fig. 7 is an illustration of weight clock information generated by a pulse width modulation cir ⁇ cuit according to one embodiment of the invention.
• DETAILED DESCRIPTION OF THE INVENTION the invention is a con ⁇ troller for generating gray scales for a flat panel display.
• the invention includes the use of two tech- niques for generating gray scales in view of the prob ⁇ lems encountered by the prior art.
• the control ⁇ ler uses a baseline time such that for any gray scale greater than 0, the pixels in the display will be on for at least the base line time.
• the base line time is chosen to be long enough such that flicker is effec ⁇ tively eliminated at the display.
• the invention also offers a plurality of al ⁇ ternative circuits for generating gray scales. More ⁇ over, these circuits may be selected and programmed depending on the identity of the display device, and therefore the intensity response characteristics of the particular display, used in the processing system.
• Fig. 1A shows a conventional data processing system 2 having analog and flat panel display capability.
• Conventional processing system 2 includes a central processing unit 4 that drives a controller 6.
• Controller 6 interacts with a memory 8 and outputs digital video control information to a digital to analog converter 10 for driving an analog display such as a CRT 14.
• Controller 6 can also output digital video control information to a buffer circuit 12 for driving a digital display 16 such as a flat panel display.
• Prior art display systems have typically utilized three techniques for generating gray scales at a monochrome display to applicants' knowledge.
• An analog technique as graphically shown in Fig. IB, uses the technique of applying different voltage levels for the same period of time to generate different intensity levels for the pixels in a display. Pulse width modulation techniques as shown illustratively in Fig.
• the intensity response of each such liquid crystal device with respect to voltage and time is different.
• the liq ⁇ uid crystal displays are known to be non-linear for an initial energization period. That is to say, during some initial units of time, any increase in the time for which a display voltage is applied will not give a corresponding marginal increase in the intensity of display.
• these intensity response curves for flat panel displays do have the known characteristic of transitioning from this non-linear response to a linear response after a certain time. Thereafter, for each unit of time for which the display voltage is applied, there will be a corresponding unit increase in the level of intensity of display. This period of time is referred to hereinafter as the linear transition time of the intensity response curve.
• the baseline time for level 1 through level N is chosen to be equal to or greater than this linear transition time.
• Fig. 3 shows one embodiment of a data processing system 2 having a controller 6 according to one embodiment of the invention.
• Controller 6 includes a frame rate control circuit, a pulse width modulation circuit and/or a black/white circuit for generating gray scales while resolving the aforementioned problems of the prior art.
• clock generator circuit 22 provides clock information to a frame rate control circuit 28, a pulse width modulation circuit 30, and a black/white circuit 32.
• sync generator circuit 24 provides sync information to frame rate control circuit 28, pulse width modulation circuit 30, and black/white circuit
• the color generation circuit 26 provides digital color information to frame rate control circuit 28, pulse width modulation circuit 30, and black/white circuit 32.
• the baseline time is encoded in a frame number and color value table in frame rate control circuit 28.
• the table may be conventionally implemented in hardware as a programmable logic array, ROM, or with random logic.
• registers 20 generate baseline time information which is provided to pulse width modulation circuit 30 and black/white control circuit 32 to generate gray scale control information. It should be understood that registers 20 could also provide baseline time information to FRC circuit 28 as an alternative embodiment of the invention.
• Frame rate control circuit 28 outputs pixel on/off data to a flat panel display 16.
• the pulse width modulation circuit 30 outputs weighted clock in- formation to panel 16.
• Black/white circuit 32 outputs pixel data to panel 16.
• Panel 16 is also fed clock information from clock generator 22, sync information from sync generators 24, and digital color information from color generator 26.
• baseline time in ⁇ formation is provided internally within frame rate control circuit 28 and registers 20 provide baseline time information to pulse width modulation circuit 30 and black/white circuit 32.
• pixels are on for at least the baseline time in order to minimize flicker at the display.
• the level 1 gray scale is typically on for one frame according to the prior art.
• Fig. 4 is a block diagram of frame rate control circuit 28 for generating gray scale control information according to one embodiment of the invention.
• Frame rate control circuit 28 outputs pixel on/off data in selected patterns to provide gray scales at panel 16.
• Frame rate control circuit 28 receives vertical sync information, four-bit digital color information, pixel clock information, horizontal sync information. Circuit 28 outputs pixel on/off data.
• the vertical sync information is provided to a frame counter 50 which provides a frame number as output to an algorithm generator 60.
• the algorithm generator can be a RAM, a ROM, a PLA, or a similar conventional device.
• Baseline time information is generated internally from a table in algorithm generator 60 but could be provided from a register (not shown) in a pro ⁇ grammable embodiment.
• the four-bit digital color in ⁇ formation is provided to a decoder 52. Decoder 52 out ⁇ puts gray scale identification information to algorithm generator 60.
• Pixel clock information is received in a divide-by-two circuit 54.
• Divide-by-two circuit 54 outputs clock information to a row column circuit 58.
• Horizontal sync information is received at another divide-by-two circuit 56.
• Divide-by-two circuit 56 outputs sync information to row column circuit 58.
• Row column circuit 58 outputs pixel position information that indicates whether or not the pixel is in an odd or even row and an odd or even column.
• the baseline information (which is built into the algorithm generator in one embodiment) , the frame identification information, the gray scale information and the pixel position information are used by al- gorithm generator 60 to generate pixel on/off data.
• the pixel on/off data determines for a given frame and a given gray scale the on/off status of a pixel identified by the pixel position data.
• the baseline information is used to ensure that the display will be energized for at least the baseline time if the identified gray scale is level 1 or greater.
• Panel 16 also uses back plane clock information as occurs in a conventional panel.
• the display may also be segregated by pixel position infor- ation such that pixels in certain rows and columns will be on for three frames and pixels in other rows and columns will be on for three frames.
• flicker is even further reduced.
• One skilled in the art will readily appreciate in view of this disclosure that other patterns can be used within the scope of the invention.
• the number of frames for the frame control circuit is chosen to be an odd number of frames.
• the number of frames can be chosen to be the number of base line time units, B, plus the number of gray scale levels N, i.e., B+N, if B+N is odd.
• Fig. 6 shows a pulse width modulation circuit that includes a weight clock generator 30.
• Weight clock generator 30 receives clock information from registers 20. This input clock information includes weight base information, weight pitch information, and other such clock information. This clock information is used to define the number of pulses, pulse width, and other characteristics of the weighted clock signal provided as output from circuit 30.
• Weight clock generator 30 also receives horizontal sync information from sync hardware (not shown) . Weight clock generator 30 outputs the weighted clock information to panel 16. Panel 16 also receives back plane clock information and four bit digital color information. Panel 16 may be a conventional panel and uses input weight clock information, back plane clock information, and four bit digital color information to generate gray scales according to conventional techniques.
• Fig. 7 shows a weight clock signal for providing gray scale control information to panel 16 according to one embodiment of the invention.
• the weight clock signal includes an initial weight base and a succession of clock pulses. Each clock pulse has a duration defined by the weight pitch. The total number of clock pulses is varied depending on the number of gray scales.
• a weight base which corresponds to the baseline information, is provided to weight clock generator 30 to ensure that, for level 1 gray scales and higher, the pixels in the display will be on for a time greater than the duration of the weight base.
• the weight base is programmable by registers 20.
• the weight pitch and the number of pulses can also be programmable by registers 20.
• the weight base, the weight pitch and the number of pulses can be programmed to match the intensity response characteristics and the flicker characteristics of a particular display.
• Controller 6 also includes a black/white circuit 32.
• Black/white circuit 32 is included to provide simple black/white display at panel 16.
• Black/white circuit 32 may be a conventional comparator circuit that compares the digital color in ⁇ put signal to a threshold. Where the digital color information exceeds the threshold, the pixel data out ⁇ put causes a black display at panel 16. Where the dig ⁇ ital color information is less than the threshold, the pixel data causes a white display at panel 16.
• the frame rate control circuit the pulse width modulation circuit, and the black/white circuit can be assembled using con ⁇ ventional controller components by one skilled in the art.
• Fig. 2 includes a frame rate control circuit, a pulse width modulation circuit, and a black/white circuit
• a frame rate control circuit or pulse width modulation circuit or a black/white circuit only may be included in a controller having the baseline time programmable.
• pixel on/off data may have patterns simpler or more complicated than the pat ⁇ tern shown in Fig. 5.
• different weight clock information can be generated for a pulse width modulation system within the scope of the invention.

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• Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Crystallography & Structural Chemistry (AREA)
• Chemical & Material Sciences (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Multimedia (AREA)
• Signal Processing (AREA)
• Control Of Indicators Other Than Cathode Ray Tubes (AREA)
• Controls And Circuits For Display Device (AREA)
• Liquid Crystal Display Device Control (AREA)
• Liquid Crystal (AREA)

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Publications (1)

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ID=22928452

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Cited By (5)

Citations (17)

• 1989
  • 1989-09-08 WO PCT/US1989/003893 patent/WO1990003023A1/en unknown
  • 1989-09-08 KR KR1019900701022A patent/KR900702501A/ko not_active Application Discontinuation
  • 1989-09-14 JP JP1239489A patent/JPH02110494A/ja active Pending

Patent Citations (17)

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